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FPGA design from scratch. Part 6 FPGA design from scratch. Part 7
Posted at 07:41 am by svenand
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FPGA design from scratch. Part 8
Before we start synthesizing the design, let's make sure we have a clean design that won't give us any problems. We will use the HDL Analysis and Lint (HAL) tool from Cadence to check our design. There are other tools available like, Spyglass from Atrenta, Indigo RTL Analysis from Blue Perl Software and Leda from Synopsys. We will use HAL because it is an efficient tool and it is part of the Incisive HDL simulator toolbox.
Using HAL
The first thing we will do is to read the HAL user guide to find out more about the program.
To open the user guide execute the following command: xpdf /cadence_install_dir/doc/hal/hal.pdf &
I have problems using the Cadence documentation system cdsdoc. I much prefer to read the pdf files using a standard PDF viewer like xpdf. To read the HAL reference manual use the following command: xpdf /cadence_install_dir/doc/halref/halref.pdf &
Introduction
This text is taken from the HAL user guide: "Functional closure in the ever-shrinking design cycles is achievable only by catching issues as early and as rapidly as possible. Design verification engineers need detection of problems related to multiple phases of design cycle, while the design is still under development at the RTL level. Such early warnings are a key to avoiding the expensive design iterations, and meeting quality and time-to-market goals. HAL checks the design for:
- Design consistency, reusability and portability
- Semantic correctness
- Synthesizability
- Testability and more"
Beautiful words let's see how good it is in reality. The flow diagram shows the two ways you can use HAL. The snapshot-based flow and the source file-based flow. We will use the snapshot-based flow.
Here is the complete HAL flow:
- Compile the design blocks into a library (design)
- Elaborate the design and save the result in a snapshot file (ETC_snapshot)
- Start hal using the following command: hal design.ETC_snapshot
- HAL will execute and the result will be stored in a log file: hal.log
- To analyze the result start ncbrowse using the following command: ncbrowse -sortby severity -sortby category -sortby tag hal.log
We can use Mongoose (see Zoo Design Platform) to run the HDL analysis using HAL. But before we do let's save the current setup using the Load/Save Setup window.
We will save the current setup in the file ETC_simulation.setup and then create a new setup called ETC_analysis.setup to be used during the HAL runs. When we want to return to the simulation setup we will load ETC_simulation.setup and everything in Mongoose will be restored. This way we can handle a new task in Mongoose without interfering with other tasks.
This time we will only elaborate the design files and exclude the testbench. Let's change the top entity to ETC and give a name to the snapshot file : ETC_snapshot.
Select IUS/Elaboration from the Tool menu and start the elaboration:
ncelab: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Elaborating the design hierarchy:
Caching library 'design' ....... Done
Caching library 'std' ....... Done
Caching library 'synopsys' ....... Done
Caching library 'ieee' ....... Done
Caching library 'ambit' ....... Done
Caching library 'vital_memory' ....... Done
Caching library 'ncutils' ....... Done
Caching library 'ncinternal' ....... Done
Caching library 'ncmodels' ....... Done
Caching library 'cds_assertions' ....... Done
Caching library 'sdilib' ....... Done
Caching library 'macrolib' ....... Done
Building instance overlay tables: .................... Done
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 10 8
Registers: 340 211
Scalar wires: 154 -
Vectored wires: 33 -
Always blocks: 94 60
Initial blocks: 6 3
Cont. assignments: 63 71
Timing checks: 16 -
Simulation timescale: 1ps
Writing initial simulation snapshot: design.ETC_snapshot:module
Select HAL from the Tool menu and start the HAL run.
hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options: design.ETC_snapshot:module.
hal: Snapshot: design.ETC_snapshot:module.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Sat Jan 13 00:16:31 CET 2007.
Performing lint checks
....................
Performing synthesizability checks
.
Analysis summary :
Errors : (2)
METAEQ (2)
Warnings : (2082)
BADSYS (24) BITUSD (6) CDEFCV (7) CNSTLT (152)
CONSTC (44) CTLCHR (404) DIRRNG (9) FNAVPC (5)
IGNDLY (4) IMPTYP (91) INIMEM (5) INPASN (2)
INTTOB (16) LCVARN (206) LEXPGM (1) MAXLEN (193)
MEMSIZ (2) METACO (2) MPCMPE (9) MULOPR (16)
NEQPRM (33) NESTIF (1) NETDCL (20) NOBLKN (49)
NOSPEC (1) NOTECH (1) OBMEMI (8) POIASG (60)
PRMNAM (1) PRMSZM (6) SEPLIN (274) STYVAL (110)
SYNTXZ (26) UCCONN (150) UELASG (34) UELOPR (24)
ULRELE (33) UNCONN (13) URAREG (19) URDPRT (1)
URDWIR (4) USEFTN (3) USEPAR (10) VERREP (3)
Notes : (90)
ALOWID (11) DECLIN (4) IDLENG (75)
Analysis failed.
Oophs! 2 errors and 2082 warnings. That's a lot of errors and warnings. Let's open the NCBrowse tool to analyze what is going on. Use the command: ncbrowse -sortby severity -sortby category -sortby tag hal.log &. Why not add this command to a user defined button. See previous chapter for a description.
A look at the log file reveals that the Xilinx memory is a behavioral verilog model that generates the two errors and many of the warnings we see. We have to exclude the memory from the analysis by adding this code in the design_info file (see HAL User Guide):
bb_list
{
designunit = ETC_DUAL_PORT_1024x32;
file = /home/svenand/root/projects/ETC/design/ETC_DUAL_PORT_1024x32.v;
}
This code will blackbox the memory and everything inside the memory block. When we rerun hal with the design_info file included we get the following result:
hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options: -cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds.lib -logfile /home/svenand/root/projects/ETC/verification/hal/log/hal.log -File hal/script/etc_hal.script.
hal: Snapshot: design.ETC_snapshot.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Sun Jan 14 00:42:26 CET 2007.
Performing lint checks
...........
Performing synthesizability checks
.
Analysis summary :
Warnings : (821)
BITUSD (6) CDEFCV (7) CNSTLT (36) CTLCHR (77)
DIRRNG (8) IMPTYP (25) LCVARN (182) MAXLEN (103)
MPCMPE (1) NESTIF (1) NETDCL (20) NOBLKN (12)
POIASG (25) SEPLIN (127) STYVAL (97) UCCONN (93)
URDPRT (1)
Notes : (73)
ALOWID (11) IDLENG (62)
Analysis failed.
We have go through the remaining warnings and see which ones can be ignored and which ones we have to investigate further.
| Warning | Description | Comment | Ignored | | BITUSD | Unused bits inside a always block
| | No | | CDEFCV | Redundant default clause used
| | No | | CNSTLT | Literal '3'b1' should be replaced with a constant
| | Yes | | CTLCHR | Control characters in the source code found (tabs)
| | Yes | | DIRRNG | Inconsistent ordering of bits [0:31]
| OPB bus swapped
| Yes | | IMPTYP | Implicit type conversion
| | No | | LCVARN | Uppercase characters used for names
| I prefer upper case
| Yes | | MAXLEN | Lines too long (more than 80 charcters)
| | Yes | | MPCMPE | Complex expressions, should add parentheses
| | No | | NESTIF | A nested if, in which the same variable is used in if comparisons, has been detected
| | No | | NETDCL | Declarations made prior to non-declarative statements
| I will move the parameter statements
| No | | NOBLKN | Always blocks not labeled
| | Yes | | POIASG | Overflow not verified
| Counters will always wrap-around
| Yes | | SEPLIN | Use a separate line for each HDL statement
| | Yes | | STYVAL | Numeric value used for identifier
| | Yes | | UCCONN | Lowercase characters used for identifier
| | Yes | | URDPRT | Unconnected port
| | No | HAL setup window:
After disabling the warnings we decided to ignore, here is the final result. I will take a closer look at these warnings and make the changes needed to get the design to pass HDL analysis.
We are then ready for the final synthesis run.
hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options: -cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds.lib -logfile /home/svenand/root/projects/ETC/verification/analysis/log/hal.log -File /home/svenand/root/projects/ETC/verification/analysis/script/etc_hal.script.
hal: Snapshot: design.ETC_snapshot.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Mon Jan 15 10:06:44 CET 2007.
Performing lint checks
...
Performing synthesizability checks
.
Analysis summary :
Warnings : (61)
BITUSD (6) CDEFCV (7) IMPTYP (25) MPCMPE (1)
NESTIF (1) NETDCL (20) URDPRT (1)
Notes : (73)
ALOWID (11) IDLENG (62)
Analysis failed.
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Posted at 02:52 pm by svenand
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FPGA design from scratch. Part 9 FPGA design from scratch. Part 10
It took longer than expected to finalize the verification phase but I think we can regain this lost time when we start debugging the real design. Hopefully we will not have that many bugs left in the design. We are now ready for the final synthesis runs.
Synthesis with timing constraints
Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL) or behavioral) is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.
The synthesis is part of the design closure process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives. A constraint is a design target that must be met in order for the design to be considered successful. For example, a chip may be required to run at a specific frequency in order to interface with other components in a system. Other constraints can be the power consumption and the chip size.
Designing an embedded system design in an FPGA that meets all timing requirements, starts already in the planing phase and continues throughout the whole project. Here are some important steps in achieving design closure.
- Understanding the differences between ASIC and FPGA
- System analysis and design partitioning
- RTL design for FPGA
- Synthesizing using the "right" timing constraints.
- Floor planing critical parts of the design
- Place and route and pin placement
Here is an article from Altera describing the differences between ASIC and FPGA design. From Altera you can also download the ASIC to FPGA Design Methodology & Guidelines.
In our design the only constraints we have are timing constraints for input and output signals. The design will operate at a maximum clock frequence of 54 MHz .This will be easily met in the Virtex-4 FPGA family.
We will use the Xilinx synthesis tool XST because it is part of the Integrated Software Environment (ISE) and it is free. Here is an interesting article form FPGA Journal about "free" synthesis tools, how good are they. Other synthesis tools we could have used can be found in this table:
Before we start the synthesis run, let's take a look in the XST User Guide and the FAQ.
XST is a Xilinx tool that synthesizes HDL designs to create Xilinx specific netlist files called NGC files. The NGC file is a netlist that contains both logical design data and constraints that takes the place of both EDIF and NCF (Netlist Constraints File) files. This manual describes XST support for Xilinx devices, HDL languages and design constraints. The manual also explains how to use various design optimization and coding techniques when creating designs for use with XST. We can choose to run XST from the command line or from inside the Project Navigator. Let's start the Project Navigator and follow these instructions.
=> ise &
After the synthesis the ISE project directory looks like this:
The synthesis report file
The Synthesis Report file is called <ETC.syr>, let's take a look at it. We can see that the synthesis was successful, that the timing looks good and that the device utilization is about 10%. We could have used a smaller FPGA.
Timing Summary:
---------------
Speed Grade: -12
Minimum period: 5.839ns (Maximum Frequency: 171.250MHz)
Minimum input arrival time before clock: 5.433ns
Maximum output required time after clock: 6.491ns
Maximum combinational path delay: 8.409ns
Device utilization summary:
---------------------------
Selected Device : 4vfx12ff668-12
Number of Slices: 601 out of 5472 10%
Number of Slice Flip Flops: 570 out of 10944 5%
Number of 4 input LUTs: 1113 out of 10944 10%
Number of IOs: 129
Number of bonded IOBs: 109 out of 320 34%
Number of GCLKs: 2 out of 32 6%
What else can we find out from the synthesis report file
The memory blocks are black boxed:
WARNING:Xst:2211 - "../../design/ETC_DUAL_PORT_1024x32.v" line 327:
Instantiating black box module <ETC_DUAL_PORT_1024x32>.
WARNING:Xst:2211 - "../../design/ETC_DUAL_PORT_1024x32.v" line 339:
Instantiating black box module <ETC_DUAL_PORT_1024x32>.
Black box instantiation
A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format. Synthesis tools will generally report some kind of warning when a black box (this is, an instantiated component with no associated VHDL code) is detected.
Examples of black boxes include:
- CORE Generator modules (in our case)
- Instantiated EDIF files
- Instantiated primitives
If you are instantiating a component that is represented by something other than VHDL code, no response to the warning message is needed. If your intent was not to instantiate a black box, check your component declaration and instantiation to ensure that the component is properly represented by VHDL code.
To avoid "black box" warning messages, add the following lines to your HDL code:
VHDL:
architecture <architecture_name>
:
attribute box_type : string;
attribute box_type of <component_name> : component is "black_box";
:
begin
Verilog:
//synthesis attribute box_type <module_name> "black_box"
Unused register bits
Some registers have unused bits:
WARNING:Xst:646 - Signal <tdi_data_reg1<31:30>> is assigned but never used.
WARNING:Xst:646 - Signal <tdi_data_reg2<31:30>> is assigned but never used.
WARNING:Xst:646 - Signal <tdi_data_reg3<31:30>> is assigned but never used.
WARNING:Xst:646 - Signal <tdi_data_reg4<31:30>> is assigned but never used. One-hot encoding not safeINFO:Xst:2117 - HDL ADVISOR -Mux Selector <jtc_tck_source> of Case statement line 313
was re-encoded using one-hot encoding.The case statement will be optimized
(default statement optimization),but this optimization may lead to design initialization problems.
To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <jtc_tck_source> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
We will take a closer look at these warnings and info messages but before we do, we will generate a Post-Synthesis Simulation Model.
Post-synthesis simulation model
The Post-Synthesis Simulation Model will contain all the building blocks used in the FPGA, like LUTs, muxes and I/O buffers. It is functionally correct but it has no timing information and it should be simulated using the unisim library.
Double-click the <Generate Post-Synthesis Simulation Model> entry in the Processes window in the Project Navigator to start the generation.
The flat netlist file ETC_synthesis.v will be found in the <ETC/netgen/synthesis> directory.
Before we can use it in our simulation we have to add the following instantiation <glbl glbl();> inside the module ETC.
We replace the ETC RTL design files with the ETC netlist file in our simulation setup and rerun our testcases and they all pass. The synthesis tool did its job.
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Posted at 08:57 am by svenand
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FPGA design from scratch. Part 11
Before we continue our FPGA design journey we will make a short stop and take a closer look at the leading actor/actress in this story. The FPGA device itself.
The Field Programmable Gate Array
If you are not involved in electronic design this header makes no sense to you. Is it a computer game where you try to arrange an array of gates out in a corn field or what is it? Let's start by explaining the gate array part first. We will turn to the Wikipedia encyclopedia for an explanation as we have done so many times before in this story.
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICS). A gate array circuit is a prefabricated silicon chip circuit with no particular function in which transistors, standard NAND or NOR logic gates, and other active devices are placed at regular predefined positions and manufactured on a wafer, usually called master slice. Creation of a circuit with a specified function is accomplished by adding a final surface layer metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customised as desired. This layer is analogous to the copper layer of a single-sided printed circuit board PCB.
Instead of having to manufacture the gate array at an expensive silicon foundry we can make it programmable by the user (in the field) and we will come up with a field programmable gate array.
A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.
Basic process technology types - SRAM - based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS.
- Antifuse - One-time programmable. CMOS.
- EPROM - Erasable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
- EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS.
- Flash - Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
- Fuse - One-time programmable. Bipolar.
FPGA manufacturers and their specialtiesAs of late 2006, the FPGA market has mostly settled into a state where there are two major "general-purpose" FPGA manufacturers and a number of other players who differentiate themselves by offering unique capabilities. - Xilinx and Altera are the current FPGA market leaders.
- Lattice Semiconductor provides both SRAM and non-volatile, flash-based FPGAs.
- Actel has antifuse and reprogrammable flash-based FPGAs, and also offers mixed signal flash-based FPGAs.
- Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx were. They focus on providing AVR Microcontrollers with FPGA fabric on the same die.
I have chosen to use a Xilinx FPGA in this story not because it is better or more powerful then the competitors, but it has the MicroBlaze soft processor core which is important to me. The evaluation board I purchased contains a Xilinx Virtex-4 FPGA device (XC4VFX12). Here is a good start to the Xilinx FPGA world.
The Virtex-4 FPGA familyThe Virtex-4 family of FPGAs was introduced 2004 and includes three platforms; Virtex-4 LX for logic, Virtex-4 SX for very high performance signal processing, and Virtex-4 FX for embedded processing and high-speed serial connectivity. Each version has a different mix of the special features and comes in a range of density to cover a variety of application sizes. Here is the data sheet.  (Courtesy of Xilinx)
These product tables show the different platforms and which features are included. To find out more about the Virtex-4 family read the user guide (pdf). Let's take a look at the XC4VFX12 and see what's inside the chip.
(Courtesy of Xilinx)
Logic Cells
A logic cell is defined by Xilinx to be one 4 input LUT + a flip flop + carry logic. The XC4FX12 has 12,312 logic cells. A logic cell looks like this:
Configurable Logic Blocks
The Configurable Logic Block (CLB) is the basic logic unit in an FPGA. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM.
- CLB is optimized for area and speed for compact high performance design.
- Four slices per CLB implement any combinatorial and sequential circuit.
- Each slice has 4-input look-up tables (LUT), flip-flops, multiplexors, arithmetic logic, carry logic, and dedicated internal routing.
- Dedicated AND/OR logic implements wide input functions.
(Courtesy of Xilinx)
Smart RAM
There are several ways you can build a memory in the XC4VFX12.
Shift Register SRL16 block - Configure any CLB LUT (Look-Up Table) to work as a fast, compact, 16-bit shift register.
- Cascade LUTs to build longer shift registers.
- Implement pipeline registers and buffers for video, wireless.
Distributed RAM - Configure any LUT to work as a single-port or dual-port 16-bit RAM/ROM.
- Cascade LUTs to build larger memories.
- Applications include flexible memory sizes, FIFOs, and buffers.
Embedded Block RAM - 36 blocks of cascadable, synchronous 18 Kbit block RAM.
- Configure any 18 Kbit block as a single/dual-port RAM.
- Supports multiple aspect ratios, data-width conversion, and parity.
- Applications include data caches, deep FIFOs, and buffers.
- The maximum size of a block RAM is 648 kbits
Digital Clock Managers
The Digital Clock Managers (DCM) provides a number of clock management features:
- Clock deskew. The DCM contains a delayed-locked loop to completely eliminate clock distribution delays.
- Frequency Synthesis. Separate outputs provide a doubled frequency. Another output provides a frequency that is a specified fraction of the input.
- Phase shifting. The DCM allows coarse and fine-grained phase-shifting.
XtremeDSP Slices
The XtremeDSP slices contain a dedicated 18x18-bits 2's complement signed multiplier, adder logic, and a 48 bit accumulator. Each multiplier and accumulator can be used independently. XC4VFX12 has 32 XtremeDSPs.
PowerPC Processor Block
The XC4VFX12 FPGA has one PowerPC™ 405, 32-bit RISC processor core. This industry standard processor offer high performance and a broad range of third-party support. The new Auxiliary Processor Unit (APU) controller simplifies the integration of hardware accelerators and co-processors.
 (Courtesy of Xilinx)Ethernet MACThe XC4VFX12 FPGA has built-in Ethernet connectivity with two Ethernet media access controller (MAC) blocks. The Xilinx unique tri-mode Ethernet MAC provides guaranteed performance and UNH-verified interoperability. This integrated functionality reduces total system cost by reducing design and verification effort, freeing approximately 1,800 logic cells per Ethernet MAC in the FPGA fabric.
Summary
The XC4VFX12FPGA device has 12,312 logic cells. We will use about 1200 logic cells for the design excluding the MicroBlaze soft processor core. The MicroBlaze will use between 800 to 2600 LUTs. For the block RAM we will use 64 kbits out of 648 kbits. There is plenty of room for future expansions.
More to read
If you want to know more about FPGA design look for a book at Amazon.com.
Training
Here are some companies providing training for Xilinix users. There are many more.
Posted at 09:09 am by svenand
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FPGA design from scratch. Part 12
Adding synthesis constraints
Constraints are essential to help you meet your design goals or obtain the best implementation of your circuit. Constraints are available in XST to control various aspects of the synthesis process itself, as well as placement and routing. Synthesis algorithms and heuristics have been tuned to automatically provide optimal results in most situations. In some cases, however, synthesis may fail to initially achieve optimal results; some of the available constraints allow you to explore different synthesis alternatives to meet your specific needs.
XST constraints can be specified in a file called the Xilinx Constraint File (XCF). The XCF must have an extension of .xcf.
To add a synthesis constraints file open the Synthesis Options window by right-clicking Synthesize - XST in the Proceses window and select Properties. Mark the Use Synthesis Constraints File box and fill in the name of the Synthesis Constraints File : /home/svenand/root/projects/ETC/synthesis/constraints/ETC_constraints.xcf
This table shows all synthesis constraints available for XST.
Here is the constraints file I am using to make a safe implementation of the case statements in the ETC_CONFIG module.
BEGIN MODEL ETC_CONFIG
NET jtc_tck_source safe_implementation = yes;
NET tdo_source safe_implementation = yes;
NET jtc_tms_source safe_implementation = yes;
NET jtc_trstz_source safe_implementation = yes;
NET jtc_tdi_source safe_implementation = yes;
NET mtc_tdo_source safe_implementation = yes;
END; When we rerun the synthesis we will see the following messages appear in the report file:
Analyzing module <ETC_CONFIG> in library <work>.
Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tms_source> in unit <ETC_CONFIG>.
Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tck_source> in unit <ETC_CONFIG>.
Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_trstz_source> in unit <ETC_CONFIG>.
Set property "SAFE_IMPLEMENTATION = yes" for signal <mtc_tdo_source> in unit <ETC_CONFIG>.
Set property "SAFE_IMPLEMENTATION = yes" for signal <tdo_source> in unit <ETC_CONFIG>.
Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tdi_source> in unit <ETC_CONFIG>. Top Next Previous
Posted at 03:56 pm by svenand
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FPGA design from scratch. Part 13
The MicroBlaze soft processor
We will use the MicroBlaze soft processor as the main controller in our system. The MicroBlaze™ soft processor is a 32-bit Harvard RISC architecture optimized for Xilinx FPGAs. The basic architecture consists of 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt. We can configure this basic design with more advanced features to allow us to balance the required performance of the target application against the logic area cost of the soft processor.
(Courtesy of Xilinx)
Here is the reference guide to download.
Installation of the Embedded Development Kit (EDK)The Embedded Development Kit provides you with a complete tool chain for the creation of your Virtex™ and Spartan™ series embedded PowerPC™ 405 and MicroBlaze™ designs. You find all the documentation here.
To install the Linux version of EDK follow these steps.- Download the EDK Get Started document
- Insert the Embedded Development Kit DVD. This DVD is part of the ML401 development kit.
- Open a terminal window and type cd /media/cdrom0 or whatever the path is to the cdrom.
- Execute the setup script ./setup. If everything goes fine the Xilinx Install Program window will be displayed.
- If you get the following error message when running the setup script it probably means that the system doesn't allow you to execute programs on the DVD: bash: ./setup: /bin/sh: bad interpreter: Permission denied.
- To fix this problem you have to edit the file /etc/fstab (static file system information) and add execute permission to the line defining the cdrom. Here is an example: /dev/hdb /media/cdrom0 udf,iso9660 user,noauto,exec 0 0
- Restart the system and start from 3 again.
- Register the EDK software here.
- Fill in all information and have the EDK product ID available, found on the back of EDK Development Kit DVD.
- The registration code will appear in the web browser and will also be sent to the email address you specified.
- Read all license agreements carefully !!! and click the agree check boxes.
- Insert the registration code when asked for.
- Specify the destination directory where the EDK software will be installed.
- Start the installation
 When the installation has finished we will see the following file tree structure. The files settings.csh and settings.sh contains setting of environment variables used by EDK. If you use a bash or sh shell add the line: source edk_install_dir/settings.sh to your shell startup file. If you use csh or tcsh add the line: source edk_install_dir/settings.csh to your shell startup file.
Now it is time to find the MicroBlaze VHDL source code. I wonder where it can be and in what format it is. Let's look in the hw directory.
Protected code
All the IP vendors protect their intellectual property using different forms of encryption. The MicroBlaze VHDL source code is encrypted and can not be read, modified or understood. It can be compiled using the Cadence ncvhdl compiler and you don't need to specify any special flags for the compilation.
Xilinx libraries
UNISIM library
The UNISIM Library is a library of functional models used for behavioral and structural simulation. It includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools. The UNISIM library also includes components that are commonly instantiated, such as I/Os and memory cells. We can instantiate the UNISIM library components in our design (VHDL or Verilog) and simulate them during behavioral simulation. All asynchronous components in the UNISIM library have zero delay. All synchronous components have a unit delay to avoid race conditions. The clock-to-out delay for these is 100 ps.
SIMPRIM library
The SIMPRIM Library is used for timing simulation. It includes all the Xilinx Primitives Library components used by Xilinx implementation tools.
XilinxCoreLib library
The Xilinx CORE Generator™ is a graphical Intellectual Property (IP) design tool for creating high-level modules like FIR Filters, FIFOs, CAMs, and other advanced IP. We can customize and pre-optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices, such as block multipliers, SRLs, fast carry logic and onchip, single-port or dual-port RAM.
The CORE Generator HDL library models are used for behavioral simulation. We can select the appropriate HDL model to integrate into our HDL design. The models do not use library components for global signals.
EDK library
The EDK Library is used for behavioral simulation. It contains all the EDK IP components, precompiled for ModelSim SE and PE or NcSim. This library eliminates the need to recompile EDK components on a per-project basis, minimizing overall compile time. The EDK IP components library is provided for VHDL only and may be encrypted. The Xilinx CompEDKLib utility deploys compiled models for EDK IP components into a common location. Unencrypted EDK IP components can be compiled using CompEDKLib. Precompiled libraries are provided for encrypted components.
Compiling everything
To find out how to compile all the libraries and all the IP blocks for the IUS simulator we first read the Embedded Systems Tools Guide. It tells us to use the Xilinx program compedklib to perform the compilation of all the libraries. We will use the program in GUI mode. Let's start. But before we start we will delete all old libraries we have compiled before. If not we may see a lot of compilation errors.
==> compedklib
Select the simulator to use.
Select directories to store compiled libraries.
Select directory to store EDK libs
Compile ISE and EDK libraries
Here is the result.
Now when we have everything compiled it is time to start building the complete simulation environment.That is the subject for the next chapter in this story.
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