Before we continue our FPGA design journey we will make a short stop and take a closer look at the leading actor/actress in this story. The FPGA device itself.

The Field Programmable Gate Array

If you are not involved in electronic design this header makes no sense to you. Is it a computer game where you try to arrange an array of gates out in a corn field or what is it? Let's start by explaining the gate array part first. We will turn to the Wikipedia encyclopedia for an explanation as we have done so many times before in this story.

A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICS). A gate array circuit is a prefabricated silicon chip circuit with no particular function in which transistors, standard NAND or NOR logic gates, and other active devices are placed at regular predefined positions and manufactured on a wafer, usually called master slice. Creation of a circuit with a specified function is accomplished by adding a final surface layer metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customised as desired. This layer is analogous to the copper layer of a single-sided printed circuit board PCB.

Instead of having to manufacture the gate array at an expensive silicon foundry we can make it programmable by the user (in the field) and we will come up with a field programmable gate array.

A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.

Basic process technology types

• SRAM - based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS.
• Antifuse - One-time programmable. CMOS.
• EPROM - Erasable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
• EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS.
• Flash - Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
• Fuse - One-time programmable. Bipolar.

FPGA manufacturers and their specialties

As of late 2006, the FPGA market has mostly settled into a state where there are two major "general-purpose" FPGA manufacturers and a number of other players who differentiate themselves by offering unique capabilities.

• Xilinx and Altera are the current FPGA market leaders.
• Lattice Semiconductor provides both SRAM and non-volatile, flash-based FPGAs.
• Actel has antifuse and reprogrammable flash-based FPGAs, and also offers mixed signal flash-based FPGAs.
• Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx were. They focus on providing AVR Microcontrollers with FPGA fabric on the same die.

I have chosen to use a Xilinx FPGA in this story not because it is better or more powerful then the competitors, but it has the MicroBlaze soft processor core which is important to me. The evaluation board I purchased contains a Xilinx Virtex-4 FPGA device (XC4VFX12). Here is a good start to the Xilinx FPGA world.

The Virtex-4 FPGA family

The Virtex-4 family of FPGAs was introduced 2004 and includes three platforms; Virtex-4 LX for logic, Virtex-4 SX for very high performance signal processing, and Virtex-4 FX for embedded processing and high-speed serial connectivity. Each version has a different mix of the special features and comes in a range of density to cover a variety of application sizes. Here is the data sheet.
 
                                                                                                                    (Courtesy of Xilinx)

These product tables show the different platforms and which features are included. To find out more about the Virtex-4 family read the user guide (pdf). Let's take a look at the XC4VFX12 and see what's inside the chip.



                                                                                                                                                          (Courtesy of Xilinx)
Logic Cells

A logic cell is defined by Xilinx to be one 4 input LUT + a flip flop + carry logic. The XC4FX12 has 12,312 logic cells. A logic cell looks like this:




Configurable Logic Blocks

The Configurable Logic Block (CLB) is the basic logic unit in an FPGA. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM.

• CLB is optimized for area and speed for compact high performance design.
• Four slices per CLB implement any combinatorial and sequential circuit.
• Each slice has 4-input look-up tables (LUT), flip-flops, multiplexors, arithmetic logic, carry logic, and dedicated internal routing.
• Dedicated AND/OR logic implements wide input functions.

                                                                          (Courtesy of Xilinx)

Smart RAM

There are several ways you can build a memory in the XC4VFX12.

Shift Register SRL16 block

• Configure any CLB LUT (Look-Up Table) to work as a fast, compact, 16-bit shift register.
• Cascade LUTs to build longer shift registers.
• Implement pipeline registers and buffers for video, wireless.

Distributed RAM

• Configure any LUT to work as a single-port or dual-port 16-bit RAM/ROM.
• Cascade LUTs to build larger memories.
• Applications include flexible memory sizes, FIFOs, and buffers.

Embedded Block RAM

• 36 blocks of cascadable, synchronous 18 Kbit block RAM.
• Configure any 18 Kbit block as a single/dual-port RAM.
• Supports multiple aspect ratios, data-width conversion, and parity.
• Applications include data caches, deep FIFOs, and buffers.
• The maximum size of a block RAM is 648 kbits
  

Digital Clock Managers

The Digital Clock Managers (DCM) provides a number of clock management features:

• Clock deskew. The DCM contains a delayed-locked loop to completely eliminate clock distribution delays.
• Frequency Synthesis. Separate outputs provide a doubled frequency. Another output provides a frequency that is a specified fraction of the input.
• Phase shifting. The DCM allows coarse and fine-grained phase-shifting.

XtremeDSP Slices

The XtremeDSP slices contain a dedicated 18x18-bits 2's complement signed multiplier, adder logic, and a 48 bit accumulator. Each multiplier and accumulator can be used independently. XC4VFX12 has 32 XtremeDSPs.

PowerPC Processor Block

The XC4VFX12 FPGA has one PowerPC™ 405, 32-bit RISC processor core. This industry standard processor offer high performance and a broad range of third-party support. The new Auxiliary Processor Unit (APU) controller simplifies the integration of hardware accelerators and co-processors.

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Adding synthesis constraints

Constraints are essential to help you meet your design goals or obtain the best implementation of your circuit. Constraints are available in XST to control various aspects of the synthesis process itself, as well as placement and routing. Synthesis algorithms and heuristics have been tuned to automatically provide optimal results in most situations. In some cases, however, synthesis may fail to initially achieve optimal results; some of the available constraints allow you to explore different synthesis alternatives to meet your specific needs.

XST constraints can be specified in a file called the Xilinx Constraint File (XCF). The XCF must have an extension of .xcf.
To add a synthesis constraints file open the Synthesis Options window by right-clicking Synthesize - XST in the Proceses window and select Properties. Mark the Use Synthesis Constraints File box and fill in the name of the Synthesis Constraints File : /home/svenand/root/projects/ETC/synthesis/constraints/ETC_constraints.xcf



This table shows all synthesis constraints available for XST.

Here is the constraints file I am using to make a safe implementation of the case statements in the ETC_CONFIG module.

BEGIN MODEL ETC_CONFIG
   NET jtc_tck_source       safe_implementation = yes;
   NET tdo_source           safe_implementation = yes;
   NET jtc_tms_source       safe_implementation = yes;
   NET jtc_trstz_source     safe_implementation = yes;
   NET jtc_tdi_source       safe_implementation = yes;
   NET mtc_tdo_source       safe_implementation = yes;
END;

When we rerun the synthesis we will see the following messages appear in the report file:

Analyzing module <ETC_CONFIG> in library <work>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tms_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tck_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_trstz_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <mtc_tdo_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <tdo_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tdi_source> in unit <ETC_CONFIG>.

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The MicroBlaze soft processor

We will use the MicroBlaze soft processor as the main controller in our system. The MicroBlaze™ soft processor is a 32-bit Harvard RISC architecture optimized for Xilinx FPGAs. The basic architecture consists of 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt. We can configure this basic design with more advanced features to allow us to balance the required performance of the target application against the logic area cost of the soft processor.


                                                                                                                                                                      (Courtesy of Xilinx)
Here is the reference guide to download.

Installation of the Embedded Development Kit (EDK)

The Embedded Development Kit provides you with a complete tool chain for the creation of your Virtex™ and Spartan™ series embedded PowerPC™ 405 and MicroBlaze™ designs. You find all the documentation here.

To install the Linux version of EDK follow these steps.

1. Download the EDK Get Started  document
   
2. Insert the Embedded Development Kit DVD. This DVD is part of the ML401 development kit.
3. Open a terminal window and type cd /media/cdrom0 or whatever the path is to the cdrom.
   
4. Execute the setup script ./setup. If everything goes fine the Xilinx Install Program window will be displayed.
5. If you get the following error message when running the setup script it probably means that the system doesn't allow you to execute programs on the DVD:  bash: ./setup: /bin/sh: bad interpreter: Permission denied.
   
6. To fix this problem you have to edit the file /etc/fstab (static file system information) and add execute permission to the line defining the cdrom. Here is an example:  /dev/hdb  /media/cdrom0   udf,iso9660 user,noauto,exec  0   0
7. Restart the system and start from 3 again.
   

1. Register the EDK software here.
2. Fill in all information and have the EDK product ID available, found on the back of EDK Development Kit DVD.
3. The registration code will appear in the web browser and will also be sent to the email address you specified.
4. Read all license agreements carefully !!! and click the agree check boxes.
   
5. Insert the registration code when asked for.
6. Specify the destination directory where the EDK software will be installed.
7. Start the installation

When the installation has finished we will see the following file tree structure.



The files settings.csh and settings.sh contains setting of environment variables used by EDK. If you use a bash or sh shell add the line: source edk_install_dir/settings.sh to your shell startup file. If you use csh or tcsh add the line: source edk_install_dir/settings.csh to your shell startup file.

Now it is time to find the MicroBlaze VHDL source code. I wonder where it can be and in what format it is. Let's look in the hw directory.




Protected code

All the IP vendors protect their intellectual property using different forms of encryption. The MicroBlaze VHDL source code is encrypted and can not be read, modified or understood. It can be compiled using the Cadence ncvhdl compiler and you don't need to specify any special flags for the compilation.

Xilinx libraries

UNISIM library

The UNISIM Library is a library of functional models used for behavioral and structural simulation. It includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools. The UNISIM library also includes components that are commonly instantiated, such as I/Os and memory cells. We can instantiate the UNISIM library components in our design (VHDL or Verilog) and  simulate them during behavioral simulation. All asynchronous components in the UNISIM library have zero delay. All synchronous components have a unit delay to avoid race conditions. The clock-to-out delay for these is 100 ps.

SIMPRIM library

The SIMPRIM Library is used for timing simulation. It includes all the Xilinx Primitives Library components used by Xilinx implementation tools.

XilinxCoreLib library

The Xilinx CORE Generator™ is a graphical Intellectual Property (IP) design tool for creating high-level modules like FIR Filters, FIFOs, CAMs, and other advanced IP. We can customize and pre-optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices, such as block multipliers, SRLs, fast carry logic and onchip, single-port or dual-port RAM.
The CORE Generator HDL library models are used for behavioral simulation. We can select the appropriate HDL model to integrate into our HDL design. The models do not use library components for global signals.

EDK library

The EDK Library is used for behavioral simulation. It contains all the EDK IP components, precompiled for ModelSim SE and PE or NcSim. This library eliminates the need to recompile EDK components on a per-project basis, minimizing overall compile time. The EDK IP components library is provided for VHDL only and may be encrypted. The Xilinx CompEDKLib utility deploys compiled models for EDK IP components into a common location. Unencrypted EDK IP components can be compiled using CompEDKLib. Precompiled libraries are provided for encrypted components.

Compiling everything

To find out how to compile all the libraries and all the IP blocks  for the IUS simulator we first read the Embedded Systems Tools Guide. It tells us to use the Xilinx program compedklib to perform the compilation of all the libraries. We will use the program in GUI mode. Let's start. But before we start we will delete all old libraries we have compiled before. If not we may see a lot of compilation errors.

==> compedklib



Select the simulator to use.




Select directories to store compiled libraries.



Select directory to store EDK libs




Compile ISE and EDK libraries




Here is the result.




Now when we have everything compiled it is time to start building the complete simulation environment.That is the subject for the next chapter in this story.

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Here you will find XCell Journals from 2003-2007.

Here you can download really old issues of XCell Journals from 1995 - 2001.Thanks Peter for the links. A lot of nostalgica can be found in these publications.

Issue 17 Q2 1995
Issue 18 Q3 1995
Issue 19 Q4 1995
Issue 20 Q1 1996
Issue 21 Q2 1996
Issue 22 Q3 1996
Issue 23 Q4 1996
Issue 24 Q1 1997
Issue 25 Q2 1997
Issue 26 Q3 1997
Issue 27 Q1 1998
Issue 28 Q2 1998
Issue 29 Q3 1998
Issue 30 Q4 1998
Issue 31 Q1 1999
Issue 32 Q2 1999
Issue 33 Q3 1999
Issue 34 Q4 1999
Issue 35 Q1 2000
Issue 36 Q2 2000
Issue 37 Q3 2000
Issue 38 Q4 2000
Issue 39 Q1 2001

Here are links to ASIC and FPGA related subjects

Conferences

• DATE Europe
• DAC
• FPGAworld Conference Stockholm & Lund 2007
• FPGA conferences
• FPGA/VLSI/CAD Conferences

News

• Chip Design Magazine
• Design & Reuse
• Embedded Computing Design
• FPGA and Structured ASIC Journal
• FPGA World
• Programmable Logic DesignLine
• SOCcentral
• topix.net

Forums

• Opal Kelly Community
• Xilinx
• topix.net

Embedded design

• Xilinx embedded
• The lab book pages

FPGA projects

• fpga4fun

FPGA CAD tools

• Aldec
• Cadence
• C to FPGA
• Mentor

FPGA Forums

• Journal Forums

FPGA Frequently Asked Questions

• FPGA-FAQ

FPGA Vendors

• Actel
• Altera
• Lattice
• QuickLogic
• Xilinx

FPGA design services

• Silicon Logic Engineering

FPGA Tutorials

• The ML403 out-of-the-box experience Part 1
  
• The ML403 out-of-the-box experience Part 2
• XPS tutorial

Embedded Linux

• Petalogix
• uClinux
• MicroBlaze uClinux project home page

Mailing lists

• MicroBlaze and uClinux

Xilinx and Linux

• Running the Xilinx tools on Linux

VLSI design

• VLSI chip design and development

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It very frustrating to read technical literature scattered with acronyms and abbreviations you don't understand or don't know the meaning of. The "FPGA design from scratch" story is also full of acronyms. I try to explain them the first time they are used but if you don't find an explanation in the text you can look here.

Here are some links to web sites that can help you.

• Acronym Finder
• Acronym Server

Acronym	Explanation	Comment
ASIC	Application-Specific Integrated Circuit
CLB	Configurable Logic Block
CMOS	Complementary metal–oxide–semiconductor
DCM	Digital Clock Manager
DSOCM	Data Side On-Chip Memory Controller
DSP	Digital Signal Processor
FIFO	First In First Out
FPGA	Field Programmable Gate Array
ISOCM	Instruction Side On-Chip Memory Controller
JTAG	Joint Test Action Group
LUT	Look-up table
MAC	Media Access Controller
NRE	Non-Recurring Engineering
RISC	Reduced Instruction Set Computer
UNH	University of New Hampshire

This summer we went to Spain to visit our daughter Sara, who was studying Spanish in Sevilla. Sevilla is the capital of Andalucia the most southern province in Spain. To see a map of Spain you can go to Google Maps. We traveled with Spanair from  Stockholm to Malaga. The direct flight took 4 hours.

We had a rental car from AurigaCrown car hire waiting for us at the Malaga Airport, a dark blue Seat Leon, good-looking sporty car. It was too late to drive that far so we decided to stay the first night in Malaga at Hotel Los Naranjos. The second day we planned to arrive in Sevilla late in the afternoon. On the way to Sevilla we wanted to make a stop in Ronda. We took the route E15/A7 driving west from Malaga. Along the way we passed the famous resorts Torremolinos, Fuengirola and Marbella. We didn't see much of Costa del Sol but we saw a lot of ugly looking hotel complex. From Marbella we turned right and drove A-376 towards Ronda. The road started to climb up the mountain and would take us more than 1000 meters up.
Ronda is one of Andalucia's loveliest towns, steeped in history. It stands on a towering plateau in the mountains of Malaga Province, and is famous through Spain for the plunging river gorge which divides the medieval from the 18th century parts of the town. This gorge is known as "El Tajo" - The Cliff and is spanned by a stone bridge, which once housed a prison. Visitors love to peer down into the gorge, to see the waters of the River Guadalevín.

We walked around in Ronda for several hours in the heat and burning sun. We visited the bullring, one of the oldest in Spain and we climbed down all the stairs to the bottom of the gorge. We had lunch in a beautiful restaurant, Restaurante Santa Casa Pola that is built in to the mountain side of the gorge. Here are more photos from Ronda.  After this fantastic start of our journey through Andalucia it was time to get back on the road again and head for Sevilla. On our way to Sevilla we passed Alogodonales a famous center for paragliding and hang gliding in Southern Spain.

Sevilla is a big city with  a population of more than 1 million, ranking as the fourth-largest metropolitan area of Spain. We had a hard time finding our hotel without a good map and not knowing where we were. After we got lost several times in the old town with all its narrow one way streets we at last found our hotel, Catalonia Giralda. When we got out of our car the heat almost knocked us. The thermometer displayed 46 Celcius (115 Farenheit) and we hesitated to leave the air-conditioned car. When we entered the hotel lobby it was 20C (68F) inside. The hotel was nice and perfectly located close to the oldest part of Sevilla. There are so many things to see in Sevilla you could easily spend several week here. The main attractions are the Cathedral with the Giralda bell tower and the Alcazar royal palace.

The Cathedral of Sevilla, formally Catedral de Santa María de la Sede (Cathedral of Saint Mary of the See) was begun in 1402, with construction continuing into the 16th century.It is the largest of all Roman Catholic cathedrals and also the largest Medieval Gothic religious building, in terms of both area and volume. It is 76 by 115 meters, and was built to cover the land previously occupied by the Almohad Mosque. Its central nave rises to an awesome 42 metres and even the side chapels seem tall enough to contain an ordinary church. Its main altarpiece is considered the largest in the Christian world.

The Giralda is the bell tower of the Cathedral of Seville one of the largest churches in the world and an outstanding example of the Gothic and Baroque architectural styles. The tower is a former Almohad minaret which, when built, was the tallest tower in the world at 97.5 m (320 ft) in height. It was one of the most important symbols in the medieval city.
The Alcázar of Seville is a royal palace. Originally a Moorish fort, the Alcázar(from the Arabic القصر al-qasr, meaning "palace") has been expanded several times. The Almohades were the first to build a palace, called Al-Muwarak, on the site. Most of the modern Alcázar was built over Moorish ruins for King Pedro of Castile  with construction beginning in 1364. Pedro used Moorish workers to build his palace giving it a distinctly Islamic design. The palace is one of the best remaining examples of mudéjar architecture, a style under Christian rule in Spain but using Islamic architectural influence.
The city sits well inland, but a mere 6 metres above sea level. Seville was long an important sea port, prior to the silting up of the Guadalquivir. From Seville Ferdinand Magellan obtained the ships for his circumnavigation. Much of the Spanish Empire's silver from the New World came to Europe in the Spanish treasure fleet that landed in Seville.
Sevilla is especially known for its Flamenco artists. The best Spanish Guitar players are from Andalusia, and many of them from Sevilla. You can also find in Sevilla many Flamenco Shows, with dancers and singers. Here are some photos from Sevilla. The barrio of Triana, across the Rio Guadalquivir from central Sevilla, used to be the quarter of the city's gitanos and the home of Sevillian ceramics. This is also where Sara lives. She share an appartement together with three other students.
The first week we used Sevilla as our starting-point for excursion to exciting places in the south-west of Spain. In a few hours time we can reach Cadiz, Jerez de la Frontera, Gibraltar and Costa de la Luz. One of the most beautiful beaches in Spain is Los Caños de Meca, located 10 km north of Barbate.

After one week in Sevilla we take road A4 to Cordoba. On the way we make a stop in Carmona. Carmona stands on a low hill just off A4, 38km east of Sevilla. It is a charming old town with impressive monuments from many different epochs and with fine views.
We arrive in the afternoon in Cordoba and find our hotel Macia Alfaros a beautiful place with a refreshing outdoor swimming pool. Cordoba is famous for a single architectural  treasure, the Mezquita symbol of the sophisticated Islamic culture. Cordoba's medieval quarter, once the home of the Jewish community, is called "La Judería" (The Jewry), a labyrinth of winding, narrow streets, shady flower-filled courtyards and picturesque squares such as La Plaza del Potro. That night we are having a exquiste diner at restaurant Casa PePe. We are sitting outside at 11 pm and it is still 30 C and it feels cool compared to the 43 C in the middle of the day.

Our next stop on our Spanish tour is Granada. There is no doubt about it - Granada does enchant. The Alhambra palace-fortress stretched along the top of the Sabika hill amid its sumptuos gardens, and the warrenlike Albayzin, Granada's old Islamic quarter, are highlights of any visit to Andalucia. There's no other city in Andalucia where the Islamic past feels so recent. We have booked a room at Parador de Granada Hotel San Fransisco which is part of the famous Palace of Alhambra. We were told we had to make reservations many month in advance but we were lucky and could get a room just a few weeks in advance. Parador hotels can be found all over Spain and they are operated by the Paradores de Turismo de Espana, S.A. which is state owned. Parador hotels are normally found in beautifully restored castles, palaces, fortresses, convents and other fine locations.



Want to read more about Andalucia search for a book at Amazon.

When writing this story I had great help from Wikipedia, the free encyclopedia. Since its creation in 2001, Wikipedia has rapidly grown into the largest reference Web site on the Internet. The content of Wikipedia is free, and is written collaboratively by people from all around the world. This Web site is a wiki, which means that anyone with access to an Internet-connected computer can edit, correct, or improve information throughout the encyclopedia, simply by clicking the edit this page link.

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How fast is my MacBook? Let's compare it to some other computers. Here are the contanders.

Model	Processor	Speed	Memory	Operating_System
Compaq EVO N610c	Pentium 4-M	1.8 GHz	512 MB	RedHat Rel 3.0
SUN SunBlade 1500	Ultra SPARC IIIi	1.5 GHz	1 GB	Solaris 10
HP Proliant DL145	AMD Opteron 200	2.6 GHz	32 GB	RedHat Rel 3.0
Apple MacBook I	Intel Duo Core	2.0 GHz	1 GB  Note 1.	Mac OS X 10.47 Ubuntu 6.06
Apple MacBook II	Intel Duo 2 Core	2.0 GHz	1 GB Note 1.	Mac OS X 10.48 Ubuntu 6.10

Note 1. On the MacBook all files are stored on the local disk. All the others have the files stored on an external file server.

The benchmark consists of two tasks. The first task uses ncvlog to compile a Xilinx macro library including 3100 Verilog files. The second task runs a verilog simulation using ncsim. Here are the results (in seconds) :

Task	Compaq	Sun	HP	Apple I	Apple II
Verilog compilation	58	72	25	24	23
Verilog simulation	60	59	31	28	17

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When designing an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) you use a hardware description language (HDL) like Verilog or VHDL. To verify that your design is correct you need a hardware simulator. To find a hardware simulator you have to contact a company that makes computer-aided design (CAD) tools. The three major companies developing CAD tools are Cadence, Mentor Graphics and Synopsys. Cadence has the Incisive Functional Verification Platform, Mentor has the Questa Scalable Verification, and Synopsys has the Discovery Verification Platform.
Ever since I started as an ASIC designer in 1990 I have been using Cadence tools. Back then Verilog-XL was one of the few hardware modeling language available and Cadence owned Verilog-XL. With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
Now it's time to install the Cadence hardware simulator. Let's go to the Cadence software download page. Before you can start the download you have to register as a Cadence user. To register you must already have a Cadence product installed. To run the simulator you also need an evaluation license. There is no freeware when it comes to CAD software but try to convince Cadence that you are a presumptive buyer of their software and they may give you access to their download page and an evaluation license. After signing up, go to the Electronic Distribution page and follow these steps:

1. Go to the Linux page.
   
2. Download and install the program InstallScape. InstallScape lets you download and install selected Cadence products in a release in a single step. Create an install directory and download the compressed tar file to this directory. Use the command <tar -zxvf Iscape03.40-s012lnx86.t.z> to unzip and unpack the file at the same time.
   
3. Before starting the installation create two directories, one to temporarily store the downloaded files (archive) and one directory where the final installation will be stored.
   
4. Start Iscape in a terminal window using the script file ../iscape/bin/iscape.sh
5. Click <Select Release> and choose a server near you. Protocol should be <http>.
6. Click the <Select Release> button. Enter user name and password.
7. Select Release and Platform. Click the Linux tab and select IUS58 or later from the list. Click next.
8. Select Release : What do you want to do and select <Download a Release>. Click next.
9. Select Release : Select Source Site to Download. Select one of the releases from the list. Click the download button.
10. Download : What do you want to do. Select <Save Archive and Install>. Click next.
11. Download : Save Archive & Install. Choose <I will select products manually>. Click next.
12. Download : Specify Archive Directory. Select the archive directory. Click next.
13. Download : Specify Install Directory. Select the install directory. Click next.
14. Select Product. Select the full Incisive Unified Simulator (29300) from the list. Click next.
15. Start the installation. You will need 2.7 GB of disk space for the archive and the install directories. When the installation has finished you can delete the archive directory. With a high speed connection the installation will take about 30 minutes. When finished quit the window.
16. Before you can start to use the simulator it must be configured. Select <Configure Product> from the main Installscape window. Select <Install Directory> and click next button.
17. Select product <29300 Incisive Unified Simulator> and click next. The configuration script will start and you have to enter IAGREE before it kicks off. When finished close the report window. The installation is now finished and you can exit InstallScape.
18. To find out if the installation was successful you can start the verilog compiler <ncvlog>. Use the command install_dir/tools/bin/ncvlog. The compiler should start and print the following message:
    ncvlog : 05.82-p002 : ......
    
    Usage : ncvlog [options] source.file ....

The simulator will not start without a license file. Cadence uses the FLEXlm software license manager and you have to have the license  manager daemon running before starting the simulator (ncsim). You can ask Cadence for an evaluation license file that will last for 45 days. To generate a license file that will only run on your computer (node-locked) they need the MAC address of your machine. To find out the MAC address, execute the following command in a Linux terminal window.
<sudo ifconfig -a>. Look for eth0 and the HWaddr. The MAC address will look like this 00:91:B8:DF:D3:C0. Send the MAC address to Cadence and they will generate a license file for you. When you receive the license file you have to make two changes to the file. The file is in ASCII format and can be edited with a standard text editor. The first three lines of the file will look like this:
SERVER Cadence-SERVER 0091B8DFD3C0 5280
DAEMON cdslmd ./cdslmd
USE_SERVER
........
Replace "Cadence-SERVER" with the hostname of your machine. To find out the hostname execute the following command in a terminal window: <hostname>
Replace ./cdslmd with the full path name of the license daemon program located in the bin directory of the IUS58 installation.
My license file looks like this after the changes:
SERVER svenand-desktop 0091B8DFD3C0 5280
DAEMON cdslmd /home/svenand/cad/Cadence/ius58/tools/bin/cdslmd
USE_SERVER
.........
After editing the license file you start the license daemon using the following command:
install_dir/tools/bin/lmgrd -c license_file
When the license daemon is up and running you can start using the simulator. Good luck.
Don't forget to define the environment variable CDS_LIC_FILE before starting. Use the following command, replacing <hostname> with the host name of your host:
setenv CDS_LIC_FILE 5280@hostname (csh and tcsh)
export CDS_LIC_FILE=5280@hostname (bash)
or
setenv CDS_LIC_FILE license_file
export CDS_LIC_FILE=license_file



The picture shows a screenshot from my MacBook running Mac OS X with Parallels Desktop installed. The virtual machine has Ubuntu Linux booted. In the Ubuntu Linux OS the Cadence waveform viewer Simvision is running. The same thing goes for VMware Fusion.

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Now when we have the hardware in place lets go through the process of installing the software we need. The first thing we have to install is the virtualization software that enables us to run multiple operating systems on top of Mac OS X. There are several offers but I have choosen Parallels Desktop from Parallels Inc.

1. Order the program and download it from Parallels download page.
2. Installing Parallels is no different than installing any other OS X program that uses an installer. Double-click the installer, follow the prompts, and wait for it to finish. After installation, you'll find the program in the Parallels folder in the Applications folder. Behind the scenes, Parallels has installed quite a few things on your machine, including a kernel extension (a low-level tool that modifies the core of OS X) to enable its magic.
   
3. The next step is selecting the Linux distribution we would like to use. All CAD vendors  tell us they only support RedHat Enterprise Rel 3 or 4 but that doesn't stop us from using our favorite Linux distribution. I will use Ubuntu 6.10. Ubuntu is a complete Linux-based operating system, freely available with both community and professional support. It is developed by a large community of developers and its small size (it fits on one CD) makes it perfect for our usage.
4. Download the CD image (ubuntu-6.10-desktop-i386.iso) from the Ubuntu download page.
   
5. The file is 700MB so try to find a high-speed connection.
6. Start Parallels Desktop and click the "New VM" button. Click the Next button in the window displayed. The next window will look like this. Select "Create a typical VM" and click the next button.
   
   


7. Select the guest OS to be used. Set guest OS type to  Linux and guest OS  version to Debian Linux and click the next button.
   
    
   


8. The Configuration Editor window will be displayed. In this window you can change the configuration of the virtual machine. Select the CD/DVD-ROM setup to specify the image file to be read during installation. Select "Use image file" and enter the full image file name  .../ubuntu-6.10-desktop-i386.iso. You may also want to change the size of the memory from 256 MB to 512 MB if you have at least 1 GB installed in your Mac. If you need more than 8 GB hard disk you should also change the "Hard Disk" setup. When finished click "OK".
   
   
   


9. Start the virtual machine by clicking the green triangle. The installation will now start and in a few minutes the Ubuntu installation startup window will be displayed.  Double-click the install icon to continue the installation. Then there a is six step process to define the default language, the time zone, the keyboard layout, username and password and to prepare the disk (erase all). From when you click the install button the whole installation will take less than 15 minutes.
   
   
   


10. After the installation has finished you must restart the virtual machine. Before restarting, edit the setup and change CD/DVD-ROM back to default. The Ubuntu Linux will start and you are ready to login.
11. For adding Parallels Tools see this tutorial.

If this didn't help here is an even better  installation guide.

More information

• Home Page of Henk Koster
• Linux On MacBook (Jason Parekh)
• Debian Wiki MacBook
• Gentoo Wiki MacBook

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