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38000 feet above see level
I am sitting in an airplane heading for New York. We have been traveling for 5 hours and still have 3 more to go. I have read all the newspapers and magazines I can find and we have been served a tasteless lunch. Airlines try to save money on everything and the food is no exception. I have tried to watch one of the movies on the 12 by 10 cm display in the seat in front of me but lost interest pretty soon. I have navigated through the menu and read about the Airbus 340 and how to exercise sitting in your seat. Flying is boring.
But what cheered me up was the possibility to connect to Internet using the connexion by Boeing service www.connexionbyboeing.com. The service worked flawlessly and to impress on some of my friends I sent them an email telling them I am in a airplane on my way to New York. It is sad that this service will close down end of this year. I guess it wasn't profitable for Boeing. This blog entry is written and published using this service.
I will run the New York Marathon next Sunday. I am one of almost 600 Swedes that have the chance to take part in this great race. The travel agency arranging this trip is called SpringTime Travel www.springtime.se. Run in Swedish is "springa" which explain the name. I applied for the race more than a year ago and have been running more than 1500 km since than. I have lost 10 kg and was in perfect shape up to a week ago when I caught a cold. The cold is almost gone and race will take place November 5th so there is still some time to recover.
My wife accompanies me and we will spend some days exploring New York before the marathon. Tomorrow night we have a table reserved at the River Cafe www.rivercafe.com
Posted at 05:30 pm by svenand
Permalink
I have decided to start my own blog. I have a lot of spare time after leaving my job at Ericsson the telecommunications company. They gave me 18 months pay so I will stay afloat until I find something else to do. My plan is to start my own company and do consulting work in ASIC and FPGA design. I never wrote a diary in my whole life but the prospect of having hundreds of readers makes it more thrilling. I will write about everything that happens in my life from running the marathon to building my own wine cellar. I will write in English although my mother tongue is Swedish. I would like to make contacts all over the world not only in Sweden. That is why I named my blog "New Horizons".
Welcome to my blog!
Posted at 08:33 pm by svenand
Permalink
//$$HEADER
/*************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/*************************************************************************/
// Module: ETC_TEST
// Design: ETC
// Written by: Sven-Ake Andersson
// Description: Testbench body file for functional testing of the
// embedded test controller (ETC)
//$$UPDATE
/*************************************************************************/
/* */
/* U P D A T E I N F O R M A T I O N */
/* */
/*************************************************************************/
// Date Version Change
//------------------------------------------------------------------------
// 070102 1.0 First version
// 070108 1.1 Changed names of include setup files
//$$DESCRIPTION
/*************************************************************************/
/* */
/* T E S T B E N C H D E S C R I P T I O N */
/* */
/*************************************************************************/
//$$DEFINE
/*************************************************************************/
/* */
/* D E F I N E D I R E C T I V E S */
/* */
/*************************************************************************/
//$$TIMESCALE
/*************************************************************************/
/* */
/* T I M E S C A L E D I R E C T I V E */
/* */
/*************************************************************************/
`timescale 1ns / 10ps
//$$MODULE
/*************************************************************************/
/* */
/* M O D U L E S T A R T */
/* */
/*************************************************************************/
module ETC_TEST();
//$$VERSION
/*************************************************************************/
/* */
/* V E R S I O N D E F I N I T I O N S */
/* */
/*************************************************************************/
parameter TestbenchVersion = 1.1;
//$$PARAMETER
/*************************************************************************/
/* */
/* U S E R D E F I N E D P A R A M E T E R S */
/* */
/*************************************************************************/
parameter MaxNumberPins = 1000; // Defines array sizes
parameter MaxNumberOfTdiBits = 4095; // Maximum number of TDI/TDO data bits
// for one task
//$$TIMING
/*************************************************************************/
/* */
/* F U N C T I O N A L */
/* T I M I N G S E T U P */
/* */
/*************************************************************************/
parameter I_CLK_ClockStart = 0;
parameter I_CLK_ClockWidth = 10;
parameter I_CLK_ClockPeriod = 20;
//$$PROGRAM DEFINED
/*************************************************************************/
/* */
/* P R O G R A M D E F I N E D P A R A M E T E R S */
/* */
/*************************************************************************/
// Set maximum values for counters and memory sizes
parameter PROGRAM_SIZE_MAX = 1024; // Maximum size of testprogram ram
parameter WAIT_CYCLES_MAX = 67108863;
parameter TRTZ_LOW_CYCLES_MAX = 4095;
parameter TMS_HIGH_CYCLES_MAX = 4095;
parameter CLOCK_RATE_DIV_BY_4 = 3'b000;
parameter CLOCK_RATE_DIV_BY_8 = 3'b001;
parameter CLOCK_RATE_DIV_BY_16 = 3'b010;
parameter CLOCK_RATE_DIV_BY_32 = 3'b011;
parameter CLOCK_RATE_DIV_BY_64 = 3'b100;
parameter ENABLE_TCK = 1'b1;
parameter DISABLE_TCK = 1'b0;
parameter ENABLE_SINGLE_STEP = 1'b1;
parameter DISABLE_SINGLE_STEP = 1'b0;
parameter ENABLE_INTERRUPT = 1'b1;
parameter DISABLE_INTERRUPT = 1'b0;
parameter NO_SHIFT_DR = 12'b0;
parameter NO_SHIFT_IR = 12'b0;
parameter SAVE_ALL_TDO = 2'b00;
parameter SKIP_TDO_SHIFTIR = 2'b01;
parameter SKIP_TDO_SHIFTDR = 2'b10;
parameter SKIP_TDO_ALL = 2'b11;
parameter ENABLE_LOOP_MODE = 1'b1;
parameter DISABLE_LOOP_MODE = 1'b0;
parameter NOT_USED = 2'b0;
parameter STOP_ETC = 32'h0;
parameter START_ETC = 32'h1;
parameter RESET_ETC = 32'h8;
//$$ETC ADDRESSES USED
/*************************************************************************/
/* */
/* E T C A D D R E S S M A P */
/* */
/*************************************************************************/
parameter ControlRegister = 32'h00000200; // write
parameter StatusRegister = 32'h00000204; // read
parameter ExecuteRegister = 32'h00000208; // write
parameter DebugRegister = 32'h0000020c; // read
parameter TestProgramMemory = 32'h00000000; // write
parameter TestResultMemory = 32'h00000100; // read
//$$CONFIG REGISTER SETUP
/*************************************************************************/
/* */
/* C O N F I G R E G I S T E R S E T U P */
/* */
/*************************************************************************/
parameter BoardTest = 4'b0000; // Connect external JTAG tester
parameter InternalTest = 4'b0001; // ETC connects to JTC internally
parameter ExternalTestDBCincl = 4'b0010; // ETC connects externally to the board
parameter ExternalTestDBCexcl = 4'b0011; // ETC connects externally to the board
parameter SystemTestDBCincl = 4'b0100; // ETC connects externally to the system
parameter SystemTestDBCexcl = 4'b0101; // ETC connects externally to the system
//$$ETC INSTRUCTION CODES
/*************************************************************************/
/* */
/* M T C I N S T R U C T I O N C O D E S */
/* */
/*************************************************************************/
parameter NoOperationOpCode = 4'b0000;
parameter TestResetTrstzLowOpCode = 4'b0001;
parameter TestResetTmsHighOpCode = 4'b0010;
parameter LoadInstructionOpCode = 4'b0011;
parameter LoadDataOpCode = 4'b0100;
parameter LoadInstructionAndDataOpCode = 4'b0101;
parameter LoadDataAndInstructionOpCode = 4'b0110;
parameter LoadDataPauseOpCode = 4'b0111;
parameter LoadDataContinueOpCode = 4'b1000;
parameter LoadDataContinuePauseOpCode = 4'b1001;
parameter WaitInRunTestIdleOpCode = 4'b1010;
parameter PauseInRunTestIdleOpCode = 4'b1011;
parameter EndOfTestOpCode = 4'b1100;
//$$TAP CONTROLLER
/*************************************************************************/
/* */
/* T A P C O N T R O L L E R C O N S T A N T S */
/* */
/*************************************************************************/
parameter ASIC_IDCODE = 32'h14012049;
parameter BoundaryScanRegLen = 51;
parameter MbistEnableRegLen = 40;
parameter MbistResultRegLen = 1;
parameter IdentificationRegLen = 32;
parameter BypassRegLen = 1;
//$$TAP_STATES
/*************************************************************************/
/* */
/* T A P C O N T R O L L E R S T A T E S */
/* */
/*************************************************************************/
parameter TEST_LOGIC_RESET = 4'b1111; // F
parameter RUN_TEST_IDLE = 4'b0100; // 4
parameter SELECT_DR_SCAN = 4'b1100; // C
parameter SELECT_IR_SCAN = 4'b0111; // 7
parameter CAPTURE_IR = 4'b0110; // 6
parameter SHIFT_IR = 4'b1001; // 9
parameter EXIT1_IR = 4'b0010; // 2
parameter PAUSE_IR = 4'b0011; // 3
parameter EXIT2_IR = 4'b0000; // 0
parameter UPDATE_IR = 4'b0101; // 5
parameter CAPTURE_DR = 4'b1110; // E
parameter SHIFT_DR = 4'b0001; // 1
parameter EXIT1_DR = 4'b1010; // A
parameter PAUSE_DR = 4'b1011; // B
parameter EXIT2_DR = 4'b1000; // 8
parameter UPDATE_DR = 4'b1101; // D
//$$JTAG INSTRUCTION
/*************************************************************************/
/* */
/* J T A G I N S T R U C T I O N S */
/* */
/*************************************************************************/
// INSTRUCTION OPCODES
parameter INSTRUCTION_LENGTH = 4;
parameter EXTEST = 4'b0000;
parameter IDCODE = 4'b0010;
parameter SAMPLE = 4'b0011;
parameter CLAMP = 4'b0100;
parameter HIGHZ = 4'b0101;
parameter MBIST_ENABLE = 4'b0110;
parameter MBIST_RESULT = 4'b0111;
parameter FAULT_INJECT = 4'b1000;
parameter EXTEST_PULSE = 4'b1001;
parameter EXTEST_TRAIN = 4'b1010;
parameter BYPASS = 4'b1111;
//$$INTEGER DEFINITIONS
/*************************************************************************/
/* */
/* I N T E G E R D E F I N I T I O N S */
/* */
/*************************************************************************/
integer i,j,jj;
integer cycles;
integer Address;
integer TestProgramSize;
integer ExpectedDataSize;
integer LoadModuleSize;
integer HeaderSize;
integer ExpectedDataAddress;
integer ExpectedDataBit;
integer NumberOfTdoDataWords;
integer CompilationError; // Set when error found during compilation
integer ShiftDataLen;
integer ShiftInstructionLen;
integer DataLenAdjust;
integer DataFinished;
integer FuncErrors; // Number of functional errors
integer EndOfTestIncluded; // Set when EndOfTest task included
integer TckClockCount;
integer SystemClockCount;
//$$REAL DEFINITIONS
/*************************************************************************/
/* */
/* R E A L D E F I N I T I O N S */
/* */
/*************************************************************************/
//$$REGISTER DEFINITIONS
/*************************************************************************/
/* */
/* R E G I S T E R D E F I N I T I O N S */
/* */
/*************************************************************************/
// Setup register
reg [31:0] TestProgram [0:1023]; // Store test program for ETC test
reg [31:0] ExpectedData [0:1023]; // Store expected data from ETC test
reg [31:0] MaskData [0:1023]; // Store mask data from ETC test
reg [31:0] TdoSavedData; // Store data when reading result memory
reg [31:0] InstructionCode;
reg [31:0] TdiDataWord;
reg [29:0] TdiDataTemp;
reg [29:0] TdiDataFix;
//$$DEVICE PINS
/*************************************************************************/
/* */
/* D E V I C E P I N S */
/* */
/*************************************************************************/
// Found in setup include file
//$$PROGRAM REGISTERS
/*************************************************************************/
/* */
/* R E G I S T E R U S E D D U R I N G S I M U L A T I O N */
/* */
/*************************************************************************/
// These register declarations must not be changed
reg [MaxNumberPins:1] COMPARE_VALUE;
reg [MaxNumberPins:1] MASK_VALUE;
reg [MaxNumberPins:1] RESULT_VALUE;
// Log file pointers
reg [31:0] AllFiles;
reg [31:0] Report;
reg [31:0] LoadModule;
reg [8*30:1] TaskName; // Store executing task name
reg [ 9 : 0] DesignIdentity;
reg [ 9 : 0] TestCaseIdentity;
reg [11 : 0] TestCaseVersion;
reg [31 : 0] LoadModuleIdentity;
reg [31 : 0] TdoRecordingMode;
reg BusyBit;
reg PauseBit;
reg FinishBit;
reg [3:0] LoadedTask;
reg [2:0] ErrorCode;
reg PauseShiftDr;
reg [5:0] RecAddress;
reg [4:0] Reserved;
reg [15:0] TdoBitCount;
reg [15:0] ExpectedTdoBits; // Count expected TDO data bits during
// test program compilatio
reg TimeStamp;
//$$PROBES
/*************************************************************************/
/* */
/* P R O B E S I N T O T H E D E S I G N */
/* */
/*************************************************************************/
wire [3:0] tapstate = {
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y4 .D ,
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y3 .D ,
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y2 .D ,
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y1 .D };
wire shiftdr = ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_SHIFTDR_STATE;
wire shiftir = ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/JTAG_SHIFTIR ;
`ifdef INTERNAL_TEST
wire TCK = ETC_TEST.ETC_TOP.ETC_INSTANCE.JTC_TCK;
`endif
`ifdef EXTERNAL_TEST
wire TCK = ETC_TEST.ETC_TOP.ETC_INSTANCE.JTC_TCK;
`endif
`ifdef SYSTEM_TEST
wire TCK = ETC_TEST.ETC_TOP.ETC_INSTANCE.JTC_TCK;
`endif
`ifdef BOARD_TEST
wire TCK = ETC_TEST.ETC_DBC3_TOP.BOARD_TESTER.ETC_TCKO;
`endif
//$$INCLUDE FILES
/*************************************************************************/
/* */
/* I N C L U D E F I L E S */
/* */
/*************************************************************************/
`ifdef INTERNAL_TEST
`include "ETC_InternalTestbench.setup"
`endif
`ifdef EXTERNAL_TEST
`include "ETC_ExternalTestbench.setup"
`endif
`ifdef SYSTEM_TEST
`include "ETC_SystemTestbench.setup"
`endif
`ifdef BOARD_TEST
`include "ETC_BoardtestTestbench.setup"
`endif
`include "ETC_SystemTasks.v"
`ifdef BOARD_TEST
`include "ETC_BoardtestTasks.v"
`endif
//$$INITIALIZATION
/*************************************************************************/
/* */
/* I N I T I A L I Z A T I O N R O U T I N E S */
/* */
/*************************************************************************/
initial
begin
Address = 0;
ExpectedDataAddress = 0;
ExpectedDataSize = 0;
TestProgramSize = 0;
ExpectedDataBit = 0;
NumberOfTdoDataWords = 0;
CompilationError = 0;
FuncErrors = 0;
MASK_VALUE = 0;
COMPARE_VALUE = 0;
EndOfTestIncluded = 0;
TckClockCount = 0;
SystemClockCount = 0;
ExpectedTdoBits = 0;
TimeStamp = 1'b0;
LoadModuleIdentity = 32'h0;
TdoRecordingMode = 32'h0;
$timeformat(-9, 0, " ns",10); // 1ns precision
DesignIdentity = 9'h171; // Identifies the design
end
/*************************************************************************/
/* */
/* O P E N O U T P U T F I L E S */
/* */
/*************************************************************************/
initial
begin
`ifdef MONGOOSE_START
Report = $fopen({"result/",`TESTCASE_STRING,".res"});
if (Report == 0) $finish;
LoadModule = $fopen({"result/",`TESTCASE_STRING,".lm"});
if (LoadModule == 0) $finish;
`endif
AllFiles = (Report | 1);
end
//$$COUNT CLOCKS
/*************************************************************************/
/* */
/* C O U N T C L O C K S */
/* */
/*************************************************************************/
always
begin
@(posedge TCK) TckClockCount = TckClockCount + 1;
end
always
begin
@(posedge I_CLK) SystemClockCount = SystemClockCount + 1;
end
//$$TEST OUTPUT SIGNALS
/*************************************************************************/
/* */
/* T E S T O U T P U T S I G N A L S */
/* */
/*************************************************************************/
always
begin
@(posedge TCK) begin
`ifdef INTERNAL_TEST
if (ETC_ENB != 1'b0 && FuncErrors == 0) begin
$fdisplay(AllFiles,"ETC_ENB signal not equal 0");
FuncErrors = FuncErrors + 1; end
`endif
`ifdef BOARD_TEST
if (ETC_ENB != 1'b0 && FuncErrors == 0) begin
$fdisplay(AllFiles,"ETC_ENB signal not equal 0");
FuncErrors = FuncErrors + 1; end
`endif
end
end
//$$CLOCKS
/*************************************************************************/
/* */
/* G E N E R A T E C L O C K S */
/* */
/*************************************************************************/
// Generate system clock
always
begin
#I_CLK_ClockStart I_CLK = 1;
#I_CLK_ClockWidth I_CLK = 0;
#(I_CLK_ClockPeriod-I_CLK_ClockStart-I_CLK_ClockWidth);
end
//$$END OF FILE
/*************************************************************************/
/* */
/* E N D O F T E S T B E N C H B O D Y */
/* */
/*************************************************************************/
// Endmodule is found in testcase file
-------------------------------------------------------------------------------------------
Posted at 09:13 am by svenand
Permalink
//$$HEADER
/*************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/*************************************************************************/
// Module: ETC_TEST
// Design: ETC
// Written by: Sven-Ake Andersson
// Description: Testcase file for functional testing
//$$UPDATE
/*************************************************************************/
/* */
/* U P D A T E I N F O R M A T I O N */
/* */
/*************************************************************************/
// Date Version Description
//------------------------------------------------------------------------
// 060322 1.0 First version
// 060719 1.1 New method for generating the testprogram
// 060823 1.11 Added expected data
// 060828 1.12 Modified for OPB interface
//$$CURRENT VERSION
/*************************************************************************/
/* */
/* C U R R E N T V E R S I O N */
/* */
/*************************************************************************/
initial
begin
TestCaseIdentity = 10'ha; // Identifies the testcase
TestCaseVersion = 12'h112; // Identifies the testcase version
end
//$$TEST DESCRIPTION
/*************************************************************************/
/* */
/* T E S T D E S C R I P T I O N */
/* */
/*************************************************************************/
// JTAG instruction tested : BYPASS
// Scan data through the bypass register and observe the TDO out data
// which will be one TCK clock cycle delayed.
//$$PARAMETERS
/*************************************************************************/
/* */
/* P A R A M E T E R S */
/* */
/*************************************************************************/
parameter MAXIMUM_NUMBER_OF_TCK_CYCLES = 24'd1000;
/*************************************************************************/
/* */
/* D E F I N E T E S T P R O G R A M */
/* */
/*************************************************************************/
task CompileTestProgram;
begin
SetLoadModuleIdentity(DesignIdentity,TestCaseIdentity,TestCaseVersion);
SetTdoRecordingMode(SKIP_TDO_SHIFTIR);
TestResetKeepingTrstzLow (10);
LoadInstruction(INSTRUCTION_LENGTH,BYPASS);
ReadWriteDataRegister(BypassRegLen+20,{{BypassRegLen{1'b0}},20'b1110011101});
SetExpectedData(BypassRegLen+20,{20'b1110011101,{BypassRegLen{1'bx}}});
EndOfTestProgram;
end
endtask
/*************************************************************************/
/* */
/* S T A R T T H E S I M U L A T I O N */
/* */
/*************************************************************************/
initial
begin
/*************************************************************************/
/* D I S P L A Y H E A D E R */
/*************************************************************************/
HeaderDisplay(AllFiles);
/*************************************************************************/
/* C O M P I L E T E S T P R O G R A M */
/*************************************************************************/
CompileTestProgram;
CompilationCheck;
if (CompilationError) begin
$fdisplay(AllFiles,"Errors found during compilation of test program");
$fdisplay(AllFiles,"Simulation stopped ");
$finish(2);
end
/*************************************************************************/
/* S A V E L O A D M O D U L E */
/*************************************************************************/
SaveLoadModule;
/*************************************************************************/
/* D I S P L A Y T E S T P R O G R A M */
/*************************************************************************/
DisplayTestProgramRam(TestProgramSize);
/*************************************************************************/
/* S E T I N P U T C O N D I T I O N S */
/*************************************************************************/
SetAllInpinsLow; // Define all other inputs
CE1 = 1; // Default value
SetAllInpinsFixed; // Define all fixed inputs
SetAllDiffInputsLow; // Define all differential inputs
ForceAllIopinsTristated; // Force all iopins from outside with "z"
/*************************************************************************/
/* R E S E T E T C */
/*************************************************************************/
ResetSystem(10,5);
/*************************************************************************/
/* L O A D T E S T P R O G R A M */
/*************************************************************************/
LoadTestProgram(TestProgramSize);
/*************************************************************************/
/* W R I T E C O N T R O L R E G I S T E R */
/*************************************************************************/
WriteTransfer(ControlRegister,{ENABLE_INTERRUPT,DISABLE_LOOP_MODE,
SKIP_TDO_SHIFTIR,DISABLE_SINGLE_STEP,
ENABLE_TCK,CLOCK_RATE_DIV_BY_8,
ExternalTestDBCexcl});
TestClockCycles(10);
/*************************************************************************/
/* S T A R T T H E T E S T */
/*************************************************************************/
WriteTransfer(ExecuteRegister,START_ETC);
/*************************************************************************/
/* W A I T F O R I N T E R R U P T ( E N D O F T E S T ) */
/*************************************************************************/
WaitForInterrupt(MAXIMUM_NUMBER_OF_TCK_CYCLES);
TestClockCycles(20);
/*************************************************************************/
/* S T O P T H E T E S T */
/*************************************************************************/
WriteTransfer(ExecuteRegister,STOP_ETC);
TestClockCycles(10);
/*************************************************************************/
/* D I S A B L E T C K */
/*************************************************************************/
WriteTransfer(ControlRegister,{DISABLE_TCK,CLOCK_RATE_DIV_BY_8,
ExternalTestDBCexcl});
SystemClockCycles(100);
/*************************************************************************/
/* F I N D N U M B E R O F T D O B I T S S T O R E D */
/*************************************************************************/
ReadStatusRegisterBits(BusyBit,PauseBit,FinishBit,LoadedTask,PauseShiftDr,
RecAddress,Reserved,TdoBitCount);
/*************************************************************************/
/* T D O D A T A C O M P A R I S O N */
/*************************************************************************/
TdoDataComparison(ExpectedDataSize);
/*************************************************************************/
/* D I S P L A Y T E S T R E S U L T */
/*************************************************************************/
ResultDisplay(AllFiles);
/*************************************************************************/
/* F I N I S H T H E S I M U L A T I O N */
/*************************************************************************/
$finish(2);
end
endmodule
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Posted at 10:40 am by svenand
Permalink
// Verilog Setup File Generated by Topi
// Generation Date : 2006-09-07
// Generation Time : 15:56:20
// Circuit Name : ETC
// Ericsson Product Name :
// Vendor Product Name :
// Spreadsheet Input File : /home/svenand/root/project/ETC/topgen/pin_table/ETC_BTEST.def
/*PIN INFORMATION*/
/******************************************************************************/
/* */
/* ASIC PIN INFORMATION */
/* */
/******************************************************************************/
// PinName PinType Width Tri Description
// I_CLK INPUT
// I_RESETS INPUT
// I_RESETA INPUT
// I_OPB_SELECT_BTEST INPUT
// I_OPB_SELECT INPUT
// I_OPB_RNW INPUT
// I_OPB_FWXFER INPUT
// I_OPB_HWXFER INPUT
// I_OPB_ABUS INPUT [31:0]
// I_OPB_DBUS INPUT [31:0]
// ETC_TDI_EX INPUT
// ETC_TRSTZI_BOARD INPUT
// ETC_TMSI_BOARD INPUT
// ETC_TDI_EX_BOARD INPUT
// ETC_TCKI_BOARD INPUT
// JTC_TDO_BTEST INPUT
// JTC_TDO_ENB_BTEST INPUT
// CE1 INPUT
// CE0_TEST INPUT
// RI INPUT
// JTC_TCK_BTEST OUTPUT
// JTC_TMS_BTEST OUTPUT
// JTC_TRSTZ_BTEST OUTPUT
// O_OPB_XFERACK OUTPUT
// O_OPB_DBUS OUTPUT [31:0]
// O_OPB_DBUSEN OUTPUT
// O_OPB_FWACK OUTPUT
// O_OPB_HWACK OUTPUT
// O_OPB_ERRACK OUTPUT
// O_OPB_TOUTSUP OUTPUT
// O_OPB_RETRY OUTPUT
// O_INTERRUPT OUTPUT
// ETC_TCKO OUTPUT
// ETC_TMSO OUTPUT
// ETC_TRSTZO OUTPUT
// ETC_TDO_ENB OUTPUT
// ETC_ENB OUTPUT
// ETC_ENB_BTEST OUTPUT
// CE0_IO_SE BIDIR
// CE1_A BIDIR
// CE1_B BIDIR
// CE1_C_0 BIDIR
// CE1_C_1 BIDIR
// IO_0 BIDIR
// IO_1 BIDIR
// IO_10 BIDIR
// IO_11 BIDIR
// IO_12 BIDIR
// IO_13 BIDIR
// IO_14 BIDIR
// IO_15 BIDIR
// IO_16 BIDIR
// IO_17 BIDIR
// IO_18 BIDIR
// IO_19 BIDIR
// IO_2 BIDIR
// IO_20 BIDIR
// IO_21 BIDIR
// IO_22 BIDIR
// IO_23 BIDIR
// IO_24 BIDIR
// IO_25 BIDIR
// IO_26 BIDIR
// IO_27 BIDIR
// IO_28 BIDIR
// IO_29 BIDIR
// IO_3 BIDIR
// IO_30 BIDIR
// IO_31 BIDIR
// IO_32 BIDIR
// IO_33 BIDIR
// IO_34 BIDIR
// IO_35 BIDIR
// IO_36 BIDIR
// IO_37 BIDIR
// IO_38 BIDIR
// IO_39 BIDIR
// IO_4 BIDIR
// IO_40 BIDIR
// IO_41 BIDIR
// IO_42 BIDIR
// IO_43 BIDIR
// IO_44 BIDIR
// IO_45 BIDIR
// IO_46 BIDIR
// IO_47 BIDIR
// IO_48 BIDIR
// IO_49 BIDIR
// IO_5 BIDIR
// IO_6 BIDIR
// IO_7 BIDIR
// IO_8 BIDIR
// IO_9 BIDIR
parameter NumberOfInputs = 83;
parameter NumberOfOutputs = 49;
parameter NumberOfBidirs = 55;
parameter NumberOfAllOuts = 104;
parameter NumberOfAllpins = 187;
/*REGS*/
/******************************************************************************/
/* */
/* INPUT PINS */
/* */
/******************************************************************************/
reg I_CLK;
reg I_RESETS;
reg I_RESETA;
reg I_OPB_SELECT_BTEST;
reg I_OPB_SELECT;
reg I_OPB_RNW;
reg I_OPB_FWXFER;
reg I_OPB_HWXFER;
reg [31:0] I_OPB_ABUS;
reg [31:0] I_OPB_DBUS;
reg ETC_TDI_EX;
reg ETC_TRSTZI_BOARD;
reg ETC_TMSI_BOARD;
reg ETC_TDI_EX_BOARD;
reg ETC_TCKI_BOARD;
reg JTC_TDO_BTEST;
reg JTC_TDO_ENB_BTEST;
reg CE1;
reg CE0_TEST;
reg RI;
/*WIRES*/
/******************************************************************************/
/* */
/* OUTPUT PINS */
/* */
/******************************************************************************/
wire JTC_TCK_BTEST;
wire JTC_TMS_BTEST;
wire JTC_TRSTZ_BTEST;
wire O_OPB_XFERACK;
wire [31:0] O_OPB_DBUS;
wire O_OPB_DBUSEN;
wire O_OPB_FWACK;
wire O_OPB_HWACK;
wire O_OPB_ERRACK;
wire O_OPB_TOUTSUP;
wire O_OPB_RETRY;
wire O_INTERRUPT;
wire ETC_TCKO;
wire ETC_TMSO;
wire ETC_TRSTZO;
wire ETC_TDO_ENB;
wire ETC_ENB;
wire ETC_ENB_BTEST;
/*WIRES*/
/******************************************************************************/
/* */
/* EXTERNAL CONNECTIONS */
/* */
/******************************************************************************/
/*REGS and WIRES*/
/******************************************************************************/
/* */
/* BIDIRECTIONAL PINS */
/* */
/******************************************************************************/
reg CE0_IO_SE_REG;
wire CE0_IO_SE;
reg CE1_A_REG;
wire CE1_A;
reg CE1_B_REG;
wire CE1_B;
reg CE1_C_0_REG;
wire CE1_C_0;
reg CE1_C_1_REG;
wire CE1_C_1;
reg IO_0_REG;
wire IO_0;
reg IO_1_REG;
wire IO_1;
reg IO_10_REG;
wire IO_10;
reg IO_11_REG;
wire IO_11;
reg IO_12_REG;
wire IO_12;
reg IO_13_REG;
wire IO_13;
reg IO_14_REG;
wire IO_14;
reg IO_15_REG;
wire IO_15;
reg IO_16_REG;
wire IO_16;
reg IO_17_REG;
wire IO_17;
reg IO_18_REG;
wire IO_18;
reg IO_19_REG;
wire IO_19;
reg IO_2_REG;
wire IO_2;
reg IO_20_REG;
wire IO_20;
reg IO_21_REG;
wire IO_21;
reg IO_22_REG;
wire IO_22;
reg IO_23_REG;
wire IO_23;
reg IO_24_REG;
wire IO_24;
reg IO_25_REG;
wire IO_25;
reg IO_26_REG;
wire IO_26;
reg IO_27_REG;
wire IO_27;
reg IO_28_REG;
wire IO_28;
reg IO_29_REG;
wire IO_29;
reg IO_3_REG;
wire IO_3;
reg IO_30_REG;
wire IO_30;
reg IO_31_REG;
wire IO_31;
reg IO_32_REG;
wire IO_32;
reg IO_33_REG;
wire IO_33;
reg IO_34_REG;
wire IO_34;
reg IO_35_REG;
wire IO_35;
reg IO_36_REG;
wire IO_36;
reg IO_37_REG;
wire IO_37;
reg IO_38_REG;
wire IO_38;
reg IO_39_REG;
wire IO_39;
reg IO_4_REG;
wire IO_4;
reg IO_40_REG;
wire IO_40;
reg IO_41_REG;
wire IO_41;
reg IO_42_REG;
wire IO_42;
reg IO_43_REG;
wire IO_43;
reg IO_44_REG;
wire IO_44;
reg IO_45_REG;
wire IO_45;
reg IO_46_REG;
wire IO_46;
reg IO_47_REG;
wire IO_47;
reg IO_48_REG;
wire IO_48;
reg IO_49_REG;
wire IO_49;
reg IO_5_REG;
wire IO_5;
reg IO_6_REG;
wire IO_6;
reg IO_7_REG;
wire IO_7;
reg IO_8_REG;
wire IO_8;
reg IO_9_REG;
wire IO_9;
/*BIDIR*/
/******************************************************************************/
/* */
/* ASSIGNMENTS BIDIR */
/* */
/******************************************************************************/
assign CE0_IO_SE = CE0_IO_SE_REG;
assign CE1_A = CE1_A_REG;
assign CE1_B = CE1_B_REG;
assign CE1_C_0 = CE1_C_0_REG;
assign CE1_C_1 = CE1_C_1_REG;
assign IO_0 = IO_0_REG;
assign IO_1 = IO_1_REG;
assign IO_10 = IO_10_REG;
assign IO_11 = IO_11_REG;
assign IO_12 = IO_12_REG;
assign IO_13 = IO_13_REG;
assign IO_14 = IO_14_REG;
assign IO_15 = IO_15_REG;
assign IO_16 = IO_16_REG;
assign IO_17 = IO_17_REG;
assign IO_18 = IO_18_REG;
assign IO_19 = IO_19_REG;
assign IO_2 = IO_2_REG;
assign IO_20 = IO_20_REG;
assign IO_21 = IO_21_REG;
assign IO_22 = IO_22_REG;
assign IO_23 = IO_23_REG;
assign IO_24 = IO_24_REG;
assign IO_25 = IO_25_REG;
assign IO_26 = IO_26_REG;
assign IO_27 = IO_27_REG;
assign IO_28 = IO_28_REG;
assign IO_29 = IO_29_REG;
assign IO_3 = IO_3_REG;
assign IO_30 = IO_30_REG;
assign IO_31 = IO_31_REG;
assign IO_32 = IO_32_REG;
assign IO_33 = IO_33_REG;
assign IO_34 = IO_34_REG;
assign IO_35 = IO_35_REG;
assign IO_36 = IO_36_REG;
assign IO_37 = IO_37_REG;
assign IO_38 = IO_38_REG;
assign IO_39 = IO_39_REG;
assign IO_4 = IO_4_REG;
assign IO_40 = IO_40_REG;
assign IO_41 = IO_41_REG;
assign IO_42 = IO_42_REG;
assign IO_43 = IO_43_REG;
assign IO_44 = IO_44_REG;
assign IO_45 = IO_45_REG;
assign IO_46 = IO_46_REG;
assign IO_47 = IO_47_REG;
assign IO_48 = IO_48_REG;
assign IO_49 = IO_49_REG;
assign IO_5 = IO_5_REG;
assign IO_6 = IO_6_REG;
assign IO_7 = IO_7_REG;
assign IO_8 = IO_8_REG;
assign IO_9 = IO_9_REG;
/*INPUTS NRZ LOW*/
/******************************************************************************/
/* */
/* SET ALL INPUTS NRZ LOW */
/* */
/****
Posted at 09:13 am by svenand
Permalink
FPGA design from scratch. An introduction.
I have been designing ASICs for more than 15 years. A few years ago I realized that there is another player in town and that is the FPGA circuit. With increasing NRE costs and with the long turn-around times, ASIC designs have become high-risk projects. At the same time FPGAs are getting bigger and faster and many companies have therefore decided to only use FPGAs. Therefore I decided to take a clooser look at the FPGA circuit. This is my story of how I hopefully will learn to use FPGAs in my future designs.
Learning-by-doing
John Dewey (1859-1952) was an American philosopher and educator whose writings and teachings have had profound influences on education in the United States. Dewey's philosophy of education, instrumentalism, focused on learning-by-doing rather than rote learning and dogmatic instruction, the current practice of his day.For Dewey, it was vitally important that education should not be the teaching of mere dead fact, but that the skills and knowledge which students learned be integrated fully into their lives as persons, citizens and human beings. Let's practice learning-by-doing.
Let's get started
We will design an embedded system, implementing a processor-controlled test equipment. Thereafter we will write a software device driver and an application program to run our system. The first thing we will do is to put together a FPGA design checklist. A checklist is used to compensate for the weaknesses of human memory to help ensure consistency and completeness in carrying out a task.
FPGA design checklist
- Make sure you have plenty of time to spare
- Find a decent computer
- If you can afford it, add a big display
- Decide which operating system to use
- Consider using a virtual machine (VM)
- Select an FPGA vendor
- Pick out a suitable development board
- Select an embedded processor to use
- Download the FPGA design software
- Add the latest service packs
- Choosing a logic simulator
- Choosing a synthesis tool
- Learn c-programming
- Read my tutorial
Make sure you have plenty of time to spareIt will take some time to set everything up, find all the information scattered all over the place and solve all problems along the way. I started this project December 2006 and I have not finished it yet. Learning from my mistakes will save you some time.
Find a decent computer
Almost any X86 equipped computer will do the job, but if you plan for some larger designs you should use a Intel Core Duo equipped computer. I am an old Mac fellow and will of course use my new MacBook with an Intel Core 2 Duo processor running at 2GHz. I will add a 23" Cinema display to provide a large screen area.
Decide which operating system to use
Here we have three choices. We can use an Unix operating system like Solaris if we happened to have a SPARC workstation from SUN avalaible, or we can use Windows XP or Linux on a X86 computer. For me the choice is easy. Coming from a Unix world I will use a Linux distribution. After trying out Ubuntu Linux I fell in love immediately.
Consider using a virtual machine
I could of course install Linux directly on my computer but that would stop me from using Mac OS X at the same time and that I don't like. A perfect solution is to install Linux in a virtual machine (VM). There are a least three ways of doing that.
After trying out Parallells Desktop and VMware Fusion I went with VMware Fusion.
Select an FPGA vendorThe two major FPGA vendors are Altera and Xilinx. Choosing with one to use is not an easy decision. The deciding factor for me was the MicroBlaze soft processor that Xilinx has.Pick out a suitable development boardWe could of course design an FPGA system ourselves but using one of the development boards from Xilinx will make things much easier. Xilinx have a number of development board in their catalog. Which one to pick. I decided to go for the ML403 board that has a Virtex-4 FPGA with a PowerPC 405 core. A cheaper alternative would be a Spartan 3 based board.
Select an embedded processor to use
As said earlier I have already decided to use the MicroBlaze. The MicroBlaze soft processor is a 32-bit Harvard RISC architecture optimized for Xilinx FPGAs. The basic architecture consists of 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt.
Download the FPGA design software
The ML403 board is bundled with two software packages called Integrated Software Environment (ISE) and Embedded Design Kit (EDK). These software packages contains all the software needed to design and implement an embedded system. The latest version of the software can be downloaded from the Xilinx web page.
Adding the latest service packs
As always with software products there are updates and bug fixes. These comes in service packs that have to be downloaded and installed. Make sure you have the latest service pack installed. That will save you some headache.
Choosing a logic simulator
The Xilinx software includes a very simple Verilog and VHDL simulator that only runs under Windows XP. The commercial simulators available from Cadence, Synopsys and Mentor cost a fortune and are out of reach for the normal user. What to do. I manage to convince Cadence to give me an evaluation license for their Incisive Unified Simulator that a could use.
Choosing a synthesis tool
The Xilinx software comes with the XST synthesis tool. There are a number of synthesis tool out on the market but I find XST good enough for me needs.
Learn C-programming
If you don't have any experience from c-programming you should find a good textbook and start learning c-programming. All the Xilinx software device drivers are written in c.
Read my tutorial
For a full description of the embedded design project read my tutorial www.fpgafromscratch.com.Lesson learned
Yes it is possible to learn how to design an embedded system using an FPGA. The biggest problem is finding the documentation and understanding the whole design flow. Hopefully my tutorial will help you in that respect. If you have some hardware and software experience it will be easier but even for a newbie it is doable.
Posted at 12:17 pm by svenand
Permalink
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