Installing and running the Linux OS

Now when we have updated our hardware to meet all software requirements it is time to install and bootup the Linux kernel we finished in part 43. Let's go through the following steps:

1. Connect everything (see part 29)
   
2. Generate a new netlist (Hardware->Generate Netlist)
   
3. Generate a new bitstream (Hardware->Generate Bitstream)
4. Download the bitstream (Device Configuration->Download Bitstream)

Disassembly of the Linux kernel

We use the following command to generate an assembly listing of the Linux kernel code: mb-obdump -d /tftpboot/image.elf > kernel.asm

Here is the start.

44000000 <_start>:
44000000:    94208001     mfs    r1, rmsr
44000004:    a421fffd     andi    r1, r1, -3
44000008:    9401c001     mts    rmsr, r1
4400000c:    b000441f     imm    17439
44000010:    31a0c000     addik    r13, r0, -16384    // 441fc000 <__init_begin>
44000014:    b000441e     imm    17438
44000018:    30408000     addik    r2, r0, -32768    // 441e8000 <_sdata>
4400001c:    b000441f     imm    17439
44000020:    3020bffc     addik    r1, r0, -16388
44000024:    b000441e     imm    17438
44000028:    33e082a8     addik    r31, r0, -32088    // 441e82a8 <init_task>
4400002c:    b0004400     imm    17408
44000030:    30c00c84     addik    r6, r0, 3204    // 44000c84 <machine_early_init>
44000034:    99fc3000     brald    r15, r6
44000038:    80000000     or    r0, r0, r0
4400003c:    b0004400     imm    17408
44000040:    31e00f68     addik    r15, r0, 3944    // 44000f68 <machine_halt>

and here is the end.

4421162c <cleanup_sunrpc>:
4421162c:    3021ffe4     addik    r1, r1, -28
44211630:    f9e10000     swi    r15, r1, 0
44211634:    b000fff8     imm    -8
44211638:    b9f4e828     brlid    r15, -6104    // 4419fe60 <cleanup_socket_xprt>
4421163c:    80000000     or    r0, r0, r0
44211640:    b000fff9     imm    -7
44211644:    b9f4ecc4     brlid    r15, -4924    // 441b0308 <unregister_rpc_pipefs>
44211648:    80000000     or    r0, r0, r0
4421164c:    b000fff9     imm    -7
44211650:    b9f4053c     brlid    r15, 1340    // 441a1b8c <rpc_destroy_mempool>
44211654:    80000000     or    r0, r0, r0
44211658:    b000441f     imm    17439
4421165c:    30a078d4     addik    r5, r0, 30932    // 441f78d4 <ip_map_cache>
44211660:    b000fff9     imm    -7
44211664:    b9f4bc30     brlid    r15, -17360    // 441ad294 <cache_unregister>
44211668:    80000000     or    r0, r0, r0
4421166c:    b000441d     imm    17437
44211670:    30a006a8     addik    r5, r0, 1704
44211674:    bc230028     bnei    r3, 40        // 4421169c
44211678:    b000fff9     imm    -7
4421167c:    b9f4f8a0     brlid    r15, -1888    // 441b0f1c <rpc_unregister_sysctl>
44211680:    80000000     or    r0, r0, r0
44211684:    b000fff9     imm    -7
44211688:    b9f4f7b8     brlid    r15, -2120    // 441b0e40 <rpc_proc_exit>
4421168c:    80000000     or    r0, r0, r0
44211690:    e9e10000     lwi    r15, r1, 0
44211694:    b60f0008     rtsd    r15, 8
44211698:    3021001c     addik    r1, r1, 28
4421169c:    b000ffdf     imm    -33
442116a0:    b9f49504     brlid    r15, -27388    // 4400aba4 <printk>
442116a4:    80000000     or    r0, r0, r0
442116a8:    b800ffd0     bri    -48        // 44211678
Disassembly of section .init.ivt:

44211e50 <__ivt_start>:
44211e50:    b0004400 b80821b0 b0004400 b80821c0     ..D...!...D...!.
44211e60:    b0004400 b8081fa0 b0004400 b8082450     ..D.......D...$P
44211e70:    b0004400 b80839f0 00000000 00000000     ..D...9.........
    ...
44211eb0:    b0004400 b8082320                       ..D...#

Download the Linux kernel

We will use the Xilinx Microprosser Debugger (XMD) to help us download the image file.

-> xmd

Xilinx Microprocessor Debug (XMD) Engine
Xilinx EDK 9.1.02 Build EDK_J_SP2.4
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

XMD% connect mb mdm
.....
......

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       0a001093           8        System_ACE
 2       05059093          16        XCF32P
 3       01e58093          10        XC4VFX12
 4       09608093           8        xc95144xl

MicroBlaze Processor Configuration :
-------------------------------------
Version............................6.00.b
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........off
Data Cache Support.................off
Exceptions  Support................off
FPU  Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on

Connected to MDM UART Target
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234

XMD% dow -data /tftpboot/image.bin 0x44000000

This command will download the Linux kernel image to the SDRAM starting at address 0x44000000

Let's read the first and last memory locations to find out if the download was successful.

XMD% mrd 0x44000000
mrd 0x44000000
44000000:   94208001

XMD% mrd 0x44211EB0
mrd 0x44211eb0
44211EB0:   B0004400

To start the Linux bootup sequence we use the following command:

XMD% con 0x44000000
con 0x44000000
Info:Processor started. Type "stop" to stop processor

RUNNING> XMD% stop
stop
XMD% Info:User Interrupt, Processor Stopped at 0x440044c8

We are having a problem here. It seems like the bootup sequence hangs and never finishes. This is what the code looks like around address 0x440044c8:

440044c4 <early_printk_putc>:
440044c4:    90a50060     sext8   r5, r5
440044c8:    b000a000     imm     -24576
440044cc:    e8600008     lwi     r3, r0, 8
440044d0:    a4630008     andi    r3, r3, 8
440044d4:    be23fff4     bneid   r3, -12        // 440044c8
440044d8:    a46500ff     andi    r3, r5, 255
440044dc:    b000a000     imm     -24576
440044e0:    f8600004     swi     r3, r0, 4
440044e4:    b60f0008     rtsd    r15, 8
440044e8:    80000000     or      r0, r0, r0

Let's set a breakpoint at address 0x440044c4 and start from the beginning.

XMD% bps 0x440044c4
bps 0x440044c4
Setting breakpoint at 0x440044c4

XMD% con 0x44000000
con 0x44000000
Info:Processor started. Type "stop" to stop processor

RUNNING> XMD% Info:Software Breakpoint 0 Hit, Processor Stopped at 0x440044c4

Let's single step and see what happens.

XMD% stp
stp
440044C8:   B000A000  imm      -24576

XMD% stp
stp
440044D0:   A4630008  andi     r3 , r3 , 8

XMD% stp
stp
440044D4:   BE23FFF4  bneid    r3 , -12

XMD% stp
stp
440044C8:   B000A000  imm      -24576

XMD% stp
stp
440044D0:   A4630008  andi     r3 , r3 , 8

XMD% stp
stp
440044D4:   BE23FFF4  bneid    r3 , -12


We are caught in this loop. Here are the register values:

XMD% rr
rr
    r0: 00000000      r8: 00000000     r16: 440044c4     r24: 00000000 
    r1: 441fbd94      r9: 00000000     r17: 00000000     r25: 00000000 
    r2: 441e8000     r10: 00000008     r18: ffffffda     r26: 00000000 
    r3: 00000046     r11: ffffffff     r19: 441fbdd4     r27: 00000000 
    r4: 441e8ee0     r12: 0000002d     r20: 00000000     r28: 00000000 
    r5: 00000046     r13: 441fc000     r21: 00000000     r29: 00000000 
    r6: 441fbdd4     r14: 00000000     r22: 00000024     r30: 00000000 
    r7: 00000026     r15: 44004514     r23: 00000046     r31: 441e82a8 
    pc: 440044c8     msr: 00000000
XMD%

I am building a new kernel. See part 43.


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A computer cache

A CPU cache is a temporary storage area where frequently accessed data can be stored for rapid access. Once the data is stored in the cache, future use can be made by accessing the cached copy rather than re-fetching or recomputing the original data, so that the average access time is lower.

A cache is made up of a pool of entries. Each entry has a datum (a nugget of data) which is a copy of the datum in some backing store. Each entry also has a tag, which specifies the identity of the datum in the backing store of which the entry is a copy. When the cache client (a CPU, web browser, operating system) wishes to access a datum presumably in the backing store, it first checks the cache. If an entry can be found with a tag matching that of the desired datum, the datum in the entry is used instead. This situation is known as a cache hit. For more information about the MicroBlaze cache functionality read the MicroBlaze Processor Reference Guide.

Enabling MicroBlaze caches

To enable the instrcuction and data caches we open the MicroBlaze IP configure window and select Cache. We enable the Instruction cache and the Data cache by ticking the two check boxes.



Specify cacheable memory segment

Cache Base Address and Cache High Address determines the cacheable segment of the SDRAM. We will make the whole SDRAM cacheable setting Cache Base Address to 0x44000000 and Cache High Address to 0x47ffffff.

Instruction cache operation

For every instruction fetched, the instruction cache detects if the instruction address belongs to the cacheable segment. If the address is non-cacheable, the cache controller ignores the instruction and lets the OPB or LMB complete the request. If the address is cacheable, a lookup is performed on the tag memory to check if the requested address is currently cached. The lookup is successful if: the word and line valid bits are set, and the tag address matches the instruction address tag segment. On a cache miss, the cache controller requests the new instruction over the instruction CacheLink (IXCL) interface, and waits for the memory controller to return the associated cache line.

Data cache operation

The MicroBlaze data cache implements a write-through protocol. Provided that the cache is enabled, a store to an address within the cacheable range generates an equivalent byte, halfword, or word write over the data CacheLink (DXCL) to external memory. The write also updates the cached data if the target address word is in the cache (i.e. the write is a cache-hit). A write cache-miss does not load the associated cache line into the cache. Provided that the cache is enabled a load from an address within the cacheable range triggers a check to determine if the requested data is currently cached. If it is (i.e. on a cache-hit) the requested data is retrieved from the cache. If not (i.e. on a cache-miss) the address is requested over data CacheLink (DXCL), and the processor pipeline stalls until the cache line associated to the requested address is returned from the external memory controller.

Xilinx CacheLink (XCL)

Xilinx CacheLink (XCL) is a high performance solution for external memory accesses. The MicroBlaze CacheLink interface is designed to connect directly to a memory controller with integrated FSL buffers, e.g. the MCH OPB DDR SDRAM controller. This method has the lowest latency and minimal number of instantiations.

The interface is only available on MicroBlaze when caches are enabled. It is legal to use a CacheLink cache on the instruction side or the data side without caching the other. Memory locations outside the cacheable range are accessed over OPB or LMB. Cached memory range is accessed over OPB whenever the caches are software disabled (i.e. MSR[DCE]=0 or MSR[ICE]=0).



Adding the MCH_OPB_DDR_SDRAM controller

We will replace the current SDRAM controller OPB_DDR_SDRAM with the new MCH_OPB_DDR_SDRAM controller.



                                                                                                                                   (Courtesy of Xilinx)




Connect IXCL and DXCL

We connect the MCH0 to the MicroBlaze IXCL port and the MCH1 to the MicroBlaze DXCL port.



Connecting ports

There are two new ports found in the mch_opb_ddr peripheral, DDR_Sleep and DDR_WakeUp.

Rising edge on DDR_Sleep enters the DDR SDRAM self refresh mode. A minimum period of 50uS after the assertion of DDR_Sleep is required before MCH_OPB_Rst can be asserted. We keep this signal low.

DDR_WakeUp indicates whether the DDR SDRAM must go through the power-up initialization after reset, or if only the sequence to exit the self refresh mode needs to be executed. This signal is sampled when reset negates and therefore should be asserted before MCH_OPB_Rst negates. We keep this signal low.

ETC_system.mhs

Here is the mch_opb_ddr setup part.

BEGIN mch_opb_ddr
 PARAMETER INSTANCE = mch_opb_ddr_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_DDR_TMRD = 14997
 PARAMETER C_MEM0_BASEADDR = 0x44000000
 PARAMETER C_MEM0_HIGHADDR = 0x47ffffff
 BUS_INTERFACE MCH0 = microblaze_0_IXCL
 BUS_INTERFACE MCH1 = microblaze_0_DXCL
 BUS_INTERFACE SOPB = mb_opb
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
 PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
 PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
 PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
 PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
 PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
 PORT DDR_Sleep = net_gnd
 PORT DDR_WakeUp = net_gnd
END



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Adding an External Memory Controller

We need a permanent storage for our Linux installation. The ML403 board contains a flash memory which is the perfect place to store our Linux OS to to be used during bootup of our system. To be able to read to and write from the flash memory we have to add an External Memory Controller (EMC). Let's do that.



The EMC supports up to four memory banks. We will use only one.



Generate addresses

The flash memory that comes with the ML403 board is 512 MB and with a 32 bit databus we will have a 128 MB address range.

Software platform settings

We have to tell the software where the flash is located. Open the Software->Software Platform Settings window and select OS and Libraries. Here we specify which memory bank we use (0) and the name of the external memory controller.





OPB External Memory Controller

The OPB EMC receives control signals from the OPB to read and write to external memory devices. The OPB EMC provides an interface between the OPB and one to four external banks of memory components. The EMC supports OPB data bus widths of 8,16 & 32 bits, and memory subsystem widths of 8,16 & 32 bits. The OPB EMC supports the OPB V2.0 byte enable architecture. Any access size up to the width of the OPB data bus is permitted. When the width of the memory is less than the width of the OPB, multiple memory cycles are performed to transfer the data width of the bus if data-width matching has been enabled for that memory bank.
The OPB EMC provides basic read/write control signals and the ability to configure the access times for read, write, and recovery times when switching from read to write or write to read. When the OPB EMC is set for flash memory control it is organized like an SRAM interface. The OPB EMC assumes that the Flash programming circuitry is built into the Flash components and that the command interface to the Flash is handled in software.



                                                                                                                                                                                         (Courtesy of Xilinx)


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Installing a Linux OS

It has been a long and bumpy ride but now we start to see the light in the tunnel. So keep up, stay onboard, we will soon reach the final destination. We are ready for the real challenge, installing a Linux OS in our embedded system.

Why using a Linux OS

Linux use in future embedded, mobile, and real-time projects will grow 278 percent over that in past projects, suggests a recent survey by Venture Development Corp. (VDC). Meanwhile, proprietary commercial embedded operating systems are holding steady, gaining customers from do-it-yourself OS users, but losing them just as fast to Linux, the analyst firm reports.

Embedded Linux OS

The MicroBlaze procssor has one drawback, it doesn't include a Memory Management Unit (MMU). To overcome this limitation, development started early to come up with a Linux kernel that could be used on a MMU-less processor. This work lead to to the introduction of uClinux. Most of the work done in the uClinux was been incorporated into the Linux kernel development and the 2.6 Linux kernel is the first stable release with mainline support for processors, such as MicroBlaze, that do not have an MMU eliminating the need to apply and forward-port uClinux patches.

uClinux

The original uClinux was a derivative of Linux 2.0 kernel intended for microcontrollers without MMUs. However, the Linux/Microcontroller Project has grown both in brand recognition and coverage of processor architectures. Today's uClinux as an operating system includes Linux kernel releases for 2.0 2.4 and 2.6 as well as a collection of user applications, libraries and tool chains.

Finding a Linux OS

This table shows some of the Linux OSes that runs on a MicroBlaze processor.

Distribution	Vendor	Information
uClinux	OpenSource
PetaLinux	PetaLogix
BlueCat Linux ME	LinuxWorks	Available ?

Third Party Real Time Operating Systems (RTOS) Support

This table and this table shows RTOS supporting PowerPC and MicroBlaze.


Application notes

You can find a number of application notes from Xilinx describing how to install an RTOS on a MicroBlaze processor.

• Getting Started with uClinux on the MicroBlaze Processor (XAPP730)
• Getting Started with the Nucleus PLUS RTOS and EDGE Tools on the MicroBlaze Processor (XAAP1016)
  

Choosing a Linux OS

We will use PetaLinux from PetaLogix. PetaLogix is an embedded Linux solution provider founded by Dr John Williams, architect and maintainer of the port of the uClinux operating system to the Xilinx MicroBlaze soft processor.

PetaLinux

PetaLogix has released PetaLinux v0.20, including Linux kernel 2.6.20 support for the Xilinx MicroBlaze soft-CPU architecture. PetaLinux is available as a free download from http://developer.petalogix.com, along with complete documentation, getting started guides and reference designs. Pre-built demo packages for the Xilinx ML401, Spartan3E-500 and Spartan3E-1600 allow a instant preview of the capabilities of Embedded Linux on the MicroBlaze.

The "uClinux microblaze port" mailing list

John Williams has setup a mailing list where you can ask all kind of questions about uClinux and the port to MicroBlaze.

Embedded Linux developer forum

uCdot is  the place to find more information about embedded Linux.

PetaLinux system requirements

The minimum system requirements to build a PetaLinux ready hardware platform are:

• MicroBlaze soft core processor
• Timer
• Interrupt Controller
• Standard input and output devices
• External memory controller
• RAM (DDR-SDRAM)
• ROM (Flash) optional
  
• Microprocessor Debug Module (for image download)
  

PetaLinux installation procedure

Let's read the installation guide.

Download

We will start by downloading petalinux-v0.20-rc3.tar.gz. The gzipped tar file is 317MB.

Select an installation directory

Create: mkdir /home/svenand/linux and goto the installation directory: cd /home/svenand/linux and move the tar file to this directory: mv /home/svenand/Desktop/petalinux-v0.20-rc3.tar.gz .

Unpacking

Unzip and unpack the file using the following command: tar zxvf petalinux-v0.20-rc3.tar.gz



After unpacking the following directory structure has been generated. The total size is 1.77GB

Environment setup

To set up our PetaLinux environment, change to the PetaLinux root directory and run the set up script. This script updates our path to point to the bundled gcc toolchain, and sets the $PETALINUX environment variable to point to the PetaLinux root.

-> cd petalinux-v0.20-rc3
-> source settings.sh (bash and sh)
-> source setting.csh (csh and tcsh)

We will add the following lines to .bashrc to make sure the script will always be run:
cd /home/svenand/linux/petalinux-v0.20-rc3
source /home/svenand/linux/petalinux-v0.20-rc3/settings.sh
cd /home/svenand


Configure and build our Linux kernel

After we have everything setup it is time to configure and build our Linux kernel. Let's follow the PetaLinux Platform from Scratch tutorial.

Selecting a platform

Selecting a platform is the initial step in the build of a kernel for our target. A platform configuration is essentially a collection of kernel configurations that are associated with that particular platform. This process allows the user to configure for a target platform without having to go through all the configurations associated with that platform.

Create a New Vendor Platform variant

We will use the petalinux-new-platform script to create a new vendor and platform combination for our system.

-> cd $PETALINUX/software/petalinux-dist
-> petalinux-new-platform -v Xilinx -p ML403 -k 2.6

The ML403 board has been added to the Xilinx directory.




PetaLinux kernel configuration

To start the configuration program execute the following commands:
-> cd software/petalinux-dist
-> make xconfig



Vendor/Product Selection




We select vendor Xilinx and the ML403 platform.


Kernel/Library/Defaults selection



We will use the default settings and click Save and Exit. The configuration setup is stored in the file $PETALINUX/software/petalinux-dist/.config. Later on we will change the configuration to match the hardware in our system.

Hardware modification

MicroBlaze

Instruction cache : Enabled
Data cache : Enabled

RS232 UART

Baudrate : 115200
Interrupt : Enable

Debug module

Enable the UART Interface on OPB: Disable
Interrupt : Enable

For more information about the hadware setup read the PetaLinux Platform from Scratch tutorial.

Auto configuration

PetaLinux AutoConfig framework allows the hardware configurations to be propagated to the bootloader and Linux kernel configurations. A few simple parameters in the EDK project's MSS (MicroProcessor Software Specification) file are all that is required to automatically configure the kernel and bootloader for our specific hardware platform.

Briefly, the steps are:

1. Create a new linux platform.
2. Create a EDK hardware project
3. Edit the MSS file to specifiy the PetaLinux autoconfiguration BSP tools (see below)
4. Use XPS to build the hardware project and generate libraries and BSPs
5. Use the petalinux-copy-autoconfig helpder script to propagate the system settings from your hardware project, across to your new Linux platform
6. Rebuild PetaLinux, to get your fully configured bootloader, Linux kernel and root filesystem image, ready for download.

Editing the MSS file

See the PetaLinux User Guide AutoConfig. Let' take a look in the ETC_system.mss file. This is what the OS part looks like:

BEGIN OS
 PARAMETER OS_NAME = standalone
 PARAMETER OS_VER = 1.00.a
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER STDIN = RS232_Uart
 PARAMETER STDOUT = RS232_Uart
END

We will change it like this:

BEGIN OS
 PARAMETER OS_NAME = petalinux
 PARAMETER OS_VER = 1.00.b
 PARAMETER PROC_INSTANCE = microblaze_0
 PARAMETER STDIN = RS232_Uart
 PARAMETER STDOUT = RS232_Uart
 PARAMETER MAIN_MEMORY = DDR_SDRAM_64Mx32
 PARAMETER MAIN_MEMORY_BANK = 0
END

Generate netlist and libraries

Let's start Xilinx Platform Studio and generate a new netlist and libraries and BSPs.
--> xps ETC_system.xmp &

The following error stops us from loading our project.

ERROR:MDT - Can not find MLD for the os petalinux 1.00.b
INFO:MDT - Directories Searched :
  - /home/svenand/root/projects/ETC/xps/bsp/petalinux_v1_00_b/data
  - /home/svenand/cad/edk91i/sw/ThirdParty/bsp/petalinux_v1_00_b/data
  - /home/svenand/cad/edk91i/sw/XilinxProcessorIPLib/bsp/petalinux_v1_00_b/data
  - /home/svenand/cad/edk91i/sw/lib/bsp/petalinux_v1_00_b/data

To fix this problem we have to find the petalinux .mld file and copy it to the XPS project directory. The .mld file can be found here: $PETALINUX/hardware/edk_user_repository/PetaLogix/bsp/petalinux_v1_00_b/data. We will make a link to the bsp directory from our EDK project directory.

-> cd $EDK_PROJECT
-> ln -s bsp $PETALINUX/hardware/edk_user_repository/PetaLogix/bsp



We use the menu command Hardware->Generate Netlist to generate a new netlist. No configuration files are generated during the netlist generation. We then generate the libraries using the menu command Software->Generate Libraries and BSPs. This process will create the following directory structure.



Here we find the auto-config.in (Linux 2.4.x) and the Kconfig.auto (Linux 2.6.x) configuration files.

Copying the AutoConfig file

To copy the configuration file across to our currently selected PetaLinux platform, we use the petalinux-copy-autoconfig command as follows: petalinux-copy-autoconfig ETC_system.xmp

==>petalinux-copy-autoconfig ETC_system.xmp                                                               
INFO: Attempting vendor/platform auto-detect
INFO: Auto-detected Xilinx/ML403 combination.
Auto-config file successfully updated for Xilinx ML403

The script will automatically detect which platform and which Linux kernel we have specified by reading the.config file and copy the right configuration file to the right place.



Platform reconfiguration

Next we have to reconfigure the platform settings of our custom platform into PetaLinux. This step requires us to run through the following configuration options.

More to be added.

Changing the default shell

In Ubuntu 7.04 the default shell (/bin/sh) is defined as /bin/dash instead of /bin/bash. The build process script relays on the bash shell to function. To change the default shell to bash execute the following commands:

--> sudo rm -f /bin/sh
--> sudo ln -s /bin/bash /bin/sh

To change back to dash execute the following commands:

--> sudo rm -f /bin/sh
--> sudo ln -s /bin/dash /bin/sh

Adding the /tftpboot directory

When working with network-enabled embedded Linux systems, it is often convenient to update Linux images and other files over the TCP/IP network.

The directory /tftpboot is commonly used as a transfer directory for this purpose. The PetaLinux tools can optionally copy Linux and bootloader files into this (or another) directory automatically.

To create the /tftpboot directory, you must have root access.

-> sudo mkdir /tftpboot
-> sudo chmod -R 777 /tftpboot

Installing zlib1g-dev

We need zlib to be able to build the Linux kernel: sudo apt-get install zlib1g-dev

Build the 2.6 kernel and user applications

The build process entails the following tasks.

• Build the Linux Kernel
• Build GNU tools
• Build the Root Filesystem
• Build the U-Boot bootloader

To start the build process for the newly added platform, in the $PETALINUX/software/petalinux-dist directory execute the following commands.

-> cd $PETALINUX/software/petalinux-dist

1. Build the project dependencies.
-> yes "" │ make oldconfig dep

2. Build images.
-> make all

The logfile

.......

Image Name:   PetaLinux Kernel 2.6
Created:      Sun Sep 30 17:36:28 2007
Image Type:   MicroBlaze Linux Kernel Image (uncompressed)
Data Size:    3289251 Bytes = 3212.16 kB = 3.14 MB
Load Address: 0x44000000
Entry Point:  0x44000000
# Run mkimage to build u-boot autoscr script
/home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/u-boot/tools/mkimage -A microblaze -O linux -T script -C none
    -a 0 -e 0 -n "PetaLinux Autoscr Script" 
    -d /home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/u-boot/board/petalogix/microblaze-auto/ub.config /home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/images/ub.config.img
Image Name:   PetaLinux Autoscr Script
Created:      Sun Sep 30 17:36:29 2007
Image Type:   MicroBlaze Linux Script (uncompressed)
Data Size:    1412 Bytes = 1.38 kB = 0.00 MB
Load Address: 0x00000000
Entry Point:  0x00000000
Contents:
   Image 0:     1404 Bytes =    1 kB = 0 MB
# Copy image files into /tftpboot, if requested
if [ "y" == 'y' ] ; then
        cp /home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/images/* "/tftpboot";
    fi
make[2]: Leaving directory `/home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/vendors/Xilinx/ML401'
make[1]: Leaving directory `/home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/vendors'
==>   

Congratulations to all of us. We made it!!!!

Output images

Once the build process is completed, all the images are located in both the $PETALINUX/software/petalinux-dist/images and the /tftpboot directory.

tftpboot directory content

Image Name	Description	File Size
Linux Kernel
image.bin	The Linux kernel and root filesystem image in binary format	3.1 MB
image.elf	The Linux kernel and root filesystem image in ELF format	3.4 MB
image.srec	The Linux kernel and root filesystem image in SREC format	9.3 MB
image.ub	The Linux kernel and root filesystem image in U-Boot format	3.1 MB
linux.bin	??	1.9 MB
romfs.img	The ROMFS image in binary format	1.2 MB
U-Boot
u-boot.bin	The U-Boot image in binary format	119 KB
u-boot.srec	The U-Boot image in SREC format	358 KB
u-boot-s.bin	The relocatable U-Boot image in binary format	119 KB
u-boot-s.elf	The relocatable U-Boot image in ELF format	120 KB
u-boot-s.rec	The relocatable U-Boot image in SREC format	358 KB
ub.config.img	U-Boot platform configuration script in binary format	1.4 KB

Top  Next   Previous

Some of you have asked me why I didn't write a book instead of this blog. Here are a few reasons:

Time to market

It takes 10 minutes to setup a blog account at one of the many companies offering blog services. It may take a year to have a book published.

Simplicity

You can start from day one writing your blog. You don't have know anything about web design or html. Write the text and click publish. It is that easy.

Flexibility

You have a lot of freedom when designing your blog. You can use any font style and font size you like. There are hundreds of page designs you can choose from and if you don't like them you can design one yourself. You can add as many images you like and you can link to other web pages and documents.

Extend and update

At any time you can introduce more information to your blog, fix mistakes and add updates.

Interaction

A blog is the best way to interact with your readers. They can ask questions and add comments and you can answer and make comments.

Presence/Exposure

This blog can be read all over the world. The only thing you need is a computer and an internet connection.


And here is one reason for not writing a blog:

No food on the table

Writing a blog doesn't bring food on the table. You have to find a way to make some money out of your blog.

Adding a timer

Before we can install a Linux OS in our embedded system we have to add a timer IP. Now when we know how to add a new peripheral it will only take us a few minutes. We start by selecting the OPB Timer Counter from the IP catalog.




We add it and configure it.



We generate addresses and connect the ports and we are done.

Connect the interrupt signal

We will add the interrupt signal coming from the timer/counter to the interrupt controller. We give the highest priority to the timer interrupt. Select the Ports display and click the first port to display this window.






OPB Timer/Counter

The OPB Timer/Counter is a 32-bit timer module that attaches to the OPB (On-Chip Peripheral Bus). It includes two programmable interval timers with interrupt, event generation, and event capture capabilities. It also includes a Pulse Width Modulator (PWM) output and a configurable counter width. Each of the two timer modules is capable of holding the initial value of the counter for event generation or capture a value based on the mode of the timer.

                                                                                                                                                (Courtesy of Xilinx)

Register address map

Register Name	Abbreviation	OPB Offset	Type
Control/Status Register 0	TSCR0	0x00	R/W
Load Register 0	TLR0	0x04	R/W
Timer/Counter Register 0	TCR0	0x08	R
Control/Status Register 1	TSCR1	0x10	R/W
Load Regster 1	TLR1	0x14	R/W
Timer/Counter Register 1	TCR1	0x18	R

The registers are organized as big-endian data.

Library Generation

After running libgen we have copied the following source files to the libsrc directory.




xparameters.h

/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1

/* Definitions for peripheral OPB_TIMER_0 */
#define XPAR_OPB_TIMER_0_BASEADDR 0x43505000
#define XPAR_OPB_TIMER_0_HIGHADDR 0x435050FF
#define XPAR_OPB_TIMER_0_DEVICE_ID 0


xtmrctr_l.h

/************************** Constant Definitions *****************************/

/**
 * Defines the number of timer counters within a single hardware device. This
 * number is not currently parameterized in the hardware but may be in the
 * future.
 */
#define XTC_DEVICE_TIMER_COUNT    2

/* Each timer counter consumes 16 bytes of address space */

#define XTC_TIMER_COUNTER_OFFSET 16

/** @name Register Offset Definitions
 * Register offsets within a timer counter, there are multiple
 * timer counters within a single device
 * @{
 */

#define XTC_TCSR_OFFSET      0     /**< control/status register */
#define XTC_TLR_OFFSET       4     /**< load register */
#define XTC_TCR_OFFSET       8     /**< timer counter register */


/** @name Control Status Register Bit Definitions
 * Control Status Register bit masks
 * Used to configure the timer counter device.
 * @{
 */

#define XTC_CSR_ENABLE_ALL_MASK     0x00000400  /**< Enables all timer counters */
#define XTC_CSR_ENABLE_PWM_MASK     0x00000200  /**< Enables the Pulse Width
                                                     Modulation */
#define XTC_CSR_INT_OCCURED_MASK    0x00000100  /**< If bit is set, an interrupt has
                                                     occured.*/
                                                /**< If set and '1' is written
                                                     to this bit position,
                                                     bit is cleared. */
#define XTC_CSR_ENABLE_TMR_MASK     0x00000080  /**< Enables only the specific timer */
#define XTC_CSR_ENABLE_INT_MASK     0x00000040  /**< Enables the interrupt output. */
#define XTC_CSR_LOAD_MASK           0x00000020  /**< Loads the timer using the load
                                                     value provided earlier in the
                                                     Load Register, XTC_TLR_OFFSET. */
#define XTC_CSR_AUTO_RELOAD_MASK    0x00000010  /**< In compare mode, configures the
                                                     timer counter to reload from the
                                                     Load Register. The default mode
                                                     causes the timer counter to hold
                                                     when the compare value is hit. In
                                                     capture mode, configures the
                                                     timer counter to not hold the
                                                     previous capture value if a new
                                                     event occurs. The default mode
                                                     cause the timer counter to hold
                                                     the capture value until
                                                     recognized. */
#define XTC_CSR_EXT_CAPTURE_MASK    0x00000008  /**< Enables the external input to
                                                     the timer counter. */
#define XTC_CSR_EXT_GENERATE_MASK   0x00000004  /**< Enables the external generate
                                                     output for the timer. */
#define XTC_CSR_DOWN_COUNT_MASK     0x00000002  /**< Configures the timer counter to
                                                     count down fromstart value, the
                                                     default is to count up. */
#define XTC_CSR_CAPTURE_MODE_MASK   0x00000001  /**< Enables the timer to capture the
                                                     timer counter value when the
                                                     external capture line is asserted.
                                                     The default mode is compare mode.*/


Application program

We have taken the application program from the examples directory found in the EDK installation (..../edk91i/sw/XilinxProcessorIPLib/drivers/tmrctr_v1_00_b/examples).

XStatus TmrCtrLowLevelExample(Xuint32 TmrCtrBaseAddress, Xuint8 TmrCtrNumber)
{
    Xuint32 Value;
    Xuint32 ControlStatus;
    Xuint32 i;


   /*
     * Set the master enable bit and enable hardware interrupts. We must set the
      * master enable bit before enabling interrupts otherwise we will get a spurious interrrupt (IRQ goes high) ???
     */
    XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK);
 
    /*
     * Enable interrupts from the timer/counter and the ETC
    */
    XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_OPB_TIMER_0_INTERRUPT_MASK | XPAR_ETC_0_O_INTERRUPT_MASK);
 
    /*
     * Clear the Timer Control Status Register
     */
    XTmrCtr_mSetControlStatusReg(TmrCtrBaseAddress, TmrCtrNumber,0x0);

    /*
     * Set the value that is loaded into the timer counter and cause it to
     * be loaded into the timer counter
     */
    XTmrCtr_mSetLoadReg(TmrCtrBaseAddress, TmrCtrNumber, 0x100);
    XTmrCtr_mLoadTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber);

    /*
     * Clear the Load Timer bit in the Control Status Register
     */
    ControlStatus = XTmrCtr_mGetControlStatusReg(TmrCtrBaseAddress,
                                                 TmrCtrNumber);
    /*
     * Setup the counter to count down and enable interrupt when counter rolls over
    */

    XTmrCtr_mSetControlStatusReg(TmrCtrBaseAddress, TmrCtrNumber,
                                 ControlStatus & (~XTC_CSR_LOAD_MASK)| XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_ENABLE_INT_MASK);


    /*
     * Start the timer counter such that it's decrementing.
     */

    XTmrCtr_mEnable(TmrCtrBaseAddress, TmrCtrNumber);

    /*
     * Read the value of the timer counter and wait for an interrupt
     */

    while (1)
     {
        /*
         * If the interrupt occurred which is indicated by the global
         * variable which is set in the device driver handler, then
         * stop waiting
         */
        Value = XTmrCtr_mGetTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber);
        if (InterruptProcessed)
        {
            break;
        }
    }

   /*
     * Disable the timer counter such that it stops incrementing
     */

    XTmrCtr_mDisable(TmrCtrBaseAddress, TmrCtrNumber);

    return XST_SUCCESS;
}

Simulation results

The counter will count down from 0x100 (256 decimal) to 0, when an interrupt will be generated. It takes 2590 ns from starting the timer to when the interrupt is generated. Clock frequency is 100 MHz (256*10 ns = 2560 ns).




Top  Next  Prevoius

Adding an interrupt controller

The ETC will generate an interrupt when the test has finished, if enabled (see Simvision plot). Instead of waiting a fixed time for the test to complete we could use the interrupt signal to tell the application program that the test has finished. Sounds like a good idea. Let's implement an interrupt controller to handle our interrupt. The MicroBlaze processor can handle one interrupt but we will probably have more than one interrupt in our final system.



Finding an interrupt controller

Let's try the Xilinx IP center and see what we find. The first thing I found was an application note, XAPP778 Using and Creating Interrupt-Based Systems.

As it says in the Xilinx documentation:
Here is a definition of an interrupt taken from this application note:


Because the MicroBlaze core only supports one external interrupt, designs which require more than one interrupt, must include an OPB Interrupt Controller (OPB_INTC).

                                                                                                                                       (Courtesy of Xilinx)

OPB_INTC



                                                                                                                                       (Courtesy of Xilinx)
Register map

Register Name	Abbreviation	OPB Offset
Interrupt Status Register	ISR	0 (0x00)
Interrupt Pending Register	IPR	4 (0x04)
Interrupt Enable Register	IER	8 (ox08)
Interrupt Acknowledge Register	IAR	12 (0x0c)
Set Interrupt Enable Bits	SIE	16 (0x10)
Clear Interrupt Enable Bits	CIE	20 (0x14)
Interrupt Vector Register	IVR	24 (0x18)
Master Enable Register	MER	28 (0x1c)

We will use Xilinx Platform Studio and add the IP. For more information about adding an IP read Part 17 and Part 31 of this tutorial.




Configuring the interrupt controller

Right-click the opb_intc_0 entry in the System Assembly View and select Configure IP. It seems we don't have to configure anything. Everything is auto computed.






Making connections

We select Ports in the System Assembly View and click the plus sign to display the ports available in opb_intc_0.



We connect the IRQ output of the interrrupt controller to the interrupt input on MicroBlaze and we are done with the hardware setup. The rest is software.




Software setup

After running library generation (libgen) the intc_v1_00_c software device driver has been added to the libsrc directory. The source code has been compiled and stored in the libxil.a library.



xparameters.h

The following parameters have been added to xparameters.h:

#define XPAR_INTC_MAX_NUM_INTR_INPUTS 1
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1

/* Definitions for peripheral OPB_INTC_0 */
#define XPAR_OPB_INTC_0_BASEADDR 0x43505000
#define XPAR_OPB_INTC_0_HIGHADDR 0x4350503F
#define XPAR_OPB_INTC_0_DEVICE_ID 0
#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000001


/******************************************************************/

#define XPAR_INTC_SINGLE_BASEADDR 0x43505000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4350503F
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define XPAR_ETC_0_O_INTERRUPT_MASK 0X000001
#define XPAR_OPB_INTC_0_ETC_0_O_INTERRUPT_INTR 0

/******************************************************************/

xintc_l.h

#define XIN_ISR_OFFSET      0       /* Interrupt Status Register */
#define XIN_IPR_OFFSET      4       /* Interrupt Pending Register */
#define XIN_IER_OFFSET      8       /* Interrupt Enable Register */
#define XIN_IAR_OFFSET      12      /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET      16      /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET      20      /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET      24      /* Interrupt Vector Register */
#define XIN_MER_OFFSET      28      /* Master Enable Register */

/* Bit definitions for the bits of the MER register */

#define XIN_INT_MASTER_ENABLE_MASK      0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK    0x2UL /* once set cannot be cleared */

Generate a software interrupt

Here is an example of a c-program to setup the interrupt controller and to generate a software interrupt. We will use the software interrupt to test our interrupt handling routine. When we are satisfied, we will enable the hardware interrupt and at the same time disable all further software interrupts.

     /*
     * Enable interrupts for all devices that cause interrupts.
     * Write to Interrupt Enable Register
     */
    XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_ETC_0_O_INTERRUPT_MASK);


    /*
     * Set the master enable bit. Note that we do not enable hardware
     * interrupts yet since we want to simulate an interrupt from software
     * down below. WRite to Master Enable Register
     */
    XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK);

    /*
     * This step is processor specific, connect the handler for the interrupt
     * controller to the interrupt source for the processor. Will be added later on.
     */
    // SetupInterruptSystem();

    /*
     * Cause (simulate) an interrupt so the handler will be called. This is
     * done by writing a 1 to the interrupt status bit for the device interrupt.
     * Write to Interrupt Status Register
     */
    XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_ISR_OFFSET, XPAR_ETC_0_O_INTERRUPT_MASK);
   

Here is an Simvision plot from our simulation. We can see that the irq output signal from the interrrupt controller goes high indicating an interrupt request.




Generate a hardware interrupt

Here is an example of a c-program to setup the interrupt controller and to generate a hardware interrupt.

     /*
     * Enable interrupts for all devices that cause interrupts.
     * Write to Interrupt Enable Register
     */
    XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_ETC_0_O_INTERRUPT_MASK);


    /*
     * Set the master enable bit. Enable hardware interrupts.
     * Write to Master Enable Register
     */
    XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK);

    /*
     * This step is processor specific, connect the handler for the interrupt
     * controller to the interrupt source for the processor. Will be added later on.
     */
    // SetupInterruptSystem();

     /*
     * Wait for the interrupt to be processed, if the interrupt does not
     * occur this loop will wait forever
     */
    while (1)
    {
        /*
         * If the interrupt occurred which is indicated by the global
         * variable which is set in the device driver handler, then
         * stop waiting
         */
        if (InterruptProcessed)
        {
            break;
        }
    }
 

Here is an Simvision plot from our simulation. We can see that the irq output signal from the interrrupt controller goes high after the ETC_INTERRUPT signal goes high, indicating a hardware interrupt request.





MicroBlaze interrupt handling

As it says in the Xilinx documentation:

Enable MicroBlaze interrupt handling

We will use the following c-program function to enable MicroBlaze interrupt handling:  microblaze_enable_interrupts();

MicroBlaze interrupt timing

This Simvision plot shows the MicroBlaze interrupt handling. It takes 70ns from when the ETC generates an interrupt until the MicroBlaze processor  reacts.





Top  Next  Previous

Debugging our hardware design

We have seen earlier how we can debug our software using Xilinx Microprocessor Debugger (XMD). Now let's see how we can debug our hardware. We could of course go out and buy an oscilloscope, a logic analyzer and voltmeter and hook them up to our development board. This is both expensive and complicated and it still wouldn't be possible to connect to internal nodes in the FPGA. A better solution is to use ChipScope Pro.

ChipScope Pro

As it says in the Xilinx documentation:
Here is document giving a glance of ChipScope Pro.

ChipScope Pro eliminates the traditional ASIC problems:

•     I Can't get internal access to signals in my hard IP"
•     Full scan insertion increases overhead"
•     How do I access the embedded system bus?"
•     It's too late – I can't afford a design re-spin!"
•     Co-Verification tools are cumbersome and slow with complex issues"
•     I need to debug my design at full system speed"

Trying out ChipScope Pro

ChipScope Pro costs 700USD to buy but we can get a 60 days evaluation license from Xilinx for free. Click "Evalaute ChipScope" to get a license and to download a copy of ChipScope Pro 9.2i from the Xilinx download center.



ChipScope installation

To install the ChipScope program we first unzip the downloaded file and store the archive in a temporary directory. We run the setup script file to install ChipScope in a directory we choose. In our case /home/svenand/cad/chipscope_9.2i.




Here is the installed directory structure for ChipScope.



Using ChipScope

I'll be back with more information on how to implement and use ChipScope. Stayed tuned.


Top  Previous  Next

Fixing our software device driver

Let's modify our template files and start with the .tcl file.

etc_v2_1_0.tcl

The .tcl script file copies the parameters we specify to the xparameters.h and xextc_g.c files during library generation. It looks like this after modifications.

proc generate {drv_handle} {
  set level [xget_value $drv_handle "PARAMETER" "level"]
  xdefine_include_file $drv_handle "xparameters.h" "XEtc" "NUM_INSTANCES" "MEM_BANK0_BASE_ADDR" "MEM_BANK0_HIGH_ADDR" "MEM_BANK1_BASE_ADDR" "MEM_BANK1_HIGH_ADDR" "REGISTER_BASE_ADDR" "REGISTER_HIGH_ADDR" "DEVICE_ID" "C_INTERRUPT_PRESENT"
  xdefine_config_file $drv_handle "xetc_g.c" "XEtc"  "DEVICE_ID" "MEM_BANK0_BASE_ADDR" "MEM_BANK1_BASE_ADDR" "REGISTER_BASE_ADDR" "C_INTERRUPT_PRESENT"
}

This is the result taken from the xparameters.h file.

/* Definitions for driver ETC */
#define XPAR_XETC_NUM_INSTANCES 1

/* Definitions for peripheral ETC_0 */
#define XPAR_ETC_0_MEM_BANK0_BASE_ADDR 0x42a08000
#define XPAR_ETC_0_MEM_BANK0_HIGH_ADDR 0x42a08fff
#define XPAR_ETC_0_MEM_BANK1_BASE_ADDR 0x42a09000
#define XPAR_ETC_0_MEM_BANK1_HIGH_ADDR 0x42a09fff
#define XPAR_ETC_0_REGISTER_BASE_ADDR 0x71A00000
#define XPAR_ETC_0_REGISTER_HIGH_ADDR 0x71A0001F
#define XPAR_ETC_0_DEVICE_ID 0
#define XPAR_ETC_0_INTERRUPT_PRESENT 0

etc_v2_1_0.tcl.mdd

The .mdd file looks like this. The "copyfiles" line instructs the EDK tools to copy the source files into the user's project directory and compile them from there.

OPTION psf_version = 2.1;

BEGIN driver etc

  OPTION supported_peripherals = (ETC_0);
  OPTION driver_state = ACTIVE;
  OPTION depends = (common_v1_00_a);
  OPTION copyfiles = all;

 BEGIN INTERFACE linux
 END INTERFACE

 BEGIN ARRAY interrupt_handler
 END ARRAY

END driver


Makefile

In the Makefile we have to add all header file under INCLUDEFILES. This will copy the header files to the directory include during library generation.

COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a

RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}

INCLUDEFILES=xetc.h xetc_l.h xetc_i.h

LIBSOURCES=*.c
OUTS = *.o


xetc_g.c

The xetc_g.c is automatically generated by Libgen. Here is the configuration table taken from the xetc_g.c file.

/*
* The configuration table for devices
*/

XEtc_Config XEtc_ConfigTable[] =
{
    {
        XPAR_ETC_0_DEVICE_ID,
        XPAR_ETC_0_MEM_BANK0_BASE_ADDR,
        XPAR_ETC_0_MEM_BANK1_BASE_ADDR,
        XPAR_ETC_0_REGISTER_BASE_ADDR,
        XPAR_ETC_0_INTERRUPT_PRESENT
    }

xetc.h

The following type definition are modified to match with the configuration table shown above.


/**
 * This typedef contains configuration information for the device.
 */
typedef struct
{
    Xuint16  DeviceId;          /* Unique ID  of device */
    Xuint32  Mem0_BaseAddress;  /* Memory bank0 base address */
    Xuint32  Mem1_BaseAddress;  /* Memory bank1 base address */
    Xuint32  Reg_BaseAddress;   /* Register bank base address */
    Xboolean InterruptPresent;  /* Are interrupts supported in h/w */
} XEtc_Config;

/**
 * The XEtc driver instance data. The user is required to allocate a
 * variable of this type for every ETC device in the system. A pointer
 * to a variable of this type is then passed to the driver API functions.
 */
typedef struct
{
    Xuint32  Mem0_BaseAddress;  /* Memory bank0 base address */
    Xuint32  Mem1_BaseAddress;  /* Memory bank1 base address */
    Xuint32  Reg_BaseAddress;   /* Register bank base address */
    Xuint32  IsReady;           /* Device is initialized and ready */
    XEtc_Config *ConfigPtr;     /* Pointer to the configuration */
} XEtc;

xetc_l.h

For the lowest level we only need to provide register read an write functions. We will use the Xilinx standard routines XIo_Out32 and XIo_in32 to give us these functions.

/****************************************************************************/
#define XEtc_mWriteReg(BaseAddress, RegOffset, Data) XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))

/****************************************************************************/
#define XEtc_mReadReg(BaseAddress, RegOffset)  XIo_In32((BaseAddress) + (RegOffset))

The XIo_Out32 and XIo_In32 are defined in the header file xio.h found in the include directory.

* Performs an input operation for a 32-bit memory location by reading from the
* specified address and returning the value read from that address.
*
* @param    InputPtr contains the address to perform the input operation at.
*
* @return   The value read from the specified input address.
*

#define XIo_In32(InputPtr)  (*(volatile Xuint32 *)(InputPtr))


* Performs an output operation for a 32-bit memory location by writing the
* specified value to the the specified address.
*
* @param    OutputPtr contains the address to perform the output operation at.
* @param    Value contains the value to be output at the specified address.
*
* @return   None.
*

#define XIo_Out32(OutputPtr, Value) (*(volatile Xuint32 *)((OutputPtr)) = (Value))


Writing an application program

We will start out writing a low level application program only using the read/write functions. Here is an example:

//$$INCLUDE
/*************************************************************************/
/*                                                                       */
/*                     I N C L U D E   H E A D E R   F I L E S           */
/*                                                                       */
/*************************************************************************/

#include "xparameters.h"
#include "xetc.h"
#include "xetc_l.h"
#include "xutil.h"
#include <stdio.h>


//$$DEFINE
/*************************************************************************/
/*                                                                       */
/*                       D E F I N E   C O N S T A N T S                 */
/*                                                                       */
/*************************************************************************/

// The following constant maps to the name of the hardware instances that
// were created in the EDK XPS system.

#define  ETC_REG_BASEADDR      XPAR_ETC_0_REGISTER_BASE_ADDR
 
// The following parameters are used to setup the ETC
#define  ENABLE_INTERRUPT      0X1000
#define  DISABLE_INTERRUPT     0X0
#define  ENABLE_LOOP_MODE      0x800
#define  DISABLE_LOOP_MODE     0x0
#define  SKIP_TDO_SHIFTIR      0x200
#define  SKIP_TDO_SHIFTDR      0x400
#define  DISABLE_SINGLE_STEP   0x0
#define  ENABLE_SINGLE_STEP    0x100
#define  DISABLE_TCK           0x0
#define  ENABLE_TCK            0x80
#define  CLOCK_RATE_DIV_BY_4   0x0
#define  CLOCK_RATE_DIV_BY_8   0x10
#define  CLOCK_RATE_DIV_BY_16  0x20
#define  CLOCK_RATE_DIV_BY_32  0x30
#define  CLOCK_RATE_DIV_BY_64  0x40
#define  EXTERNAL_TEST         0x8

#define  START_ETC             0x1
#define  STOP_ETC              0x0

//$$FUNCTIONS
/*************************************************************************/
/*                                                                       */
/*                       D E F I N E   F U N C T I O N S                 */
/*                                                                       */
/*************************************************************************/

void usleep(unsigned int useconds)
{
  int i,j;
  for (j=0;j<useconds;j++)
    for (i=0;i<26;i++) asm("nop");
}

//$$ETC TEST PROGRAM
/*************************************************************************/
/*                                                                       */
/*                     E T C   T E S T  P R O G R A M                    */
/*                                                                       */
/*************************************************************************/


// Define testprogram

// TestResetKeepingTrstzLow (10);
// LoadInstruction(INSTRUCTION_LENGTH,IDCODE);
// ReadWriteDataRegister(IdentificationRegLen+20,{{IdentificationRegLen{1'b0}},20'b1110011101});
// SetExpectedData(IdentificationRegLen+20,{20'b1110011101,{IdentificationRegLen{1'bx}}});
// EndOfTestProgram;

 Xuint32 TestProgram[] = {
     
  0x800000a1,
  0xc0000043,
  0x00000002,
  0xc0340004,
  0x4000039d,
  0x00000000,
  0x8000000c };
 
  int  ProgramSize =  7;


//$$MAIN
/*************************************************************************/
/*                                                                       */
/*                        M A I N   P R O G R A M                        */
/*                                                                       */
/*************************************************************************/


int main(void) {

    int               i;
    Xuint32  StatusReg;
   
    print("Load test program ");
   
    // Load test program to test program RAM
    for (i = 0; i < ProgramSize; i++) {
           XEtc_mWriteReg(XPAR_ETC_0_MEM_BANK0_BASE_ADDR, i*4, TestProgram[i]);   
    };

    // Write to control register
    XEtc_mWriteReg(ETC_REG_BASEADDR, XETC_CONTROL_REG_OFFSET,
        DISABLE_INTERRUPT +
        DISABLE_LOOP_MODE +
        SKIP_TDO_SHIFTIR +
        DISABLE_SINGLE_STEP +
        ENABLE_TCK +
        CLOCK_RATE_DIV_BY_4 +
        EXTERNAL_TEST);
   
    print("Start test ");
    // Start test
    XEtc_mWriteReg(ETC_REG_BASEADDR, XETC_EXECUTE_REG_OFFSET,
        START_ETC);
 
   // Wait for test to finish
   usleep(4);

    print("Stop test ");
    // Stop test
    XEtc_mWriteReg(ETC_REG_BASEADDR, XETC_EXECUTE_REG_OFFSET,
        STOP_ETC);
       
    // Stop TCK
    XEtc_mWriteReg(ETC_REG_BASEADDR, XETC_CONTROL_REG_OFFSET,
        DISABLE_INTERRUPT +
        DISABLE_LOOP_MODE +
        SKIP_TDO_SHIFTIR +
        DISABLE_SINGLE_STEP +
        DISABLE_TCK +
        CLOCK_RATE_DIV_BY_4 +
        EXTERNAL_TEST);

   // Read status register
   print("Read status register ");  
   StatusReg = XEtc_mReadReg(ETC_REG_BASEADDR, XETC_STATUS_REG_OFFSET);
   xil_printf("Status reg : %x ",StatusReg);


   return 0;
   
    }

Print statements

To save memory space we don't use the standard print routines like printf. Instead we use <xil_printf>and <print>.  


Printout from program

After compiling and linking the program we download it to our design. The program starts and prints out the following text:

Load test program
Start test
Stop test
Read status register
Status reg : 3464


The value in the status register tells us that the testprogram ran successfully. We have written our first application program to drive the ETC. One more milestone reached.

Generate HDL simulation files

We can use the following command from the commandline to generate the HDL simulation files.

==> cd /home/svenand/root/projects/ETC/xps
==> simgen -f simgen.opt

Here is the output:

Simulation Model Generator
Xilinx EDK 9.1.01 EDK_J_SP1.3
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Command Line: simgen -p xc4vfx12ff668-10 -lang vhdl -pe microblaze_0
SDK_projects/ETC_system_program/Debug/ETC_system_program.elf -mixed yes -s ncs
-tb -X /home/svenand/root/projects/ETC/verification/database/ncsim/macrolib/ -E
/home/svenand/root/projects/ETC/verification/database/ncsim/edklib/ -m
behavioral ETC_system.mhs

MHS file              : /home/svenand/root/projects/ETC/xps/ETC_system.mhs
Language (-lang)      : VHDL
Simulation Model (-m) : Behavioral
Simulator (-s)        : NcSim (NCS)
Part (-p) [ family ]  : xc4vfx12ff668-10 [ virtex4 ]
Output directory (-od): /home/svenand/root/projects/ETC/xps/

Edklib (-E) :
/home/svenand/root/projects/ETC/verification/database/ncsim/edklib/
Xlib (-X)   :
/home/svenand/root/projects/ETC/verification/database/ncsim/macrolib/

..........

Analyzing file
/home/svenand/root/projects/ETC/xps/SDK_projects/ETC_system_program/Debug/ETC_sy
stem_program.elf...
INFO:MDT - BRAM lmb_bram will be initialized with ELF of processor microblaze_0
Running Data2Mem with the following command:
data2mem -bm ETC_system_sim.bmm  -bd
/home/svenand/root/projects/ETC/xps/SDK_projects/ETC_system_program/Debug/ETC_sy
stem_program.elf tag microblaze_0  -u  -o u tmpucf.ucf

Generating simulator compile script ...

Generating the BRAM initialization file

If we only changed the application program file (.elf) we don't have to generate all the HDL simulation files. We only need the BRAM initialization file:  ETC_system_init.vhd. This file can generated in these two steps:

1. Use data2mem to convert the .elf file to a .ucf file
2. Use ucf2vhdl.pl to convert the .ucf file to a .vhdl file
   

==> cd /home/svenand/root/projects/ETC/xps/simulation/behavioral

==> data2mem -bm ETC_system_sim.bmm  -bd /home/svenand/root/projects/ETC/xps/SDK_projects/ETC_system_program/Debug/ETC_sy
stem_program.elf tag microblaze_0  -u  -o u tmpucf.ucf

==> xilperl /home/svenand/cad/edk91i/bin/lin/ucf2vhdl.pl tmpucf.ucf ETC_system_init.vhd ETC_system ETC_system_conf vhdl

Running a simulation

Here is the same application program running in a simulation.




Top  Next  Previous

How good is our virtual machine and is there a difference between Parallels Desktop and VMware Fusion when it comes to execution speed. Let's find out.  We will benchmark the two. Here is what we have.

Hardware

MacBook Intel Core 2 Duo. 2.0 GHz with 1Gb of memory.

Host software

Mac OS X 10.4.10 and the virtual machines Parallels Desktop 3.0 and VMware Fusion 1.0.


Virtual machine software

Ubuntu Linux 7.04 Feisty


Virtual machine setup

512 Mb of memory. One virtual CPU.

Applications

We will use the following Xilinx FPGA tools in our benchmark.

• Netlist generation
• Bitstream generation

The netlist generation tool runs the Xilinx tool XST to synthesis a complete FPGA design. The bitstream generation tool does the  place and route of the whole design and generates the bitstream to configure the FPGA. Both tools are very compute intensive, using more than 90% of the processor time.


Result

Task	Execution time [s] Parallels Desktop	Execution time [s] VMware Fusion
Netlist generation	585	556
Bitstream generation	255	245

Conclusion

The difference between the two virtual machines is very small and that is what we expected. This benchmark is not very comprehensive and should not be used as a deciding factor.