Before we run Simgen let's make sure we have our software project selected in Xilinx Platform Studio. We also make sure we ticked the Marked for BRAM initialization (right-click Project: ETC_system_program).



We invoke Simgen from the Xilinx Platform Studio using the menu command: Simulation->Generate HDL Simulation Files. When the Simgen program has finished we find a new sub directory (simulation) in our xps directory.

  -- Clock generator for fpga_0_DDR_CLK_FB

  process
  begin
    fpga_0_DDR_CLK_FB <= '0';
    loop
      wait for (fpga_0_DDR_CLK_FB_PERIOD/2);
      fpga_0_DDR_CLK_FB <= not fpga_0_DDR_CLK_FB;
    end loop;
  end process;

  -- Clock generator for sys_clk_pin

  process
  begin
    sys_clk_pin <= '0';
    loop
      wait for (sys_clk_pin_PERIOD/2);
      sys_clk_pin <= not sys_clk_pin;
    end loop;
  end process;

  -- Reset Generator for sys_rst_pin

  process
  begin
    sys_rst_pin <= '0';
    wait for (sys_rst_pin_LENGTH);
    sys_rst_pin <= not sys_rst_pin;
    wait;
  end process;

  -- START USER CODE (Do not remove this line)

  -- User: Put your stimulus here. Code in this
  --       section will not be overwritten.

  -- END USER CODE (Do not remove this line)

end architecture STRUCTURE;

configuration ETC_system_tb_conf of ETC_system_tb is
  for STRUCTURE
    for all : ETC_system
      use configuration work.ETC_system_conf;
    end for;
  end for;
end ETC_system_tb_conf;


Modifying the testbench file

We normally run all our simulations in batch mode and we need a simple way to tell how long the simulation will run. Here is one method to run 80000 ns after reset is released.

  process
  begin
    sys_rst_pin <= '0';
    wait for (sys_rst_pin_LENGTH);
    sys_rst_pin <= not sys_rst_pin;
    wait for 800000 ns;
    assert false report "NONE. End of simulation." severity failure;
  end process;


Compiling the BRAM initialization file

We compile the ETC_system_init.vhd together with the wrapper files and store it in the top library.

Compiling the testbench file

We compile the ETC_system_tb.vhd testbench file into the ETC_system_tb library and after elaboration we have the following database structure.



Simulating program execution

Here is the whole sequence to add a new application program to our simulation environment.

1. Compile and link the program
2. Convert the ELF file to a BRAM memory image (ETC_system_init.vhd)
   
3. Compile the ETC_system_init.vhd using ncvhdl
4. Elaborate everything using ncelab
5. Run the simulation using ncsim (ETC_SYSTEM_TB_CONF)
6. Save the waveforms
7. When the simulation has finish look at the waveforms in Simvision.
   

Here is the program.

// The following constant maps to the name of the hardware instances that
// were created in the EDK XPS system.
 
#define GPIO_LCD_DEVICE_ID    XPAR_LCD_16X2_DEVICE_ID
#define GPIO_LED4_DEVICE_ID   XPAR_LEDS_4BIT_DEVICE_ID
#define GPIO_LEDP_DEVICE_ID   XPAR_LEDS_POSITIONS_DEVICE_ID

// The following constant is used to determine which channel of the GPIO is
// used if there are 2 channels supported.

#define LCD_CHANNEL 1
#define LED_CHANNEL 1

// The following are declared globally so they are zeroed and so they are
// easily accessible from a debugger

XGpio GpioLCD;     /* The Instance of the GPIO LCD Driver */
XGpio GpioLED4;    /* The Instance of the GPIO LED4 Driver */
XGpio GpioLEDPOS;  /* The Instance of the GPIO LEDPOS Driver */

int main(void) {  

     XStatus Status;
   
    // Initialize the GPIO component
    Status = XGpio_Initialize(&GpioLCD, GPIO_LCD_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
    Status = XGpio_Initialize(&GpioLED4, GPIO_LED4_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
    Status = XGpio_Initialize(&GpioLEDPOS, GPIO_LEDP_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
  
    // Set the direction for all bits to be outputs
    XGpio_SetDataDirection(&GpioLCD,    LCD_CHANNEL, 0x00);  
    XGpio_SetDataDirection(&GpioLED4,   LED_CHANNEL, 0x00);
    XGpio_SetDataDirection(&GpioLEDPOS, LED_CHANNEL, 0x00);
     
    // Turn on LEDs
    XGpio_DiscreteWrite(&GpioLED4,   LED_CHANNEL, 0xa);  
    XGpio_DiscreteWrite(&GpioLEDPOS, LED_CHANNEL, 0xa);
    // Write to LCD
    XGpio_DiscreteWrite(&GpioLCD,    LCD_CHANNEL, 0xa);
      
    return XST_SUCCESS;

  }

Here is the result.




The simulation runs as expected. One more milestone reached.

To allow for 64 bit addressing two 32 bit worlds are reserved for each vector.

Reset sequence



When a Reset occurs, MicroBlaze flushes the pipeline and starts fetching instructions from the reset vector (address 0x0). The external reset signal is active high and should be asserted for a minimum of 16 cycles.

The branch instruction <b

• Set up any reset, interrupt, and exception vectors as required.
• Set up stack pointer, small-data anchors, and other registers. Refer to Table 10-9 for details.
• Clear the BSS memory regions to zero.
• Invoke language initialization functions, such as C++ constructors.
• Initialize the hardware sub-system.
  
• Set up arguments for the main procedure and invoke it.

• Invoke language cleanup functions, such as C++ destructors.
• De-initialize the hardware sub-system. For example, if the program is being profiled, clean up the profiling sub-system.

1. Clears the .bss section to zero.
2.  Invokes _program_init.
3.  Invokes "constructor" functions (__init).
4. Sets up the arguments for main and invokes main.
5. Invokes "destructor" functions (__fini).
6. Invokes _program_clean and returns.

C program

Here is the first program we are going to use. We load the code into SDK and compile and link it and then convert the load module to a memory image that we can use in our simulation.

#include "xparameters.h"

#define poke(addr,val)     (*(unsigned char*) (addr) = (val))
#define pokew(addr,val)    (*(unsigned*) (addr) = (val))
#define peek(addr)         (*(unsigned char*) (addr))
#define peekw(addr)        (*(unsigned*) (addr))

int main(void) {  

   unsigned char byte_of_data;
   unsigned      word_of_data;
   int           i,j;
 
   // Define GPIO bus as outputs only
   pokew(XPAR_LCD_16X2_BASEADDR+4,0x00);
  
   // Write data to LCD
   pokew(XPAR_LCD_16X2_BASEADDR,0x7f);
   pokew(XPAR_LCD_16X2_BASEADDR,0x00);
   pokew(XPAR_LCD_16X2_BASEADDR,0x2a);
  
   // Stay in this loop
   while(1);
  
   return 0;
  
  }

Program execution

Here is the result.




Looks perfectly fine to me. So far so good. Let's do the same thing using the Xilinx's software drivers. Like this:

//$$INCLUDE
/*************************************************************************/
/*                                                                       */
/*                I N C L U D E   H E A D E R   F I L E S                */
/*                                                                       */
/*************************************************************************/

#include "xparameters.h"
#include "xgpio.h"

//$$DEFINE
/*************************************************************************/
/*                                                                       */
/*                  D E F I N E   C O N S T A N T S                      */
/*                                                                       */
/*************************************************************************/

// The following constant maps to the name of the hardware instances that
// were created in the EDK XPS system.
 
#define GPIO_LCD_DEVICE_ID    XPAR_LCD_16X2_DEVICE_ID

// The following constant is used to determine which channel of the GPIO is
// used for the LCD if there are 2 channels supported.

#define LCD_CHANNEL 1

// The following are declared globally so they are zeroed and so they are
// easily accessible from a debugger

XGpio GpioLCD;     /* The Instance of the GPIO Driver */

//$$MAIN
/*************************************************************************/
/*                                                                       */
/*                        M A I N   P R O G R A M                        */
/*                                                                       */
/*************************************************************************/

int main(void) {  

    XStatus Status;
   
    // Initialize the GPIO component
    Status = XGpio_Initialize(&GpioLCD, GPIO_LCD_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
 
    // Set the direction for all bits to be outputs
    XGpio_SetDataDirection(&GpioLCD,    LCD_CHANNEL, 0x00000000);  
 
    // Write data
    XGpio_DiscreteWrite(&GpioLCD,    LCD_CHANNEL, 0x7f);
    XGpio_DiscreteWrite(&GpioLCD,    LCD_CHANNEL, 0x00);
    XGpio_DiscreteWrite(&GpioLCD,    LCD_CHANNEL, 0x2a);
    while(1);
    return XST_SUCCESS;

  }

Before we continue to compile and build a complete application program let's take a look at Xilinx software platform.

Generating the software libraries and BSPs

For more information about Libgen, refer to the "Library Generator (Libgen)" chapter in the Embedded System Tools Reference Manual. For more information on libraries and device drivers, see the OS and Libraries Document Collection.

The software library for the project is created in the project area:  .../microblaze_0/lib/libxil.a
The address map of the system is created in the header file:  .../microblaze_0/include/xparameters.h

A status message appears in the Console window at the bottom of the SDK main window.

• C Compiler (cc1) – The compiler is responsible for most of the optimizations done on the input C code and generating assembly code.
• C++ Compiler (cc1plus) – The compiler is responsible for most of the optimizations done on the input C++ code and generates assembly code.
  

• C source files
• C++ source files
• Assembly files
• Object files
• Linker scripts

• An ELF file; the default output file name is a.out
• Assembly file, if -save-temps or -S option is used
• Object file, if -save-temps or -c option is used
• Preprocessor output, .i or .ii file, if -save-temps option is used

(SDK) from Xilinx to help us accomplish the task. We start SDK from within Xilinx Platform Studio (XPS) using the menu command Software->Launch Platform Studio SDK.




To find out more about how to use SDK we select the Help menu.



When we click the Getting Started book the SDK design checklist is displayed in our web browser.



We are going to use available software drivers in our program. Let's find out how do that by studying the SDK design checklist.

SDK platform settings

Select Xilinx Tools->Software Platform Settings to look at the available software drivers and the current version used.




C program build

Select the menu Project->Properties to display the program build settings.



C header files

We find all header files in the directory .../SDK_projects/microblaze_0_sw_platform/microblaze_0/include.



The file xparameters.h holds information about the LCD_16x2 module. We will include this file in our c-program.

/* Definitions for peripheral LCD_16X2 */
#define XPAR_LCD_16X2_BASEADDR 0x41F0C000
#define XPAR_LCD_16X2_HIGHADDR 0x41F0CFFF
#define XPAR_LCD_16X2_DEVICE_ID 3
#define XPAR_LCD_16X2_INTERRUPT_PRESENT 0
#define XPAR_LCD_16X2_IS_DUAL 0

The GPIO API definitions

The header file xgpio.h contains the software

definition of the Xilinx General Purpose I/O (XGpio) device driver component. This file will also be included in our c-program.


C program examples

We are not going to re-invent the wheel. Let's look for some good examples to copy. In the directory .../edk91i/sw/XilinxProcessorIPLib/drivers/gpio_v2_01_a there are a few good ones.



More program examples

Looking in the directories of the reference system CD the following example files were found (xrom_lcd.c and xrom_lcd.h).



Let's use the functions declared in xrom_lcd.h.

Main program

//$$DEFINE
/*************************************************************************/
/*                                                                       */
/*                  I N C L U D E  &   D E F I N E                       */
/*                                                                       */
/*************************************************************************/

  #include "xparameters.h"
  #include "xgpio.h"
  #include "xutil.h"
  #include "stdio.h"
  #include "xrom_lcd.h"

  // The following constant maps to the name of the hardware instances that
  // were created in the EDK XPS system.
 
  #define GPIO_LCD_DEVICE_ID    XPAR_LCD_16X2_DEVICE_ID
  #define GPIO_LED4_DEVICE_ID   XPAR_LEDS_4BIT_DEVICE_ID
  #define GPIO_LEDP_DEVICE_ID   XPAR_LEDS_POSITIONS_DEVICE_ID

  // The following constant is used to determine which channel of the GPIO is
  // used for the LCD if there are 2 channels supported.

  #define LCD_CHANNEL 1
  #define LED_CHANNEL 1

  // The following are declared globally so they are zeroed and so they are
  // easily accessible from a debugger

  XGpio GpioLCD;     /* The Instance of the LCD GPIO Driver */
  XGpio GpioLED4;    /* The Instance of the LED4 GPIO Driver */
  XGpio GpioLEDPOS;  /* The Instance of the LED Pos GPIO Driver */
 

1. Specify the ELF file to be marked for block RAM (BRAM) initialization by selecting Device Configuration > Program Hardware Settings
2. Select the initialization file (Bootloop, XMDStub, or ELF file) and click Save.

Set address range

We will select a 4k address range and click Generate Addresses to define the Base Address and the High Address for the IP block.



Connecting ports

We will make GPIO_IO an external port. All other ports are left unconnected.




The easy way to add a new block

Probably the easiest way to add a new peripheral is to edit the ETC_system.mhs file. This file will be read when we start XPS and the information will be displayed in the System Assembly window. To add a new GPIO block we can copy one of the existing GPIO block and edit the information to fit our new block. Like this:

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = mb_opb
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

Copy, paste and edit.

BEGIN opb_gpio
 PARAMETER INSTANCE = LCD_16x2
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 7
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x41f0c000
 PARAMETER C_HIGHADDR = 0x41f0cfff
 BUS_INTERFACE SOPB = mb_opb
 PORT GPIO_IO = LCD_16x2_GPIO_IO
END

The next time we start Xilinx Platform Studio the LCD_16x2_GPIO_IO block will be added.


Configure the IP block

Before we can configure the IP block we need to know more about the LCD display on the ML403 evaluation board. Let's read the

.


                                                                                                                                                                   

8-bit write operation

After initial display communication is established, all data transfers are 8-bit ASCII character codes, data bytes or 8-bit addresses. Each 8-bit transfer obviously has to be decomposed into two 4-bit transfers which must be spaced by at least 1μs. Following an 8-bit write operation, there must be an interval of at least 40μs before the next communication. This delay must be increased to 1.64ms following a clear display command.



Programming sequence

Here are all the steps needed to send an 8 bit instruction to the LCD driver in 4 bit mode:

1. Keep LCD_RW low (write mode)
   
2. Set LCD_RS high (data mode)
3. Put data bits 7:4 on the bus (LCD_D7:LCD_D4)
4. Wait 100ns
   
5. Set LCD_E high
6. Wait 300ns
7. Set LCD_E low
8. Wait 1500ns
   
9. Put data bits 3:0 on the bus (LCD_D7:LCD_D4)
10. Wait 100ns
11. Set LCD_E high
12.  Wait 300ns
13. Set LCD_E low
14. Wait 60us
    

• Connect LCD to MicroBlaze using an OPB customer peripheral
• Initial design for Spartan-3E Starter KIT (LCD display control)

It looks like we need seven General Purpose IO pins to control the LCD display. The rest is software. We will set the GPIO Data Bus Width to 7 and leave everything else untouched.




Adding constraints

The following constraints will be added to the constraints file .../ETC/xps/data/ETC_system.ucf

#### Module LCD_16x2 constraints

NET "LCD_16x2_GPIO_IO_pin<0>" LOC="AE13" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<1>" LOC="AC17" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<2>" LOC="AB17" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<3>" LOC="AF12" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<4>" LOC="AE12" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<5>" LOC="AC10" | IOSTANDARD = LVCMOS33 | TIG ;

• ML403 Embedded Processor Reference System (MicroBlaze-based)
• ML403 Embedded Processor Reference System (PoerPC 405-based)
• ML403 DCM Phase Shift Reference System (MicroBlaze-based)

Hardware setup

Before we start running application programs. Let's take a look at our hardware setup.

1. Apple MacBook Intel Core 2 Duo, Mac OS X 10.4.9. VMware Fusion virtual machine with Ubuntu 7.04 installed.
2. Apple PowerBook G4  setup as a VT100 terminal emulator.  The screen program emulates the HyperTerminal program. We can use any terminal we have available. We just happened to have a PowerBook lying around doing nothing.
   
3. Apple CInema Display 23", the main display where ISE and EDK windows are displayed.
4. Xilinx Platform Cable USB used to communicate with the ML403 evaluation board.
5. Keyspan USB to Serial converter for connecting to the VT100 terminal.
   
6. Xilinx ML403 evaluation board.
   

                                                                               (system.bit should be download.bit)

Download and execute a simple program

We will use the memory test program TestApp_Memory.c as our first simple example to see if the hardware and software will function on our board.



Start the Xilinx Platform Studio

==> xps &



Download the bitstream

The file system.bit, created after hardware generation (completion of Xflow), is an uninitialized bitstream and does not include the ELF file. It is only when we execute the command to download or update the bitstream that the system.bit and ELF files merge into download.bit.

When we select Device Configuration > Download Bitstream, XPS downloads the bitstream (download.bit file) onto the target board using iMPACT in batch mode. XPS uses the file etc/download.cmd for downloading the bitstream. Because XPS tools are makefile based, the download button calls on the makefile and executes the steps necessary to create the bitstream with the Executable Linked Format (ELF) file populated within the bitstream.

Get program size

To ensure that the compiled TestApp_Memory code fits into the BRAM we will use the command Software->Get Program Size.

At Local date and time: Mon Jun  4 19:46:49 2007
 mb-size /home/svenand/root/projects/ETC/xps/TestApp_Memory/executable.elf started...
   text       data        bss        dec        hex    filename
   3944        332       2064       6340       18c4    /home/svenand/root/projects/ETC/xps/TestApp_Memory/executable.elf

Done!

Running the program

After we downloaded the bitstream the included program will start executing and display the result in the VT100 terminal.



The DDR SDRAM test program TestApp_Memory executes and it passes. We have reach one more

.

• DesignF/X
• Mentor I/O Designer
• Oleda Technologies
• Xilinx PACE (Pinout and Area Constraint Editor)
• Xilinx Floorplanner
• Xilinx PlanAhead
• Topi Top Code Generator

ISE includes PACE (Pinout and Area Constraints Editor), a powerful, yet fast and easy way to map design pins to your device, and floorplan logic areas. Drag-and-drop pins onto a graphical display of the device, group pins logically by color-coding for easy recognition, specify I/O standards and banks, assign and place differential I/Os, and much more. As devices grow ever larger, PACE brings a new level of ease to the difficult task of assigning design pins.

Running PACE

Let's start the PACE program.

==> pace &

/home/svenand/cad/xilinx91i/bin/lin/_pace: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory

To fix this problem we have to load the following Ubuntu packages:
libmotif3
libmotif-dev

==> pace &

 Wind/U X-toolkit Error: wuDisplay: Can't open display

We have to change the DISPLAY variable from :0.0 to :0

==> export DISPLAY=:0
==> pace &





We specify our constraints file ETC_system.ucf as the input file to PACE and click OK.

PACE allows you to edit both location and area constraints, define logic areas graphically, and display I/Os on the periphery for connectivity checking. PACE allows area mapping by examining the defined HDL hierarchy and checks logic areas against expected gate size, making area definitions quick, accurate, and easy. Pins can be assigned using PACE before HDL coding has even started, and then write the HDL starting templates for you to edit. Pin information can be exported or imported to PCB layout editors through standard CSV files, greatly simplifying the design planning stage.

PACE contains built-in design rule checks like Simultaneous Switching Outputs to help predict ground bounce problems, unique displays like Package Flight Time allow you to see I/O to package lead delays for super-accurate timing.

is all about. When designing an FPGA with more than 1000 signal pins you need an exact and precise way of adding all the signal names. Topi will help you generate the top testbench, the top instantiation and the FPGA pin layout, all in the same tool.


Topi Setup

Using Topi to modify the Xilinx user constraints file

Let's start Topi.
==> topi &



We open the Setup->Pin Table window and select the Xilinx CSV table format.




Let's load the Xilinx CSV file into the Topi Spreadsheet Editor.

The next step is to import the pin layout information into the Topi Pin Layout Editor. From the Load menu we select Pin Names (Match Package Balls).

The Xilinx Floorplanner enables designers to plan a design prior to or after using Place-and-Route (PAR) software. Invoking Floorplanner after a design has been placed and routed allows designers to view and possibly improve the results of the automatic implementation. In an iterative floorplan design flow, designers floorplan and place and route interactively.

When we started the PACE program we were told it will be replaced by the Floorplanner program. Why not give it a try.

==> floorplanner &



We enter the name of the ngd file and all the other files are found automatically. Click OK.




Viewing pin placement

If we select view Package Pins from the View menu we get the following display.




Xilinx PlanAhead

Here is an article about using

Using the iMPACT configuration tool

After we have connected the USB JTAG programming cable and started iMPACT it will detect the JTAG chain on the ML403 evaluation board and display it in the boundary scan window.



The FPGA, Platform Flash memory, and CPLD can be configured through the JTAG

The Virtex-4 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the instruction register, the instruction decoder, the Boundary-Scan register, and the bypass register. The Virtex-4 family also supports a 32-bit identification register and a configuration register in full compliance with the standard.


                                                                                                                               (Courtesy of Xilinx)
The identification register

Virtex devices have a 32-bit identification register called the IDCODE register. The IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being addressed. This register allows easy identification of the part being tested or programmed by Boundary-Scan, and it can be shifted out for examination by using the IDCODE instruction.

Read IDCODE

Select one of the devices displayed in the Boundary Scan window and and double-click the Get Device ID entry in the Operations window. The result is displayed in the Output window.

Configuring and programming are often used interchangeably. However, there is a distinction between these two terms. Configuration refers to the process of loading design-specific data into one or more volatile FPGAs using an external data source such as a PROM. Programming refers to the process of loading design-specific data into one or more non-volatile PROMs or CPLD devices. Configuring or programming a device defines the functional operations of the device. For simplification, we refer both configuring and programming as the device configuration. For general configuration guidelines, see XAPP501 Application Note.

Now when we are confident about our usb cable connection we are ready for the final step, downloading the bitstream to the FPGA device. We will start Xilinx Platform Studio (xps) to help us do the job.

==> cd $ETC_PROJECT
==> xps



To start the bitstream download select Device Configuration->Download Bitstream. The result is displayed in the output window. It says Programmed successfully.