Adding a 16x2 character LCD display

To write the "Hello world" program we need a place to display the greeting. We will add an LCD display. We are going to use the General Purpose IO interface to drive the LCD display. In the IP catalog we open the General Purpose IO entry and choose the OPB General Purpose IO and select Add IP from the menu. For more information about adding a new IP block see Part 17.

Set address range

We will select a 4k address range and click Generate Addresses to define the Base Address and the High Address for the IP block.

Connecting ports

We will make GPIO_IO an external port. All other ports are left unconnected.

The easy way to add a new block

Probably the easiest way to add a new peripheral is to edit the ETC_system.mhs file. This file will be read when we start XPS and the information will be displayed in the System Assembly window. To add a new GPIO block we can copy one of the existing GPIO block and edit the information to fit our new block. Like this:

BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_4Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
END

Copy, paste and edit.

BEGIN opb_gpio
PARAMETER INSTANCE = LCD_16x2
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 7
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 1
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x41f0c000
PARAMETER C_HIGHADDR = 0x41f0cfff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_IO = LCD_16x2_GPIO_IO
END

The next time we start Xilinx Platform Studio the LCD_16x2_GPIO_IO block will be added.

Configure the IP block

Before we can configure the IP block we need to know more about the LCD display on the ML403 evaluation board. Let's read the ML403 User Guide. Here is what it has to say about the LCD display:

The ML403 board has a 16-character x 2-line LCD (Lumex LCM-S01602DTR/M) on the board to display text information. Potentiometer R1 adjusts the contrast of the LCD. The data interface to the LCD is connected to the FPGA to support 4-bit mode only. A level translator chip is used to shift the voltage level between the FPGA and the LCD.

The Spartan-3A Starter Kit Board User Guide gives us some more information about the LCD display (see chapter 5), but observe that this is not the same implementation as used on the ML403 board. To find out more about the LCD implementation on the ML403 board we take a look at the schematics.

(Courtesy of Xilinx)
The LCD driver

The LCD driver used on the ML403 board is a Samsung S6A0069 dot matrix LCD driver & controller LSI device. It can display 1 or 2 lines with a 5x8 or a 5x11 dots matrix. It can be set to use an 8 bit or 4 bit data bus. On the ML403 board the bus is 4 bits.

RS	RW	Operation
L	L	Instruction write operation (MPU writes instruction code into IR)
L	H	Read Busy Flag (DB7) and address counter
H	L	Data write operation (MPU writes data into DR)
H	H	Data read operation (MPU reads data from DR)

LCD display timing

The LCD display is a practical way to display a variety of information using standard ASCII characters and even allows you to create some of your own. However, these displays are not fast. This design scrolls the display at 0.5 second intervals and that really is the practical limit for clarity. This low performance rate also relates to the signals used for communication. Compared with a Virtex-4 operating at 100MHz, the display can appear extremely slow. This is where MicroBlaze can be used to efficiently implement timing delays as well as control the actual content of the display.

4-bit write operation

This timing diagram shows a single write operation being performed. The diagram is approximately to scale showing the minimum times allowed for setup, hold and enable pulse length relative to a 50MHz clock (20ns period). The data D[7:4], Register Select (RS) and write control (RW) must be set up at least 40ns before the enable E goes High. Enable must be High or at least 230ns which is almost 12 clock cycles at 50MHz. In our write only system, the R/W signal can be tied Low permanently.

8-bit write operation

After initial display communication is established, all data transfers are 8-bit ASCII character codes, data bytes or 8-bit addresses. Each 8-bit transfer obviously has to be decomposed into two 4-bit transfers which must be spaced by at least 1μs. Following an 8-bit write operation, there must be an interval of at least 40μs before the next communication. This delay must be increased to 1.64ms following a clear display command.

Programming sequence

Here are all the steps needed to send an 8 bit instruction to the LCD driver in 4 bit mode:

Keep LCD_RW low (write mode)
Set LCD_RS high (data mode)
Put data bits 7:4 on the bus (LCD_D7:LCD_D4)
Wait 100ns
Set LCD_E high
Wait 300ns
Set LCD_E low
Wait 1500ns
Put data bits 3:0 on the bus (LCD_D7:LCD_D4)
Wait 100ns
Set LCD_E high
Wait 300ns
Set LCD_E low
Wait 60us

Display setup

Before the display can be used for the first time, there is an initialisation sequence which must be followed to allow communication to take place. These sequences are ideally suited to an processor such as MicroBlaze. Besides the relative complexity of the sequence, the process is only executed once and then the processor is available to perform other tasks including the control on the display itself.

More reading

Signal wiring on the ML403 board

Signal Name	Description	GP IO pin	FPGA Pin Location
LCD_E	Read/Write Enable Pulse 0: Disabled 1: Read/Write operation enabled	0	AE13
LCD_RS	Register Select 0:Instruction register during write 1:Data for read or write operation	1	AC17
LCD_RW	Read/Write Control 0:Write, LCD accepts data 1:Read, LCD presents data	2	AB17
LCD_DB7	Data Bus bit 7	3	AF12
LCD_DB6	Data Bus bit 6	4	AE12
LCD_DB5	Data Bus bit 5	5	AC10
LCD_DB4	Data Bus bit 4	6	AB10

It looks like we need seven General Purpose IO pins to control the LCD display. The rest is software. We will set the GPIO Data Bus Width to 7 and leave everything else untouched.

Adding constraints

The following constraints will be added to the constraints file .../ETC/xps/data/ETC_system.ucf

#### Module LCD_16x2 constraints

NET "LCD_16x2_GPIO_IO_pin<0>" LOC="AE13" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<1>" LOC="AC17" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<2>" LOC="AB17" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<3>" LOC="AF12" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<4>" LOC="AE12" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<5>" LOC="AC10" | IOSTANDARD = LVCMOS33 | TIG ;
NET "LCD_16x2_GPIO_IO_pin<6>" LOC="AB10" | IOSTANDARD = LVCMOS33 | TIG ;

Generate Netlist

After adding the new IP block we have to rerun netlist generation Hardware->Generate Netlist. The netlist generation generates a number of warnings but finish successfully.

WARNING:MDT - INST:dcm_1 PORT:LOCKED CONNECTOR:dcm_1_lock -
   /home/svenand/root/projects/ETC/xps/ETC_system.mhs line 306 - floating
   connection!

WARNING:Xst:2211 - "/home/svenand/root/projects/ETC/xps/hdl/ETC_system.vhd" line 2217: Instantiating black box module <IOBUF>.

Xst:387 - The KEEP property attached to the net <microblaze_0/microblaze_0/Performance.Decode_I/of_PipeRun_Prefetch> may hinder timing optimization.
   You may achieve better results by removing this property

Generate Bitstream

Next step is to generate a new bitstream Hardware->Generate Bitstream. The bitstream generation generates a number of warnings but finish successfully.

WARNING:NgdBuild:440 - FF primitive
   'ddr_sdram_64mx32/ddr_sdram_64mx32/DDR_CTRL_I/WO_ECC.RDDATA_PATH_I/V2_ASYNCH_
   FIFO_I/BU520' has unconnected output pin
WARNING:NgdBuild:478 - clock net debug_module/bscan_drck1 with clock driver
   debug_module/debug_module/BUFG_DRCK1 drives no clock pins

WARNING:PhysDesignRules:372 - Gated clock. Clock net
   DCM_AUTOCALIBRATION_dcm_0/dcm_0/Using_DCM_ADV.DCM_ADV_INST/dcm_0/dcm_0/Using_
   DCM_ADV.DCM_ADV_INST/cd/CLK<1> is sourced by a combinatorial pin. This is not
   good design practice. Use the CE pin to control the loading of data into the
   flip-flop.

Can someone explain the meaning of these warnings to me.

Top Next Previous

Posted at 10:25 am by svenand
Comments (7) Permalink

Running demonstration software applications

To understand the process of running software applications in our embedded system we will start by reading the ML40x EDK Processor Reference Design user guide (Chapter 3. EDK Tutorial and Demonstrations).

ML403 Reference Systems on the CD

The ML403 development kit comes with three reference systems on the Development Kit Reference CD.

ML403 Embedded Processor Reference System (MicroBlaze-based)
ML403 Embedded Processor Reference System (PoerPC 405-based)
ML403 DCM Phase Shift Reference System (MicroBlaze-based)

Here is the content of the CD. Read the Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition for more information.

Top Next Previous

Posted at 02:19 pm by svenand
Make a comment Permalink

Hardware setup

Before we start running application programs. Let's take a look at our hardware setup.

Apple MacBook Intel Core 2 Duo, Mac OS X 10.4.9. VMware Fusion virtual machine with Ubuntu 7.04 installed.
Apple PowerBook G4 setup as a VT100 terminal emulator. The screen program emulates the HyperTerminal program. We can use any terminal we have available. We just happened to have a PowerBook lying around doing nothing.
Apple CInema Display 23", the main display where ISE and EDK windows are displayed.
Xilinx Platform Cable USB used to communicate with the ML403 evaluation board.
Keyspan USB to Serial converter for connecting to the VT100 terminal.
Xilinx ML403 evaluation board.

Software setup

Read the EDK Concept, Tools and Techniques guide to find out more about the software flow.

(system.bit should be download.bit)
(Courtesy of Xilinx)
Download and execute a simple program

We will use the memory test program TestApp_Memory.c as our first simple example to see if the hardware and software will function on our board.

Start the Xilinx Platform Studio

==> xps &

Download the bitstream

The file system.bit, created after hardware generation (completion of Xflow), is an uninitialized bitstream and does not include the ELF file. It is only when we execute the command to download or update the bitstream that the system.bit and ELF files merge into download.bit.

When we select Device Configuration > Download Bitstream, XPS downloads the bitstream (download.bit file) onto the target board using iMPACT in batch mode. XPS uses the file etc/download.cmd for downloading the bitstream. Because XPS tools are makefile based, the download button calls on the makefile and executes the steps necessary to create the bitstream with the Executable Linked Format (ELF) file populated within the bitstream.

Get program size

To ensure that the compiled TestApp_Memory code fits into the BRAM we will use the command Software->Get Program Size.

At Local date and time: Mon Jun 4 19:46:49 2007
mb-size /home/svenand/root/projects/ETC/xps/TestApp_Memory/executable.elf started...
text data bss dec hex filename
3944 332 2064 6340 18c4 /home/svenand/root/projects/ETC/xps/TestApp_Memory/executable.elf

Done!

Running the program

After we downloaded the bitstream the included program will start executing and display the result in the VT100 terminal.

The DDR SDRAM test program TestApp_Memory executes and it passes. We have reach one more milestone.

Top Next Previous

Posted at 11:10 am by svenand
Make a comment Permalink

Power calculations

Xilinx provides a number of spreadsheet- and web-based power estimation tools, power analyzers, and power-related documentation to meet our power solutions needs.

XPower

XPower is a power-analysis and detailed power estimation software available for programmable logic design. Included in all configurations of ISE™, XPower allows you to analyze total device power, power per-net, routed, partially routed or unrouted designs. XPower provides these capabilites through a comprehensive graphical user interface (GUI), or via command-line driven batch-mode. XPower also reads HDL simulation data to quickly set estimation stimulus, reducing setup time.

Let's try XPower.

==> export DISPLAY=0:
==> xpower &

We will launch the design wizard.

Set voltage sources.

Set frequences for all clocks, feedback signals and inputs.

Set capacitive loads for outputs.

Set DC loads for outputs.

XPower power calculation

We will add more data into XPower at a later stage when we know more about our design.

Low power consumption

Meeting our power budget is essential for attaining system performance and cost goals. Low power enables higher clock frequency, higher reliability, better noise margins, and reduced capital and operational costs.

Top Next Previous

Posted at 04:32 pm by svenand
Make a comment Permalink

Pin assignment closure process

Closing on a pin assignment that will meet requirements from both the PCB and FPGA environments is becoming more challenging. On one side of the interface, ever-increasing FPGA performance, density, and I/O count are placing tighter board constraints on the layout of the signal to and from the FPGA. On the other side, timing, congestion, and signal integrity of ever-faster signals on the PCB are placing constraints on FPGA pin assignment. Here is an article by Philippe Garrault from Xilinx describing the pin assignment closure process.

(Courtesy of Xilinx)
Tools to help you in pin assignment closure

PACE Pin and Area Constraint Editor

ISE includes PACE (Pinout and Area Constraints Editor), a powerful, yet fast and easy way to map design pins to your device, and floorplan logic areas. Drag-and-drop pins onto a graphical display of the device, group pins logically by color-coding for easy recognition, specify I/O standards and banks, assign and place differential I/Os, and much more. As devices grow ever larger, PACE brings a new level of ease to the difficult task of assigning design pins.

Running PACE

Let's start the PACE program.

==> pace &

/home/svenand/cad/xilinx91i/bin/lin/_pace: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory

To fix this problem we have to load the following Ubuntu packages:
libmotif3
libmotif-dev

==> pace &

Wind/U X-toolkit Error: wuDisplay: Can't open display

We have to change the DISPLAY variable from :0.0 to :0

==> export DISPLAY=:0
==> pace &

We specify our constraints file ETC_system.ucf as the input file to PACE and click OK.

PACE allows you to edit both location and area constraints, define logic areas graphically, and display I/Os on the periphery for connectivity checking. PACE allows area mapping by examining the defined HDL hierarchy and checks logic areas against expected gate size, making area definitions quick, accurate, and easy. Pins can be assigned using PACE before HDL coding has even started, and then write the HDL starting templates for you to edit. Pin information can be exported or imported to PCB layout editors through standard CSV files, greatly simplifying the design planning stage.

PACE contains built-in design rule checks like Simultaneous Switching Outputs to help predict ground bounce problems, unique displays like Package Flight Time allow you to see I/O to package lead delays for super-accurate timing.

Topi the Top Code Generator

Ever heard of table driven design. That is exactly what Topi is all about. When designing an FPGA with more than 1000 signal pins you need an exact and precise way of adding all the signal names. Topi will help you generate the top testbench, the top instantiation and the FPGA pin layout, all in the same tool.

Topi Setup

Using Topi to modify the Xilinx user constraints file

Let's start Topi.
==> topi &

We open the Setup->Pin Table window and select the Xilinx CSV table format.

Let's load the Xilinx CSV file into the Topi Spreadsheet Editor.

Here is the result.

'
The next step is to import the pin layout information into the Topi Pin Layout Editor. From the Load menu we select Pin Names (Match Package Balls).

In the pin layout editor we can easily change the pin placement by editing each indivudual signal name or by moving pins around using the move function. When we are satisfied with the result we can save the information in a Xilinx user constraints file (ucf).

Xilinx Floorplanner

Xilinx Floorplanner is a graphical placement tool that provides "drag and drop" control over design placement within an FPGA. Floorplanning is particularly useful on structured designs and data path logic. With the Xilinx Floorplanner, designers can see where to place logic for optimal results, placing data paths exactly at the desired location on the die.

The Xilinx Floorplanner enables designers to plan a design prior to or after using Place-and-Route (PAR) software. Invoking Floorplanner after a design has been placed and routed allows designers to view and possibly improve the results of the automatic implementation. In an iterative floorplan design flow, designers floorplan and place and route interactively.

When we started the PACE program we were told it will be replaced by the Floorplanner program. Why not give it a try.

==> floorplanner &

We enter the name of the ngd file and all the other files are found automatically. Click OK.

Viewing pin placement

If we select view Package Pins from the View menu we get the following display.

Xilinx PlanAhead

Here is an article about using PlanAhead Design and Analysis Tool.

Top Next Previous

Posted at 09:52 am by svenand
Comments (2) Permalink

Using the iMPACT configuration tool

After we have connected the USB JTAG programming cable and started iMPACT it will detect the JTAG chain on the ML403 evaluation board and display it in the boundary scan window.

The FPGA, Platform Flash memory, and CPLD can be configured through the JTAG port. The JTAG chain of the board is illustrated in this figure.

(Courtesy of Xilinx)
Boundary -Scan and JTAG configuration

Virtex-4 devices support the new IEEE 1532 standard for In-System Configuration (ISC), based on the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture is commonly referred to as JTAG. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This standard provides a means to ensure the integrity of individual components and the interconnections between them at the board level. With multi-layer PC boards becoming increasingly dense and more sophisticated surface mounting techniques in use, Boundary- Scan testing is becoming widely used as an important debugging standard.

IEEE standard 1149.1 (JTAG)

The Virtex-4 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the instruction register, the instruction decoder, the Boundary-Scan register, and the bypass register. The Virtex-4 family also supports a 32-bit identification register and a configuration register in full compliance with the standard.

                                                                                                                               (Courtesy of Xilinx)
The identification register

Virtex devices have a 32-bit identification register called the IDCODE register. The IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being addressed. This register allows easy identification of the part being tested or programmed by Boundary-Scan, and it can be shifted out for examination by using the IDCODE instruction.

Read IDCODE

Select one of the devices displayed in the Boundary Scan window and and double-click the Get Device ID entry in the Operations window. The result is displayed in the Output window.

// *** BATCH CMD : ReadIdcode -p 3
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'3': IDCODE is '00100001111001011000000010010011'
'3': IDCODE is '21e58093' (in hex).
'3': : Manufacturer's ID =Xilinx xc4vfx12, Version : 2

Read the FPGA status register

Select the Virtex-4 device in the Boundary Scan window and double-click the Read Status Register entry in the Operations window, The result is displayed in the Output window.

// *** BATCH CMD : ReadStatusRegister -p 3
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'3': Reading status register contents...
CRC error                                        :         0
Decryptor security set                           :         0
DCM locked                                       :         1
DCI matched                                      :         1
End of startup signal from Startup block         :         1
status of GTS_CFG_B                              :         1
status of GWE                                    :         1
status of GHIGH                                  :         1
value of MODE pin M0                             :         1
value of MODE pin M1                                     :         1
Value of MODE pin M2                             :         1
Internal signal indicates when housecleaning is completed:         1
Value driver in from INIT pad                    :         1
Internal signal indicates that chip is configured        :         1
Value of DONE pin                                        :         1
Indicates when ID value written does not match chip ID   :         0
Decryptor error Signal                           :         0
System Monitor Over-Temperature Alarm                    :         0

Device configuration

Configuring and programming are often used interchangeably. However, there is a distinction between these two terms. Configuration refers to the process of loading design-specific data into one or more volatile FPGAs using an external data source such as a PROM. Programming refers to the process of loading design-specific data into one or more non-volatile PROMs or CPLD devices. Configuring or programming a device defines the functional operations of the device. For simplification, we refer both configuring and programming as the device configuration. For general configuration guidelines, see XAPP501 Application Note.

Using Xilinx Platform Studio

Now when we are confident about our usb cable connection we are ready for the final step, downloading the bitstream to the FPGA device. We will start Xilinx Platform Studio (xps) to help us do the job.

==> cd $ETC_PROJECT
==> xps

To start the bitstream download select Device Configuration->Download Bitstream. The result is displayed in the output window. It says Programmed successfully. Huzzah!

Top Next Previous

Posted at 03:47 pm by svenand
Make a comment Permalink

Parallels Desktop has not proven to be the perfect solution for running Linux on my MacBook as I thought from the beginning. I have the same experience as described here, plus I was never able to mount an usb stick. It seems to me that Parallels has concentrated on getting the Windows application to run smoothly and left us Linux users out in the cold. What to do? Let's try VMware Fusion instead.

About VMware

VMware is the leader in virtual infrastructure technology. Until just recently they didn't have a solution for us Mac users but when Apple moved to Intel X86 processors that changed everything.

VMware Fusion for Mac

VMware Fusion enables you to run any PC application on your Intel-based Mac. Using VMware Fusion, you can run Windows, Linux, Solaris and other PC operating systems right alongside Mac OS X, safely and easily, without the need to reboot your computer.

Download and install VMware Fusion 1.0

The first official release of VMware Fusion is now available. We will download build 51348 from here and install it on our MacBook.

Download Ubuntu 7.04

Here is the download page for Ubuntu 7.04.

Creating a virtual machine using VMware Fusion

Start VMware Fusion.

Click the New button.

Click Continue

We choose the operating system and click Continue.

Select name and location.

Specify disk size.

Select the disc image file and click Finish. The Ubuntu installation will start.

We go through a normal Ubuntu installation and answer a few questions before the installation starts. It takes less than 20 minutes to finish.

When the installation has finished we will shut down the system and before we reboot we will make sure that we have the CD ROM set to cdrom0.

Now we are ready to boot Ubuntu.

Ubuntu login screen.

VMware Tools

When VMware Fusion really starts to shine is after we have installed the VMware tools package. To install the package the Linux OS must be up and running and we have to be logged in. We also have to make sure we have the gcc compiler installed. To install gcc use the following command: sudo apt-get install build-essential

VMware Tools installation

Follow these steps to install the VMware Tools package.

Select from the VMware menu: Virtual Machine->Install VMware Tools
The following files will be downloaded

You must use the tar installer to install VMware Tools in Ubuntu Linux.

Copy VMwareTools-e.x.p-51348.tar.gz to a temporary directory
Open a terminal window
Unpack the file using the command tar zxfv VMwareTools-e.x.p-51348.tar.gz
Move to the directory vmware-tools-distrib: cd vmware-tools-distrib
Execute the perl script as root: sudo ./vmware-install.pl

Printout from installation

svenand@svenand-desktop:~/temp/vmware-tools-distrib$ sudo ./vmware-install.pl

Installing VMware Tools. This may take from several minutes to over an hour
depending upon its size.

In which directory do you want to install the binary files?
[/usr/bin]

What is the directory that contains the init directories (rc0.d/ to rc6.d/)?
[/etc]

What is the directory that contains the init scripts?
[/etc/init.d]

In which directory do you want to install the daemon files?
[/usr/sbin]

In which directory do you want to install the library files?
[/usr/lib/vmware-tools]

The path "/usr/lib/vmware-tools" does not exist currently. This program is
going to create it, including needed parent directories. Is this what you want?
[yes]

In which directory do you want to install the documentation files?
[/usr/share/doc/vmware-tools]
The path "/usr/share/doc/vmware-tools" does not exist currently. This program
is going to create it, including needed parent directories. Is this what you
want? [yes]

The installation of VMware Tools e.x.p build-51348 for Linux completed
successfully. You can decide to remove this software from your system at any
time by invoking the following command: "/usr/bin/vmware-uninstall-tools.pl".

Before running VMware Tools for the first time, you need to configure it by
invoking the following command: "/usr/bin/vmware-config-tools.pl". Do you want
this program to invoke the command for you now? [yes]

Stopping VMware Tools services in the virtual machine:
Guest operating system daemon: done
Trying to find a suitable vmmemctl module for your running kernel.

None of the pre-built vmmemctl modules for VMware Tools is suitable for your
running kernel. Do you want this program to try to build the vmmemctl module
for your system (you need to have a C compiler installed on your system)?
[no] yes

Using compiler "/usr/bin/gcc". Use environment variable CC to override.

What is the location of the directory of C header files that match your running
kernel? [/lib/modules/2.6.20-15-generic/build/include]

Extracting the sources of the vmmemctl module.

Building the vmmemctl module.

The vmemctl module will now be built

The configuration of VMware Tools e.x.p build-51348 for Linux for this running
kernel completed successfully.

You must restart your X session before any mouse or graphics changes take
effect.

You can now run VMware Tools by invoking the following command:
"/usr/bin/vmware-toolbox" during an X server session.

To use the vmxnet driver, restart networking using the following commands:
/etc/init.d/networking stop
rmmod pcnet32
rmmod vmxnet
depmod -a
modprobe vmxnet
/etc/init.d/networking start

If you wish to configure any experimental features, please run the following
command: "vmware-config-tools.pl --experimental".

Enjoy,

--the VMware team

After restarting our system we can start enjoying all the nice features of VMware Fusion. The network connection was disabled during VMware Tools installation but will be reconnected after a reboot of the system. Every time there is a Linux kernel update we have to rerun this process.

Comparing Parallels Desktop and VMware Fusion when running Ubuntu Linux

Here is a comparison between Parallels Desktop 3.0 and VMware Fusion 1.0 and the winner is VMware Fusion. After Parallels release of Parallels tools for Linux Parallels Desktop now have almost the same features as VMware Fusion.

Feature	Parallels Desktop	VMware Fusion
Drag and drop files between Mac OS X and the virtual machine	No	Yes
Displaying progress bar during bootup and shutdown	No	Yes
Copying and pasting text between Mac OS X and the virtual machine	No	Yes
Moving the cursor between Mac OS X and the virtual machine	Yes	Yes
Support for Airport Wireless network	Yes	Yes
Mounting usb devices	Yes (Not working in Ubuntu)	Yes
Coherence mode	No	No
Taking snapshots	Yes	Yes
Snapshot manager	Yes	No
Resizing the virtual machine window	Yes	Yes
Price	$79.99	$59.99

Useful tips

If you are using a bluetooth keyboard and/or mouse make sure you have disconnected the Apple Bluetooth Adapter in the VMware Settings otherwise you can not use the bluetooth keyboard or mouse.

File sharing between Ubuntu and Mac OS X

You can setup a shared folder in VMware Fusion or you can just drag and drop files.

The shared folder will show up in Ubuntu under: /mnt/hgfs/...

Network connection

I am sharing the host's internet connection (NAT). I works fine for me.

Problem log

I will report all problems found in this problem log. There can be many causes to a problem and sometimes VMware is not to blame.

Slogan	Note	Release	Date	Fixed
Printing to an usb printer connected to an Airport Express	1	1.0b3	2007-05-21	Fixed in RC1
Unmounting a Western Digital usb disk	2	1.0b3	2007-05-21	This is an Ubuntu 7.04 problem.

Note 1. I can't see the usb printer connected to my Airport Express when trying to setup a new printer from the System->Administration->Printing setup window. See Customizing Ubuntu Linux for more information.

Running nmap shows the following ports and their usage:

==> nmap -P0 10.0.1.200

Starting Nmap 4.20 ( http://insecure.org ) at 2007-07-21 22:16 CEST
Interesting ports on 10.0.1.200:
Not shown: 1693 filtered ports
PORT STATE SERVICE
53/tcp open domain
5000/tcp open UPnP
9100/tcp open jetdirect
10000/tcp open snet-sensor-mgmt

Nmap finished: 1 IP address (1 host up) scanned in 33.455 seconds

Note 2. When trying to unmount (eject) my Western Digital usb disk I get the follwing message and the disk will not unmount. The disk is formatted as a MacOS Extended disk.

We can use the command lsusb to list all usb device that are connected.

==> lsusb
Bus 002 Device 003: ID 1058:0901 Western Digital Technologies, Inc.
Bus 002 Device 002: ID 05ac:8501 Apple Computer, Inc.
Bus 002 Device 001: ID 0000:0000
Bus 001 Device 001: ID 0000:0000

We can also look at the end of the /var/log/messages file using the command dmesg.

==> dmesg | grep usb
[16586.068162] usbcore: registered new interface driver usbfs
[16586.068179] usbcore: registered new interface driver hub
[16586.068203] usbcore: registered new device driver usb
[16586.069444] usb usb1: configuration #1 chosen from 1 choice
[16587.619562] usb usb2: configuration #1 chosen from 1 choice
[16587.938243] usb 2-1: new high speed USB device using ehci_hcd and address 2
[16588.075327] usb 2-1: configuration #1 chosen from 1 choice
[20057.730075] usb 2-2: new high speed USB device using ehci_hcd and address 3
[20057.881311] usb 2-2: configuration #1 chosen from 1 choice
[20058.015269] usbcore: registered new interface driver libusual
[20058.097910] usbcore: registered new interface driver usb-storage
[20058.098520] usb-storage: device found at 3
[20058.098523] usb-storage: waiting for device to settle before scanning
[20062.516934] usb-storage: device scan complete

Manually unmounting

The usb-disk can be unmounted using the following command: sudo umount "/media/My Book"

Discussion forums

Here you can discuss everything around VMware Fusion. You must register as a user before posting.

Frequently asked questions

The FAQ is found here.

More information

YouTube Videos

Top

Posted at 08:31 pm by svenand
Comments (17) Permalink

Implementing the hardware platform

After more than 5 month of hard work we have reached the point of no return, it is time to program the FPGA. After completing hardware platform design entry, we are ready to:

Specify design constraints
Generate the bitstream (BIT) file that represents the completed hardware platform

User Constraints File

To create the BIT file for downloading and implement the design, we must first set up our User Constraints File (UCF). As in ISE, an FPGA design implemented using EDK requires a UCF. Primarily, the UCF specifies pinouts and timing constraints. It can also control a variety of other hardware implementation features, such as the configurable electrical characteristics of our FPGA I/O signals.

Setting up our User Constraints File

To access the UCF file for our XPS project:

Click the Project tab in the Project Information Area of the main window and look for the UCF file under the Project Files heading.
Double-click the UCF file to open it in the System Assembly panel.

The UCF has the same base filename as the Xilinx Microprocessor Project (XMP) file, and it must reside in the data subfolder of our project directory.

Specifying Pin Constraints

We must often provide a Location (LOC) constraint to define the FPGA pin location for each external port. To view the list of the external ports, do the following:

In the XPS main window, click the System Assembly tab.
Select the Ports filter.

LOC constraints take the following form:

NET RS232_RX_pin LOC=U4;

Specifying Timing Constraints

For most embedded processor designs, we need only specify the input (reference) clock period to ensure that your system meets performance requirements. In some cases, our design might contain off-chip peripherals, such as memory controllers, that have particular input and output timing requirements. We should also declare Timing IGnore (TIG) constraints on signals that are not timing critical to allow better place and route tools to optimize other timing paths. The following are typical of the basic timing constraints we must provide in our UCF file:

Net sys_clk_pin PERIOD = 20000 ps;
Net sys_rst_pin TIG;

The implementation directory

The result from netlist generation is stored in the implemenation directory. All the NGC files from the synthesis runs are collected here. The bitstream generation program will include all the netlist files to generate the final bitstream. We have to make sure all netlist files can be found in the implementation directory before we start the bitstream generation. When we generated the ETC_DUAL_PORT_1024x32 memory using Coregen (see part 4) the netlist file ETC_DUAL_PORT_1024x32.edn was created. This file will also be copied to the implementation directory.

Start bitstream generation

From the XPS Hardware menu we choose Generate Bitstream to start the bitstream generation.

Here is a printout from the startup of the program.

At Local date and time: Fri May 25 16:18:25 2007
make -f ETC_system.make bits started...
*********************************************

Running Xilinx Implementation tools..

*********************************************

xflow -wd implementation -p xc4vfx12ff668-10 -implement xflow.opt ETC_system.ngc

Release 9.1.02i - Xflow J.30

Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

xflow -wd implementation -p xc4vfx12ff668-10 -implement xflow.opt ETC_system.ngc

Using Flow File: /home/svenand/root/projects/ETC/xps/implementation/fpga.flw

Using Option File(s):

/home/svenand/root/projects/ETC/xps/implementation/xflow.opt

Creating Script File ...

#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm ETC_system.bmm
"/home/svenand/root/projects/ETC/xps/implementation/ETC_system.ngc" -uc
ETC_system.ucf ETC_system.ngd

#----------------------------------------------#

Release 9.1.02i - ngdbuild J.33
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Command Line: ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm ETC_system.bmm
/home/svenand/root/projects/ETC/xps/implementation/ETC_system.ngc -uc
ETC_system.ucf ETC_system.ngd

Bitstream generation flow

The Bitstream generation uses the XFLOW program to setup and run the complete program flow. XFLOW is a command line program that automates Xilinx synthesis, implementation, and simulation flows. XFLOW reads a design file as input as well as a flow file and an option file. Xilinx provides a default set of flow files that automate which Xilinx programs are run to achieve a specific design flow. For example, a flow file can specify that NGDBuild, MAP, PAR, and TRACE are run to achieve an implementation flow for an FPGA. Here is the xflow log file from our bitstream generation run.
For more information about XFLOW read the Xilinx Development System Reference Guide.

(Courtesy of Xilinx)

The NGC files are processed, along with the system constraints, through Xilinx tools (NGDBuild, MAP, PAR, and TRACE) when XPS invokes the XFlow command-line program.

Script file to run XFlow

Here is the script file that are generated when we start the bitstream generation.

#!/bin/csh -f
###########################################
# Script file to run the flow
#
###########################################
#
# Command line for ngdbuild
#
ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm ETC_system.bmm "/home/svenand/root/projects/ETC/xps/implementation/ETC_system.ngc" -uc ETC_system.ucf ETC_system.ngd

#
# Command line for map
#
map -o ETC_system_map.ncd -pr b ETC_system.ngd ETC_system.pcf

#
# Command line for par
#
par -w -ol high ETC_system_map.ncd ETC_system.ncd ETC_system.pcf

#
# Command line for post_par_trce
#
trce -e 3 -xml ETC_system.twx ETC_system.ncd ETC_system.pcf

Bitstream generation result

During the bitstream generation a number of files have been generated.

File Name	Description	Readable
ETC_system.bgn	Bitgen log file	Yes
ETC_system.bit	Bitstream download file	No
ETC_system.bld	Ngdbuild log file	Yes
ETC_system.bmm	Address map bram	Yes
ETC_system.drc	Drc log file	Yes
ETC_system.ncd	Mapping output file	No
ETC_system.ngc	XST synthesis output file	No
ETC_system.ngd	Xilinx native generic database format	No
ETC_system.pad	Pin definition file (spreadsheet import file)	Yes
ETC_system.par	Placer report file	Yes
ETC_system.pcf	Map report file	Yes
ETC_system.twr	Trace report file (timing constraints)	Yes
ETC_system.twx	Trace XML file	Yes
ETC_system.ucf	User constraints file (copied from data dir)	Yes
ETC_system.unroutes	Displays unrouted nets	Yes
ETC_system_pad.cvs	Pin definition file (spreadsheet import file)	Yes
ETC_system_pad.txt	Pin definition file (text format)	Yes
ETC_system_map.mrp	Mapping report file	Yes

Configuration of the FPGA

Virtex-4 devices are configured by loading application-specific configuration dataï¿½the bitstreamï¿½into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:

Master-serial configuration mode
Slave-serial configuration mode
Master SelectMAP (parallel) configuration mode
Slave SelectMAP (parallel) configuration mode
In addition, the bitstream can be loaded through the JTAG interface

Read more in the Virtex-4 Configuration Guide.

Using the Platform Cable USB

Platform Cable USB is a high-performance download cable attaching to user hardware for the purpose of programming or configuring any of the following Xilinx devices:

ISP Configuration PROMs
CPLDs
FPGAs

Platform Cable USB attaches to the USB port on a desktop or laptop PC with an off-the-shelf Hi-Speed USB A-B cable. It derives all operating power from the hub port controller. No external power supply is required. A sustained slave-serial FPGA configuration transfer rate of 24 Mb/s is possible in a Hi-Speed USB environment. Actual transfer rates can vary if bandwidth of the hub is being shared with other USB peripheral devices. Platform Cable USB attaches to target systems using a 14-conductor ribbon cable designed for high-bandwidth data transfers.

ML403 evaluation board

(Courtesy of Xilinx)

Read the ML403 user guide to find out what the numbers stand for. Here are some known issues with this board. Here is all the documentation about the ML403 board.

ML403 block diagram

(Courtesy of Xilinx)
ML403 blocks and busses

(Courtesy of Xilinx)
Installing cable drivers

In the Xilinx answers database we find answer #22648: 9.1i iMPACT - Installing Xilinx cable drivers on Linux operating system/kernel version 2.6. We will install the drivers in our Ubuntu Linux 7.04 system. To find out which version of the kernel we have installed we use the command:

==> uname -a
Linux svenand-desktop 2.6.20-15-generic #2 SMP Sun Apr 15 07:36:31 UTC 2007 i686 GNU/Linux

When I was out on the web looking for information about installing the cable drivers I came across the following link: http://www.rmdir.de/~michael/xilinx/

XILINX JTAG tools on Linux without proprietary kernel modules

When using Xilinx JTAG software like Impact, Chipscope and XMD on Linux, the proprietary kernel module windrvr from Jungo is needed to access the parallel- or usb-cable. As this module does not work with current linux kernel versions (> 2.6.18) a library was developed, which emulates the module in userspace and allows the tools to access the JTAG cable without the need for a proprietary kernel module.

Let's give it a try. To me it sounds like a much better solution than the one Xilinx provides. We will follow the instructions found in this README file.

Install the libusb-dev package using the command: sudo apt-get install libusb-dev
Download usb-driver-HEAD.tar.gz and save the file in a temp directory
Goto the temp directory cd .../temp
Unpack the file using the command: tar zxvf usb-driver-HEAD.tar.gz
Goto the usb-driver directory: cd usb-driver
Install the package build-essential (contains make) sudo apg-get install build-essential
Build the libusb-driver.so library file using the command: make
Copy libusb-driver.so to the /usr/lib directory: sudo cp libusb-driver.so /usr/lib/.
To use this library we have to preload it before starting impact:
export LD_PRELOAD=/usr/lib/libusb-driver.so (sh and bash)
setenv LD_PRELOAD /usr/lib/libusb-driver.so (csh and tcsh)

Setting up the USB cable

To use the device as an ordinary user, put the following line in the file /etc/udev/rules.d/50-xilinx-usb-pav.rules (or use any file name you like) ACTION=="add",BUS=="usb",SYSFS{idVendor}=="03fd",MODE="666"
sudo gedit /etc/udev/rules.d/50-xilinx-usb-pav.rules and add the line above
Restart udev: sudo /etc/init.d/udev restart
Execute the command: lsusb
Bus 002 Device 002: ID 03fd:000f Xilinx, Inc.
Bus 002 Device 001: ID 0000:0000
Bus 001 Device 001: ID 0000:0000
If your cable does not have the ID 03fd:0008 in the output of lsusb the initial firmware has not been loaded (loading it changes the product-ID from another value to 0008
To load the firmware follow these steps:
If you have no /etc/udev/rules.d/xusbdfwu.rules file, copy it from /ISE_install_dir/bin/lin/xusbdfwu.rules
Install the package fxload using the command: sudo apt-get install fxload
Copy the file /ISE_install_dir/bin/lin/xusbdfwu.hex to /usr/share/xusbdfwu.hex
Restart udev: sudo /etc/init.d/udev restart
Execute the command: lsusb
Bus 002 Device 001: ID 0000:0000
Bus 001 Device 003: ID 0e0f:0002
Bus 001 Device 002: ID 03fd:0008 Xilinx, Inc.
Bus 001 Device 001: ID 0000:0000
The ID is 03fd:0008
Replug the usb cable
Make sure the green status light is on. The USB cable interface must be connected during VMware Fusion Ubuntu bootup. WMware will detect the USB cable interface and automatically connect it.

Permission denied. Change owner

Can't open /dev/parport0: Permission denied

If this message is displayed in the terminal when starting iMPACT, we have to change the owner of this file from root to the current user. Like this: sudo chown svenand /dev/parport0. This has to repeated every time after we have booted the Linux OS.

Unlocking the cable interface

Use the following commands to unlock the cable interface if needed:

==> impact -batch
> setMode -bscan
> cleancablelock
> quit

iMPACT FPGA configuration tool

iMPACT allows designers to easily perform device configuration and programming either as a batch operation or through a convenient graphical user interface. iMPACT is a full featured software tool used for configuration and programming of all Xilinx PLDs (FPGAs and CPLDs) and PROMs. iMPACT features a series of design wizards that easily guide the user through each step of the configuration process.

Starting iMPACT

==> impact & (xilinx_install_dir/bin/lin/impact)

We will create a new project in iMPACT and give it a name ETC_system.icf

We will use Boundary-Scan (JTAG) to configure the FPGA.

When we click Finish the program connects to our evaluation board. Here is the printout from iMPACT:

Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /home/svenand/cad/xilinx91i/bin/lin/xusbdfwu.hex = 1025(dec), 0x0401.
File version of /usr/share/xusbdfwu.hex = 1025(dec), 0x0401.
libusb-driver.so version: 2007-05-27 00:37:02.
Cable PID = 0008.
Max current requested during enumeration is 280 mA.
Cable Type = 3, Revision = 0.
Cable Type = 0x0605.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1025.
CPLD file version = 0012h.
CPLD version = 0006h.
WARNING:iMPACT:2356 - Platform Cable USB firmware must be updated. This operation may take up to 10 minutes on a USB 2.0 port or up to 30 minutes on a USB 1.1 port.
Please do not stop the process or disconnect the cable prior to completion. The cable
STATUS LED will be RED for the duration of the update process.

Updating the cable firmware...
PROGRESS_START - Starting Operation.
Firmware update completed successfully.
PROGRESS_END - End Operation.
Elapsed time = 1943 sec.
Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify
PROGRESS_START - Starting Operation.
Identifying chain contents ....'1': : Manufacturer's ID =Xilinx xc95144xl, Version : 5
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/xc9500xl/data/xc95144xl.bsd...
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'2': : Manufacturer's ID =Xilinx xc4vfx12, Version : 2
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/virtex4/data/xc4vfx12.bsd...
INFO:iMPACT:501 - '1': Added Device xc4vfx12 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'3': : Manufacturer's ID =Xilinx xcf32p, Version : 15
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/xcfp/data/xcf32p.bsd...
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'4': : Manufacturer's ID =Xilinx xccace, Version : 0
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time = 4 sec.
// *** BATCH CMD : identifyMPM

Congratulations! We have a working cable connection to our evaluation board. Thanks Michael, you saved our day.

Top Next Previous

Posted at 11:34 am by svenand
Comments (4) Permalink

System simulations

System simulation is an effective method for verifying that software drivers are compatible with the hardware. Using a simulator for that purpose offers several advantages over GDB. For example, no physical link to the hardware is required and internal system signals may be easily monitored. In addition, the hardware does not need to be run through the implementation tools to run a system simulation, allowing the quick analysis of the effects of changes to the code or the generics. The flow presented here can easily be modified to support structural and timing simulation.

The EDK System Simulation guide presents Xilinx idea about system simulations. They use Modelsim and the setup is to complicated for my taste. We will stay with NCSIM and the simulation strategy we formulated in part 23. We will specify testcases to verify all interfaces in our system. Each testcase will include a c-program to access the peripheral and it's registers. Here is our system.

DDR SDRAM controller

The DDR SDRAM controller (opb_ddr) connects the DDR SDRAM to the OPB. The DDR SDRAM is a Micron MT46V16M16P-6T.

Features

OPB interface
Performs device initialization sequence upon power-up and reset conditions for ~200uS. Provides a parameter to adjust this time for simulation purposes only.
Performs auto-refresh cycles
Supports CAS latencies of 2 or 3 set by a design parameter
Supports 16, 32 and 64 bits DDR data widths set by a designparameter
Supports indeterminate burst length
Provides big-endian connections to memory devices
Supports multiple (up to 4) DDR memory banks.

DDR SDRAM Initialization

Prior to normal operation, DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures, other than those specified, may result in undefined operation. To ensure device operation, the DRAM must be initialized as described in the following steps:

Simultaneously apply power to VDD and VDDQ
Apply VREF and then VTT power. VTT must be applied after VDDQ to avoid device latchup, which may cause permanent damage to the device. Exept for CKE, inputs are not recognized as valid until after VREF is applied.
Assert and hold CKE at a LVCMOS logic LOW. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access).
Provide stable clock signals.
Wait at least 200μs.
Bring CKE HIGH, and provide at least one NOP or DESELECT command. At this point, the CKE input changes from a LVCMOS input to a SSTL_2 input only and will remain a SSTL_2 input unless a power cycle occurs.
For more information about the initialization see the DDR SDRAM data sheet.

Setting the initialization time

The OPB DDR block will insert a 200us delay before it asserts DDR_init_done (see waveform plot) to allow time for DDR SDRAM initialization to happen.

For simulation purpose only we can change that time by editing the wrapper file ddr_sdram_64mx32_wrapper.vhd.
Look for the line: C_SIM_INIT_TIME_PS => 200000000 and change it to C_SIM_INIT_TIME_PS => 20000 (20ns).

C program

This program will write and read three addresses in the DDR SDRAM.

int main()

#define poke(addr,val)     (*(unsigned char*) (addr) = (val))
#define pokew(addr,val)    (*(unsigned*) (addr) = (val))
#define peek(addr)         (*(unsigned char*) (addr))
#define peekw(addr)        (*(unsigned*) (addr))

{

   unsigned char byte_of_data;
   unsigned      word_of_data;

   pokew(0x44000000,0xffffffff);
   pokew(0x46000004,0xaaaaaaaa);
   pokew(0x47fffffc,0x55555555);

   word_of_data = peekw(0x44000000);
   word_of_data = peekw(0x46000004);
   word_of_data = peekw(0x47fffffc);

    return 0;
}

Assembly code

   0:    3021fff0     addik   r1, r1, -16
   4:    fa61000c     swi     r19, r1, 12
   8:    12610000     addk    r19, r1, r0
   c:    3060ffff     addik   r3, r0, -1
10:    b0004400     imm     17408
14:    f8600000     swi     r3, r0, 0
18:    b000aaaa     imm     -21846
1c:    3060aaaa     addik   r3, r0, -21846
20:    b0004600     imm     17920
24:    f8600004     swi   r3, r0, 4
28:    b0005555     imm     21845
2c:    30605555     addik   r3, r0, 21845
30:    b00047ff     imm     18431
34:    f860fffc     swi     r3, r0, -4
38:    b0004400     imm     17408
3c:    e8600000     lwi     r3, r0, 0
40:    f8730008     swi   r3, r19, 8
44:    b0004600     imm     17920
48:    e8600004     lwi     r3, r0, 4
4c:    f8730008     swi     r3, r19, 8
50:    b00047ff     imm     18431
54:    e860fffc     lwi     r3, r0, -4
58:    f8730008     swi     r3, r19, 8
5c:    10600000     addk    r3, r0, r0
60:    10330000     addk    r1, r19, r0
64:    ea61000c     lwi     r19, r1, 12
68:    30210010     addik   r1, r1, 16
6c:    b60f0008     rtsd    r15, 8
70:    80000000     or      r0, r0, r0

Simulation result

LED displays and push buttons

The LED displays (LED_Positions and LEDs_4Bit) and the push buttons are connected to the general purpose input/outputs and through the OPB General Purpose Input/Output (GPIO) controller to the OPB bus.

Features

OPB v2.0 bus interface with byte-enable support
Configurable as single or dual GPIO channel(s)
Number of GPIO bits configurable from 1 to 32 bits
Each GPIO bit dynamically programmable as input or output
Can be configured as inputs-only on a per channel basis to reduce resource utilization
Ports for both 3-state and non 3-state connections
Independent reset values for each bit of all registers
Optional interrupt request generation

Address ranges

0x40020000-0x4002ffff LEDs_Positions
0x40040000-0x4004ffff LEDs_4Bit
0x40000000-0x4000ffff Push_Buttons_Position

OPB GPIO Registers

There are four internal registers in the OPB GPIO design as shown in the table. These registers are implemented in the GPIO_CORE interface module. The memory map of the OPB GPIO design is determined by setting the C_BASEADDR parameter. The internal registers of the OPB GPIO are at a fixed offset from the base address.

Register Name	Description	OPB Address	Access
GPIO_DATA	Channel 1 OPB GPIO Data Register	C_BASEADDR + 0x00	Read/Write
GPIO_TRI	Channel 1 OPB GPIO 3-state Register	C_BASEADDR + 0x04	Read/Write
GPIO2_DATA	Channel 2 OPB GPIO Data register	C_BASEADDR + 0x08	Read/Write
GPIO2_TRI	Channel 2 OPB GPIO 3-state Register	C_BASEADDR + 0x0C	Read/Write

C program

int main()

#define poke(addr,val)     (*(unsigned char*) (addr) = (val))
#define pokew(addr,val)    (*(unsigned*) (addr) = (val))
#define peek(addr)         (*(unsigned char*) (addr))
#define peekw(addr)        (*(unsigned*) (addr))

{

   unsigned char byte_of_data;
   unsigned      word_of_data;

// Write to LEDs
   pokew(0x40020000,0xffffffff);
   pokew(0x40020004,0x00000000);
   pokew(0x40020008,0x33333333);
   pokew(0x4002000c,0x00000000);
   pokew(0x40040000,0x55555555);
   pokew(0x40040004,0x00000000);
   pokew(0x40040008,0x11111111);
   pokew(0x4004000c,0x00000000);
// Read push buttons
   pokew(0x40000004,0xffffffff);
   word_of_data = peek(0x40000000);
   pokew(0x4000000c,0xffffffff);
   word_of_data = peek(0x40000008);

   return 0;

Assembly code

   0:    3021fff0     addik r1, r1, -16
   4:    fa61000c     swi    r19, r1, 12
   8:    12610000     addk   r19, r1, r0
   c:    3060ffff     addik r3, r0, -1
10:    b0004002     imm    16386
14:    f8600000     swi    r3, r0, 0
18:    b0004002     imm    16386
1c:    f8000004     swi    r0, r0, 4
20:    b0003333     imm    13107
24:    30603333     addik r3, r0, 13107
28:    b0004002     imm    16386
2c:    f8600008     swi    r3, r0, 8
30:    b0004002     imm    16386
34:    f800000c     swi    r0, r0, 12
38:    b0005555     imm    21845
3c:    30605555     addik r3, r0, 21845
40:    b0004004     imm    16388
44:    f8600000     swi    r3, r0, 0
48:    b0004004     imm    16388
4c:    f8000004     swi    r0, r0, 4
50:    b0001111     imm    4369
54:    30601111     addik r3, r0, 4369
58:    b0004004     imm    16388
5c:    f8600008     swi    r3, r0, 8
60:    b0004004     imm    16388
64:    f800000c     swi    r0, r0, 12
68:    3060ffff     addik r3, r0, -1
6c:    b0004000     imm    16384
70:    f8600004     swi    r3, r0, 4
74:    b0004000     imm    16384
78:    e8600000     lwi    r3, r0, 0
7c:    f8730008     swi    r3, r19, 8
80:    3060ffff     addik r3, r0, -1
84:    b0004000     imm    16384
88:    f860000c     swi    r3, r0, 12
8c:    b0004000     imm    16384
90:    e8600008     lwi    r3, r0, 8
94:    f8730008     swi    r3, r19, 8
98:    10600000     addk   r3, r0, r0
9c:    10330000     addk   r1, r19, r0
a0:    ea61000c     lwi    r19, r1, 12
a4:    30210010     addik r1, r1, 16
a8:    b60f0008     rtsd   r15, 8
ac:    80000000     or     r0, r0, r0

Simulation result

Embedded Test Controller

The Embedded Test Controller (ETC) is a custom IP that implements a 1149.1 complient JTAG tester. It can run JTAG test sequences on the board and/or the complete system during startup and normal operation.

ETC address map

Register/ Memory Name	Size	Access	Address
Control	32	Write	0x42a10000
Status	32	Read	0x42a10004
Execute	32	Write	0x42a10008
Debug	32	Read	0x42a1000c
Test program RAM	1Kx32	Write	0x42a08000
Test result RAM	1Kx32	Read	0x42a09000

C program

int main()

#define poke(addr,val)     (*(unsigned char*) (addr) = (val))
#define pokew(addr,val)    (*(unsigned*) (addr) = (val))
#define peek(addr)         (*(unsigned char*) (addr))
#define peekw(addr)        (*(unsigned*) (addr))

{

   unsigned char byte_of_data;
   unsigned      word_of_data;

// Write testprogram
   pokew(0x42a08000,0x800000f1);
   pokew(0x42a08004,0x80000000);
   pokew(0x42a08008,0x800000f2);
   pokew(0x42a0800c,0x8000000c);

// Write control register in ETC
// Enable TCK clock
   pokew(0x42a10000,0x000000a0);

// Read status register in ETC
   word_of_data = peekw(0x42a10004);
// Read debug register in ETC
   word_of_data = peekw(0x42a1000c);

// Start test program
   pokew(0x42a10008,0x00000001);

Simulation result

Debugging the On-chip Peripheral Bus

When I started to debug the ETC IP I quickly found out that my implementation and the Xilinx implementations of the OPB interface differed.

Specifications

Here is the IBM On-Chip Peripheral Bus Architecture Specification and here is the Xilinx implementation

MicroBlaze write cycle.

Let's take a closer look at the OPB. Here are two plots showing all signals in the Xilinx implemantation of the OPB interface.

Here are all the input signals to the mb_opb block.

Here are all the output signals from the mb_opb block.

OPB signal description

Signal	Description	Width	Used in ETC
OPB_ABus	Address bus	32	Yes
OPB_BE	Data byte enable	4	Yes
OPB_beAck	OPB byte enable acknowledge	1	No
OPB_beXfer	OPB byte enable transfer	1	No
OPB_busLock	OPB bus arbitration lock	1	No
OPB_Dbus	OPB Ddata bus	32	Yes
OPB_dwAck	OPB doubleword acknowledge	1	No
OPB_dwXfer	OPB doubleword transfer	1	No
OPB_errAck	OPB error acknowledge	1	Yes, always = 0
OPB_fwAck	OPB fullword acknowledge	1	Yes, always = 0
OPB_fwXfer	OPB fullword transfer	1	No
OPB_hwAck	OPB halfword acknowledge	1	No
OPB_hwXfer	OPB halfword transfer	1	No
OPB_MGrant	OPB master bus grant	2	No
OPB_MRequest	OPB Master bus request	2	No
OPB_pendReq	OPB pending master request	2	No
OPB_rdDbus	OPB read data bus	32	No
OPB_retry	OPB bus cycle retry	1	Yes, always = 0
OPB_RNW	OPB read not write (write=L)	1	Yes
OPB_Rst	OPB reset	1	Yes
OPB_select	OPB select	1	Yes
OP_seqAddr	OPB sequential address	1	No
OPB_timeout	OPB timeout error	1	No
OPB_toutSup	OPB timeout suppress	1	Yes, always = 0
OPB_wrDbus	OPB write data bus	32	No
OPB_xferAck	OPB transfer acknowledge	1	Yes

Final result

It took me a couple of days to sort out all issues around the ETC OPB interface. Here is what I found out. Right or wrong?

The read and write cycles can be two or more clock cycles long. The OPB interface can decide how long the read and write cycles will be by asserting the OPB_xferAck in the last clock cycle. I am using 3 clock cycles in the ETC OPB interface.
The fullword and halfword control signals are not implemented in the Xilinx version of OPB. Use the signal OPB_BE instead. OPB_BE = 4'b1111 enable all four bytes when reading and writing 32 bit words.
Always keep the read data bus low when no valid read cycle is taking place. Read data busses from all peripherals are or'ed together in the mb_opb block and only one peripheral at a time can drive the bus high. Important !!!
You don't have to implement the signals OPB_errAck, OPB_toutSup and OPB_retry. I have set them all low.

Here is my OPB interface to the ETC block. Comments and improvements are welcomed.

Top Next Previous

Posted at 08:55 pm by svenand
Comment (1) Permalink

HyperTerminal is a communications program bundled with multiple versions of the Microsoft Windows operating system. It is a tool used when connecting to other computers, bulletin board systems (BBSs), and a host of other Internet-related services.

HyperTerminal is designed to emulate various types of text terminal. It can be configured to make a connection through a modem or directly over a serial port. Various serial parameters are configurable such as:

HyperTerminal supports various terminal protocols such as VT100 (ANSI X3.64), as well as various forms of file transfer protocols such as ASCII, XMODEM and YMODEM.

The screen program

A good replacement for HyperTerminal in Mac OS X is the unix program /usr/bin/screen.

NAME
       screen - screen manager with VT100/ANSI terminal emulation

SYNOPSIS
       screen [ -options ] [ cmd [ args ] ]
       screen -r [[pid.]tty[.host]]
       screen -r sessionowner/[[pid.]tty[.host]]

DESCRIPTION
       Screen is a full-screen window manager that multiplexes a physical ter-
       minal between several processes (typically interactive shells).   Each
       virtual terminal provides the functions of a DEC VT100 terminal and, in
       addition, several control functions from the ISO 6429 (ECMA 48, ANSI
       X3.64) and ISO 2022 standards (e.g. insert/delete line and support for
       multiple character sets). There is a scrollback history buffer for
       each virtual terminal and a copy-and-paste mechanism that allows moving
       text regions between windows.

We will use the screen program to communicate with the Xilinx evaluation board ML403. Here is the setup.

Connecting the MacBook to the ML403 evaluation board

We will us the Keyspan usb to serial converter USA-19HS.

Download the driver software from Keyspan.
Install the driver and restart the computer.
Open a terminal
Start the screen program in the terminal using the command: screen /dev/tty.USA19H1b1P1.1
If you type screen /dev/tty.U and use the file completion (tab) you will find the right name.
Connect the usb contact to the usb port on your Mac and connect the serial connector to the evaluation board where is says Uart Host.
Turn on the power to the ML403 board and press the System ACE reset button.
This is what the screen window looks like.

We are ready to run the demo programs that come with the ML403 board.

More information

Use screen as serial terminal emulator (MacOSXHints)

Posted at 01:52 pm by svenand
Make a comment Permalink

New Horizons

Setting up our User Constraints File

Specifying Pin Constraints

Specifying Timing Constraints

XILINX JTAG tools on Linux without proprietary kernel modules