1. Write a small c-program or use machine code from start.
2. Compile the program using gcc and generate machine code in ASCII format.
3. Load the machine code to the MicroBlaze instruction memory.
4. Start the simulation and generate system clock and a reset.
5. The MicroBlaze processor will execute the program and write the result to the data memory.
6. Read the result and compare it to expected data.

ETC_SYSTEM_TEST

Simulation result

The program is executing. The MicroBlaze processor is reading instructions from the instruction memory. In the Simvision plot you can also see the content of the instruction memory displayed.




Write a simple c-program

Let's write a simple c-program adding two integers and storing the result.

Running a simulation

Here is the result from the simulation. The result (=1024) is stored in memory[3] location.




Reading and writing registers in peripherals

We will start by using simple peek and poke commands to access the registers in the peripherals.  First let's take a look at the address map which can be found in the ETC_system.log file.

MicroBlaze address map

(0000000000-0x00001fff) dlmb_cntlr               dlmb
(0000000000-0x00001fff) ilmb_cntlr               ilmb
(0x40000000-0x4000ffff) Push_Buttons_Position    mb_opb
(0x40020000-0x4002ffff) LEDs_Positions           mb_opb
(0x40040000-0x4004ffff) LEDs_4Bit                mb_opb
(0x40600000-0x4060ffff) RS232_Uart               mb_opb
(0x41400000-0x4140ffff) debug_module             mb_opb
(0x42a08000-0x42a08fff) ETC_0                    mb_opb
(0x42a09000-0x42a09fff) ETC_0                    mb_opb
(0x44000000-0x47ffffff) DDR_SDRAM_64Mx32         mb_opb
(0x71a00000-0x71a0000f) ETC_0                    mb_opb

C-program  to access registers in ETC

Here is a simple program that will do the job.

int main()

#define poke(addr,val)     (*(unsigned char*) (addr) = (val))
#define pokew(addr,val)    (*(unsigned*) (addr) = (val))
#define peek(addr)         (*(unsigned char*) (addr))
#define peekw(addr)        (*(unsigned*) (addr))
 

{   

   unsigned char byte_of_data;
   unsigned      word_of_data;
  
   pokew(0x71a00000,0xffffffff);
   pokew(0x71a00000,0xaaaaaaaa);
   pokew(0x71a00000,0x55555555);
   
   return 0;
}

Here is the assembly code.

   0:    3021fff0     addik    r1, r1, -16
   4:    fa61000c     swi      r19, r1, 12
   8:    12610000     addk     r19, r1, r0
   c:    3060ffff     addik    r3, r0, -1
  10:    b00071a0     imm      29088
  14:    f8600000     swi      r3, r0, 0
  18:    b000aaaa     imm      -21846
  1c:    3060aaaa     addik    r3, r0, -21846
  20:    b00071a0     imm      29088
  24:    f8600000     swi      r3, r0, 0
  28:    b0005555     imm      21845
  2c:    30605555     addik    r3, r0, 21845
  30:    b00071a0     imm      29088
  34:    f8600000     swi      r3, r0, 0
  38:    10600000     addk     r3, r0, r0
  3c:    10330000     addk     r1, r19, r0
  40:    ea61000c     lwi      r19, r1, 12
  44:    30210010     addik    r1, r1, 16
  48:    b60f0008     rtsd     r15, 8
  4c:    80000000     or       r0, r0, r0

From this Simvision plot we can see the address and data appear on the OPB bus.

open-source tool suite. The Platform Studio SDK is a complementary program to XPS; that is, from SDK, you can develop the software that the peripherals and processor(s) elements connected in XPS use.

You must create an SDK project for each software application. The project directory contains your C/C++ source files, executable output file, and associated utility files, such as the make files used to build the project. Each SDK project directory is typically located under the XPS project directory tree for the embedded system that the application targets. Each SDK project produces just one executable file, <project_name>.elf. Therefore, you may have more than one SDK project targeting a single XPS embedded system.

Software development flow


                                                                                                                    

Warning, on a Debian/Ubuntu machine, you will not have a binary called gmake, but "make" is already "gmake". You need to add a proper symlink: sudo ln -s /usr/bin/make /usr/bin/gmake

Running SDK

We will start SDK from inside the Xilinx Platform Studio. Read the EDK Concepts, Tools, and Techniques Chapter 6, The Software Platform and SDK for more information on how to write embedded software applications. To start SDK directly from  the terminal use the command: xps_sdk &

==> xps &

Before we start SDK let's take a look at the software platform settings. From the Software menu select Software Platform Settings.



Starting SDK

From the Software menu select Launch Platform Studio SDK to open SDK.






Let's read the Getting started with the Xilinx Platform Studio SDK

before we continue. To display the guide in your web browser click the Getting Started in the Welcome window. We will launch the Application Wizard to help us setup our first software project.

Xilinx Tools->Launch Application Wizard and select Import XPS Application Projects.



Click Next.



Mark the application TestApp_Memory and click Finish.


Creating a new C application project

We give the project a name and then click Finish.

The wizard starts working and after a few seconds the result is displayed. We are ready to write out first c-program.

A new directory called SDK_projects has been created with two projects in it.

1. I applied all updates to Ubuntu 6.10
2. I checked that I had the latest version of Update Manager (0.45.2). I had.
3. I opened the Update Manager: System->Administration->Update Manager
4. I was told that my system is up-to-date and that there is a new distribution release '7.04' available.
5. I clicked Upgrade and followed the on-screen instructions.

When the installation had finished after about an hour I was asked to restart the system. After the bootup the system came up without any problems.

No network connection

The system came up with the network connection disabled. An exclamation mark indicated there were no network connection.



This was easily fixed by selecting a wired network. The Parallels Desktop virtual machine will connect to the wireless network in Mac OS X through a wired network connection.

• Only Ubuntu Linux
• Technical Itch
• The Armorer's CodeX
• Simplehelp
• Unofficial Ubunu 7.04 Starter Guide
• Muffin Research Labs

What's new in Ubuntu 7.04

File sharing between Ubuntu and Mac OS X has been simplified. If we open the Network File Browser Places->Network this window is displayed. By using a ssh tunnel we can see the Mac OS X file system in the Ubuntu File Browser.



By using sftp we can move files between Ubuntu and Mac OS X.



Avahi Zeroconf Browser

Disk Usage Analyzer

Applications->Assessories->Disk Usage Analyzer



Ubuntu Help Center

If you click the question mark in the top panel you are transfered to the Ubuntu Help Center with tons of information.




Top

• Testcase FirstTest.tc selected
• Waveform generation enabled. Dump sst/wlf
• NCSIM used
• Compile/elaborate/simulate in one run selected
  

Here is the result.



The simulation stops after 110ns displaying the following error message: Input Error : RST on instance * must be asserted for 3 CLKIN clock cycles. It looks to me like the DCM  is missing a reset signal. Here starts the debugging phase. Up to now it has been "klipp och klistra" (Swedish for cut and glue) work. Now starts the real engineering work.
Let's open the Simvision waveform viewer

The dcm_1 block has no input clock. Let's dig into the problem. We will use the Simvision Schematic Tracer to help us find our way around in the design. Here is a view of the complete system.



Here is the dcm_1 block in full view.



Here is the explanation, the ddr_feedback clock is missing. We have to add one more clock generator in our testbench.

 always
   begin
    #DDR_CLK_ClockStart DDR_CLK_FB = 1;
    #DDR_CLK_ClockWidth DDR_CLK_FB = 0;
    #(DDR_CLK_ClockPeriod-DDR_CLK_ClockStart-DDR_CLK_ClockWidth);
   end
 

We will also add the DDR SDRAM to our simulation model.

Adding the DDR SDRAM

If we take a look at the Xilinx evaluation board we find two Micron DDR SDRAM 46V16M16 organized as 16Mx32. To download a Verilog model of this SDRAM we will go the

Here is an example showing the connection of two 16 bit DDR SDRAMS to the OPB DDR SDRAM controller.


                                                                                                                                           

. The bit and byte labeling for the big-endian data types is shown below. To address 32 bit words the address must be incremented by 4 to read the next word. One more observation, the MSB is bit 0 and the LSB is bit 31, opposite to what you may be used to.



The DDR SDRAM Verilog model

Let's see if the Verilog model (ddr.v) matches the OPB interface. Here is the module declaration:
module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm);  It seems we a perfect match.

Compilation of the Verilog DDR SDRAM module

We will compile the ddr.v file together with the include file ddr_parameters.vh to the database directory $ETC_VERIFICATION/database/ncsim/userlib/sdram_v1_00_a. The default memory compiled will have 16 bits data width and speed grade sg75Z. Fine for us.

Instantiation of two memory modules

Here is the instantiation that has been added to the EXT_system_testbench.tb.

//$$INSTANTIATION OF EXTERNAL COMPONENTS
/*************************************************************************/
/*                                                                       */
/*                 E X T E R N A L   C O M P O N E N T S                 */
/*                                                                       */
/*************************************************************************/


ddr    ddr_sdram_16_31    (

    .Clk                            (DDR_SDRAM_Clk_pin),
    .Clk_n                          (DDR_SDRAM_Clkn_pin),
    .Cs_n                           (DDR_SDRAM_CSn_pin),
    .Cke                            (DDR_SDRAM_CKE_pin),
    .Ba                             (DDR_SDRAM_BankAddr_pin),
    .Addr                           (DDR_SDRAM_Addr_pin),
    .Ras_n                          (DDR_SDRAM_RASn_pin),
    .Cas_n                          (DDR_SDRAM_CASn_pin),
    .We_n                           (DDR_SDRAM_WEn_pin),
    .Dm                             (DDR_SDRAM_DM_pin[2:3]),
    .Dqs                            (DDR_SDRAM_DQS_pin[2:3]),
    .Dq                             (DDR_SDRAM_DQ_pin[16:31]) );

ddr    ddr_sdram_0_15    (

    .Clk                            (DDR_SDRAM_Clk_pin),
    .Clk_n                          (DDR_SDRAM_Clkn_pin),
    .Cs_n                           (DDR_SDRAM_CSn_pin),
    .Cke                            (DDR_SDRAM_CKE_pin),
    .Ba                             (DDR_SDRAM_BankAddr_pin),
    .Addr                           (DDR_SDRAM_Addr_pin),
    .Ras_n                          (DDR_SDRAM_RASn_pin),
    .Cas_n                          (DDR_SDRAM_CASn_pin),
    .We_n                           (DDR_SDRAM_WEn_pin),
    .Dm                             (DDR_SDRAM_DM_pin[0:1]),
    .Dqs                            (DDR_SDRAM_DQS_pin[0:1]),
    .Dq                             (DDR_SDRAM_DQ_pin[0:15]) );

When we rerun our simulation the signals to the memory looks like this. Looks good to me.



If we run the simulation a little bit longer we get the following message.

ETC_SYSTEM_TEST.ddr_sdram_0_15: at time  202273 ns MEMORY:  Power Up and Initialization Sequence is complete
At time  202373 ns LMR  : Load Mode Register
At time  202373 ns LMR  : Burst Length = 2
At time  202373 ns LMR  : CAS Latency = 2

After the power up sequence is complete the auto refresh starts.




Suppressing assert messages in IEEE packages

When we have an 'x" in our simulation the VHDL packages will print millions of assert messages telling you there is an 'x' in your simulation. To suppress these message we can use the following tcl commands to ncsim:

ncsim> set pack_assert_off ieee.NUMERIC_STD
ncsim> set pack_assert_off ieee.STD_LOGIC_ARITH

We will add these commands to the TCL input file : $ETC_VERIFICATION/tcl/ncsim_tcl_input.def and they will be executed every time we run ncsim.

• Cadence Incisive Unified Simulator (IUS58) will be used
• The Mongoose Simulation Environment will be used to define the simulation setup
  
• All IP blocks are or will be compiled and storied in a simulation database
• All wrapper files and the top entity files will be compiled and stored in the database
• The verilog testbench template will be generated by the Topi Top Code Generator
• We have to find a verilog or VHDL model for the external SDRAM
  

Part 13 (Compiling everything) for information on how to compile the EDK libraries. Here is a view of the simulation database:

This is the printout from the compilation.



The following line in the cds.lib file defines the name and the location of the compilation database.

define etc_v1_00_a  /home/svenand/root/projects/ETC/verification/database/ncsim/userlib/etc_v1_00_a

Compiling Verilog wrappers

The ETC_system_verilog_v1_00_a.def contains all the Verilog wrappers. In our case only the ETC wrapper.



When compiling Verilog code you almost every time get a message telling you that some modules are missing timescale directives. The easiest way to fix this problem is to have a separate timescale file only containing a timescale directive. Like this: timescale 1ns/10ps. I call this file timescale.v and put it as the first file in the Verilog compile script.

Compiling VHDL wrappers

The ETC_system_vhdl_v1_00_a.def contains all the VHDL wrappers and the top entity.

define top   /home/svenand/root/projects/ETC/verification/database/ncsim/top_design

Elaborating the design

We have now compiled the whole design and are ready to elaborate. Here is the elaboration script generated from Mongoose:

/* NCSIM elaboration control file generated from Mongoose 15.5       */
/* Generation date :  2007-04-22                                     */
/* Generation time :  04:57:52                                       */

-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_system_vhdl_v1_00_a.elog
-messages
-notimingchecks
-access +rwc
ETC_SYSTEM

Here is the result from the elaboration.



Warning messages

During the elaboration phase you will probably see a lot of warnings displayed in the terminal window. For example:

ncelab: *W,CUDEFB: default binding occurred for component instance (:ETC_system(STRUCTURE):etc_0) with verilog module (top.etc_0_wrapper:module).

and

ncelab: *W,CUNOTB: component instance is not fully bound (:ETC_system(STRUCTURE):iobuf_47) [File:ETC_system.vhd, Line:2075]

To find out more about these warnings we can execute the following commands:

==> nchelp ncelab CUDEFB

nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab/CUDEFB =
    No explicit binding mechanism was found for the component instance
    in the form of a configuration specification or a component
    declaration. Default binding occurred with an entity having a
    visible entity declaration which had the same simple name as that
    of the instantiated component.

I do remember overhearing something about this particular message.  Default binding is a perfectly normal thing to
do, and is standard VHDL.  However, some customer was trying to use a methodology of requiring explicit binding for
everything.  To enforce this, they wanted a warning produced whenever default binding was used instead.  As a result,
everyone else has to put up with a bunch of warnings that they didn't care about.
I think we can ignore this warning. We will add this line to the elaboration script: -nowarn CUDEFB

1. Uses explicit binding indications
2. If there is no explicit binding indication, the elaborator tries to bind the component to in order:

• A design unit made visable with a USE clause given to the architecture instantiating the component.
• A design unit made visable with a USE clause given to the entity of the architecture instantiating the component.
• A design unit available in the library into whjich the component was compiled.
• A design unit in the work library

1. A design unit made visable with a LIBRARY clause given to the architecture instantiating the component (no corresponding USE clause).
2. A design unit made visable with a LIBRARY clause given to the entity of the architecture instantiating the component (no corresponding USE clause)
3. A design unit in a library defined in the cds.lib file. If a binding has not been found the elaborator opens the cds.lib file and searches all of the libraries that are defined.

• Bring the IP catalog tab forward
• Expand the Project Repository hierarchy
• Drag and drop the ETC into the System Assembly View or double click on the ETC.
• Expand the ETC instance
• Highlite the slave OPB connection (SOPB)
• Select the No Connection pull down menu and change it to mb_opb

Port connection

All OPB signals have already been connected to OPB bus. The remaining signals can be connected using the port view. We will make all signals external. Some input signals not used will be connected to ground and some unused output signals will be left unconnected.




Generate addresses

Select the Address filter to define addresses for the newly added ETC peripheral. The address can be assigned by entering the Base Address or the tool can assign an address. We will let the tool generate addresses:

• Change the size of the memory blocks to 1K and for the register map to 4.
• Click the Generate Addresses

A message in the console window will state that the address map has been generated successfully. The design is now ready to be implemented.

Mixed language design

All IP blocks from Xilinx are written in VHDL. The ETC IP is written in Verilog and therefor this design will be a mixed language design. The synthesis and simulation tools have no problems dealing with mixed language designs and hopefully this will not complicate our design job.

Set project options

Select Project->Project Options and click the HDL and Simulation tab. Because the majority of the design is in VHDL we will generate a VHDL top entity file. We will use NCSim for our simulations and we will allow mixed language behavioral files.





Generate the system netlist

We can now generate the system netlist. Click Hardware->Generate Netlist. The generation starts and returns with the following error message:

ERROR:MDT - INST:ETC_0 PORT:I_OPB_BE CONNECTOR:mb_opb_OPB_BE -
   /home/svenand/root/projects/ETC/xps/pcores/ETC_v1_00_a/data/ETC_v2_1_0.mpd
   line 43 - calculated index is out of signal VEC range of [0:3]

Completion time: 1.00 seconds

ERROR:MDT - platgen failed with errors!

make:
*** [implementation/microblaze_0_wrapper.ngc] Error 2

Done!

Let's open the

What happend during the netlist generation

When we start the netlist generation the following command is executed: platgen -p xc4vfx12ff668-10 -lang vhdl   ETC_system.mhs

• hdl
• implementation
• synthesis

The synthesis directory holds all synthesis scripts used when running the syntesis tool XST.




We are now ready to program the FPGA on the evaluation board and start debugging the design. But before we do that we will setup a simulation environment and simulate the whole design. I am an old ASIC designer. Always simulate before implement.

Generate simulation HDL files

We will try the Xilinx HDL simulation environment. To generate the simulation setup goto the Simulation menu and select Generate Simulation HDL Files. The following script will start: make -f ETC_system.make simmodel. When the script has finished a new directory called simulation has been created.



Here is the

• Using simulation, you don't have to wait for hardware to be complete before testing your software. The result: facilitated software development, which allows you meet more aggressive project deadlines.
• Simulation provides insight into the internal workings of your system. Signals and register values are more accessible in a simulated system than they are once a design is in hardware.
• Simulation also allows you complete control of your system. Conditions that may be difficult to create in a hardware setting are relatively easy to simulate.
  

1. cd /home/svenand/root/projects/ETC/xps/simulation/behavioral
2. chmod 777 ETC_system.sh (make script executable)
   
3. chmod 777 ETC_system_setup.sh
4. Edit the ETC_system_setup.sh file and change -lib_binding to -relax
   
5. Start the simulation script: ./ETC_system_setup.sh
   

1. The interface required by your IP must be determined.
   The bus to which your custom peripheral will attach must be identified. For example:
   a. Processor Local Bus (PLB). The PLB provides a high-speed interface between the processor and high-performance peripherals.
   b. On-chip Peripheral Bus (OPB). The OPB allows processor access to low-speed, low-performance system resources.
2. Functionality must be implemented and verified.
   Your custom functionality must be implemented and verified, with awareness that common functionality available from the EDK peripherals library can be reused. Your
   stand-alone core must be verified. Isolating the core ensures easier debug in the future.
3. The IP must be imported to EDK.
   Your peripheral must be copied to an EDK-appropriate directory, and the Platform
   Specification Format (PSF) interface files (MPD and PAO) must be created, so other
   EDK tools can recognize your peripheral.
4. Your peripheral must be added to the processor system created in XPS.
   

Create or import an user peripheral

One of the key advantages of building an embedded system in an FPGA is the ability to include customer IP and interface that IP to the processor. To start the Create and Import Peripheral Wizard select Hardware->Create or Import Peripheral.



Click the More Info button for more information. We will import an existing peripheral.






We will call our peripheral ETC (the name of the top module) and add a version to the name.




The peripheral is made up of Verilog files (.v).



We will use the ISE project file to define the Verilog source code.



Here are all the verilog source files.



The ETC peripheral will operate as an OPB slave (SOPB) and the OPB interface is already designed and verified. The

The wizard tries to map the ETC interface names to the standard naming convention for OPB. All the names that don't match have to be manually inserted.




It seems like we are missing some of the optional OPB signals. I have to add these signals to the top module

In this window we have to select the right parameters defining the address range for registers and memory banks.




Here we define the interrupt signal and the operation of the interrupt.




Congratulations! We have added our peripheral to the current XPS project. Good work.





Here are all files in the pcores directory.



File description

XPS provides an interactive development environment that allows you to specify all aspects of your hardware platform. XPS maintains your hardware platform description in a high-level form, known as the Microprocessor Hardware Specification (MHS) file. The MHS, an editable text file, is the principal source file representing the hardware component of your embedded system. XPS synthesizes the MHS source file into Hardware Description Language (HDL) netlists ready for FPGA place and route.

The MHS File

The MHS file is integral to your design process. It contains all peripherals along with their parameters. The MHS file defines the configuration of the embedded processor system and includes information on the bus architecture, peripherals, processor, connectivity, and address space. For more detailed information on the MHS file, refer to the "Microprocessor Hardware Specification (MHS)" chapter of the Platform Specification Format Reference Manual, available at

EDK is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx FPGA device. To run EDK, ISE must be installed as well. Think of it as an umbrella covering all things related to embedded processor systems and their design.

Xilinx Platform Studio (XPS)

XPS is the development environment or GUI used for designing the hardware portion of your embedded processor system.

Software Development Kit (SDK)

Platform Studio SDK is an integrated development environment, complimentary to XPS, that is used for C/C++ embedded software application creation and verification. SDK is built on the Eclipse™ open-source framework. Because many other software development tools are being built on the Eclipse infrastructure, this software development tool might already be familiar to you or members of your design team.

EDK includes other elements such as:
•    Hardware IP for the Xilinx embedded processors
•    Drivers and libraries for embedded software development
•    GNU Compiler and debugger for C/C++ software development targeting the MicroBlaze™ and PowerPC™ processors
•    Documentation
•    Sample projects

The utilities provided with EDK are designed to assist in all phases of the embedded design process.



                                                                                                                                        

==> cd $ETC_PROJECT
==> xps&
[1] 4463
==>
Xilinx Platform Studio
Xilinx EDK 9.1 Build EDK_J.19
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Launching XPS GUI...
Overriding Xilinx file <mdtgui/images/xps-splash-screen.bmp> with local file
</home/svenand/cad/edk91i/data/mdtgui/images/xps-splash-screen.bmp>




We will create a new project using the Base System Builder wizard (see chapter 2 in CTTG).



First we have to create a new top-level project file (ETC_system.xmp). A Xilinx Microprocessor Project (XMP) file is the top-level file description of the embedded system under development. All XPS project information is saved in the XMP file, including the location of the Microprocessor Hardware Specification (MHS) and Microprocessor  Software Specification (MSS) files. The MHS and MSS files are described in detail later.




When I click the OK button I get the following error message:

I just realized there is a service pack 1 available for EDK 9.1i. I will download this sevice pack and see if it fixes the problem. The service pack fixed the problem. Sorry to bother you Xilinx.



We would like to create a new design for the ML403 evaluation board.



We will use the MicroBlaze soft processor.



We will use the 100MHz system clock available on the board, an active low reset signal and we will have an on-chip debug module. We don't need memory caches and a floating point unit.



In the next four pages we will select the peripherals to use:



We will change the baudrate to 57600 at a later stage.









The UART will be used for the serial communication between the board and the terminal.



Here are more information about available IO devices:

When we click the Generate button, we will start the generation of our embedded system.




We have now put together our embedded system. We can always go back and add or remove IO interfaces at a later stage. Here is the file tree generated from XPS.

• blkdiagram - contains the blockdiagram of our system that can be displayed in a web browser (ETC_system.html).
  
• data - contains the UCF (user constraints file) for the target board
• etc - contains system settings for JTAG configuration on the board that is used when downloading the bit file and the default parameters that are passed to the ISE tools
• pcores - is empty right now, but is utilized for custom peripherals
• TestApp_Memory - contains a user application in C code source, for testing the memory in the system

Look at project options

Select Project->Project Options to display the current project setup.



Generate a design report file

To generate a design report file select Project->Generate and view design report. The design report will be stored in the report directory and can be viewed in a web browser (ETC_system.html).


Now it's time to add our own IP block, the Embedded Test Controller (ETC). That is the subject of the next part.