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FPGA design from scratch. Part 22
Using the XPS Software Development Kit
It is time to start writing some small programs to be used in our simulations. We will use the Platform Studio Software Devlopment Kit (SDK) to help us out with this task.
The Platform Studio Software Development Kit (SDK) was designed to facilitate the development of embedded software application projects. SDK has its own GUI and is based on the Eclipse open-source tool suite. The Platform Studio SDK is a complementary program to XPS; that is, from SDK, you can develop the software that the peripherals and processor(s) elements connected in XPS use.
You must create an SDK project for each software application. The project directory contains your C/C++ source files, executable output file, and associated utility files, such as the make files used to build the project. Each SDK project directory is typically located under the XPS project directory tree for the embedded system that the application targets. Each SDK project produces just one executable file, <project_name>.elf. Therefore, you may have more than one SDK project targeting a single XPS embedded system.
Software development flow
(Courtesy of Xilinx)
GNU Compiler Collection
The GNU Compiler Collection (usually shortened to GCC) is a set of programming language compilers produced by the GNU Project.
Executable and Linkage Format file
In computing, the Executable and Linking Format (ELF, formerly called Extensible Linking Format) is a common standard file format for executables, object code, shared libraries, and core dumps
Missing gmake
Warning, on a Debian/Ubuntu machine, you will not have a binary called gmake, but "make" is already "gmake". You need to add a proper symlink: sudo ln -s /usr/bin/make /usr/bin/gmake Running SDK We will start SDK from inside the Xilinx Platform Studio. Read the EDK Concepts, Tools, and Techniques Chapter 6, The Software Platform and SDK for more information on how to write embedded software applications. To start SDK directly from the terminal use the command: xps_sdk &
==> xps & 
Before we start SDK let's take a look at the software platform settings. From the Software menu select Software Platform Settings.
Starting SDK
From the Software menu select Launch Platform Studio SDK to open SDK.
Let's read the Getting started with the Xilinx Platform Studio SDK before we continue. To display the guide in your web browser click the Getting Started in the Welcome window. We will launch the Application Wizard to help us setup our first software project.
Xilinx Tools->Launch Application Wizard and select Import XPS Application Projects.
Click Next.
Mark the application TestApp_Memory and click Finish.
Creating a new C application project
We give the project a name and then click Finish.  The wizard starts working and after a few seconds the result is displayed. We are ready to write out first c-program.
A new directory called SDK_projects has been created with two projects in it. 
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Posted at 02:21 pm by svenand
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FPGA design from scratch. Part 21
Debugging IP blocks
All Xilinx IP blocks are protected, meaning we don't have access to the RTL code and we can't probe internal nodes during a simulation. This makes debugging complicated. We can only observe input and output signals to the IP block and we have no idea what is going on inside the block.
The reset logic
The OPB_V20 design includes several sources for bus reset. A power-on reset circuit asserts the OPB_Rst for 16 clock cycles anytime the FPGA has completed configuration. External resets that occur during the 16 clock reset time are ignored. After the 16-clock reset has completed, external resets can be applied to the OPB_V20 reset signals. The external resets are: SYS_Rst (can be configured as high-true or low-true), WDT_Rst, and Debug_SYS_Rst. SYS_Rst is the main user reset for the OPB and can be connected to internal logic or an external signal or switch.
WDT_Rst can be connected to the reset output of a Watchdog Timer to allow for OPB resets in the event of a watchdog time-out. Debug_SYS_Rst can be connected to the reset output of a debug peripheral, such as the JTAG UART, so that the debugger can remotely reset the OPB. SYS_Rst, WDT_Rst, and Debug_SYS_Rst are synchronized to the OPB_Clk in the OPB_V20, but the width of these signals is otherwise unaltered.
Reset signal polarity
What is the polarity of the reset signal. Here is the specification for the opb_v20 setup, taken from the ETC_system.mhs file.
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 0
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
The PARAMETER C_EXT_RESET_HIGH = 0 specification means that the reset signal is active low.
The system reset SYS_rst goes to the opb_mb block and should propagate through this block and generate the inverted OPB_rst signal.
MicroBlaze reset
When a Reset (OPB_rst) or Debug_Rst occurs, MicroBlaze will flush the pipeline and start fetching instructions from the reset vector (address 0x0). Both external reset signals are active high, and should be asserted for a minimum of 16 cycles.
All output signals are defined from the opb_mb block and we have the reset signal to the MicroBlaze processor coming through. We are ready for more advanced simulations. First we have to study how the MicroBlaze processor operates. Here is the MicroBlaze Processor Reference Guide.
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Posted at 12:47 pm by svenand
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FPGA design from scratch. Part 20
Running our first simulation
Our first testcase will be a simple one. We will start the system clock running at 100MHz. After a few clock cycles we will assert the system reset and watch what happens. Here is the testcase.
We are ready to start.
- Testcase FirstTest.tc selected
- Waveform generation enabled. Dump sst/wlf
- NCSIM used
- Compile/elaborate/simulate in one run selected
Here is the result.
The simulation stops after 110ns displaying the following error message: Input Error : RST on instance * must be asserted for 3 CLKIN clock cycles. It looks to me like the DCM is missing a reset signal. Here starts the debugging phase. Up to now it has been "klipp och klistra" (Swedish for cut and glue) work. Now starts the real engineering work.
Let's open the Simvision waveform viewer by clicking the Simvision button in the terminal window, find the dcm_0 and dcm_1 in the design browser, select all signals and open the waveform viewer.
The dcm_1 block has no input clock. Let's dig into the problem. We will use the Simvision Schematic Tracer to help us find our way around in the design. Here is a view of the complete system.
Here is the dcm_1 block in full view.
Here is the explanation, the ddr_feedback clock is missing. We have to add one more clock generator in our testbench.
always
begin
#DDR_CLK_ClockStart DDR_CLK_FB = 1;
#DDR_CLK_ClockWidth DDR_CLK_FB = 0;
#(DDR_CLK_ClockPeriod-DDR_CLK_ClockStart-DDR_CLK_ClockWidth);
end
We will also add the DDR SDRAM to our simulation model.
Adding the DDR SDRAM
If we take a look at the Xilinx evaluation board we find two Micron DDR SDRAM 46V16M16 organized as 16Mx32. To download a Verilog model of this SDRAM we will go the Micron web page.
Before we connect the DDR SDRAM to the ETC system we will study the SDRAM interface already implemented and try to understand how it works. Here is the Xilinx document describing the interface. This table shows all the external signals in the DDR SDRAM interface.
| Signal | Width | Dir
| Description | | DDR_SDRAM_Clk_pin | 1 | Out
| Clock | | DDR_SDRAM_Clkn_pin | 1 | Out
| Clock inverted
| | DDR_SDRAM_Addr_pin | 0 : 12 | Out
| Address bus
| | DDR_SDRAM_BankAddr_pin | 0 : 1 | Out
| Bank address
| | DDR_SDRAM_CASn_pin | 1 | Out
| Active low column address strobe | | DDR_SDRAM_CKE_pin | 1 | Out
| Clock enable
| | DDR_SDRAM_CSn | 1 | Out
| Active low chip select | | DDR_SDRAM_RASn | 1 | Out
| Active low row address strobe | | DDR_SDRAM_WEn_pin | 1 | Out
| Active low write enable | | DDR_SDRAM_DM_pin | 0 : 3 | Out
| Data mask | | DDR_SDRAM_DQS_pin | 0 : 3 | Inout
| Data strobe both read and write
| | DDR_SDRAM_DQ_pin | 0 : 31
| Inout
| Data bus in/out | Here is an example showing the connection of two 16 bit DDR SDRAMS to the OPB DDR SDRAM controller.
(Courtesy of Xilinx)
Memory organization
OPB DDR SDRAM memory can be accessed as byte (8 bits), halfword (2 bytes), word (4 bytes) or Double word (8 bytes) depending on the size of the bus to which the processor is attached. From the point of view of the OPB, data is organized as big-endian. The bit and byte labeling for the big-endian data types is shown below. To address 32 bit words the address must be incremented by 4 to read the next word. One more observation, the MSB is bit 0 and the LSB is bit 31, opposite to what you may be used to.
The DDR SDRAM Verilog model
Let's see if the Verilog model (ddr.v) matches the OPB interface. Here is the module declaration:
module ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); It seems we a perfect match.
Compilation of the Verilog DDR SDRAM module
We will compile the ddr.v file together with the include file ddr_parameters.vh to the database directory $ETC_VERIFICATION/database/ncsim/userlib/sdram_v1_00_a. The default memory compiled will have 16 bits data width and speed grade sg75Z. Fine for us.
Instantiation of two memory modules
Here is the instantiation that has been added to the EXT_system_testbench.tb.
//$$INSTANTIATION OF EXTERNAL COMPONENTS
/*************************************************************************/
/* */
/* E X T E R N A L C O M P O N E N T S */
/* */
/*************************************************************************/
ddr ddr_sdram_16_31 (
.Clk (DDR_SDRAM_Clk_pin),
.Clk_n (DDR_SDRAM_Clkn_pin),
.Cs_n (DDR_SDRAM_CSn_pin),
.Cke (DDR_SDRAM_CKE_pin),
.Ba (DDR_SDRAM_BankAddr_pin),
.Addr (DDR_SDRAM_Addr_pin),
.Ras_n (DDR_SDRAM_RASn_pin),
.Cas_n (DDR_SDRAM_CASn_pin),
.We_n (DDR_SDRAM_WEn_pin),
.Dm (DDR_SDRAM_DM_pin[2:3]),
.Dqs (DDR_SDRAM_DQS_pin[2:3]),
.Dq (DDR_SDRAM_DQ_pin[16:31]) );
ddr ddr_sdram_0_15 (
.Clk (DDR_SDRAM_Clk_pin),
.Clk_n (DDR_SDRAM_Clkn_pin),
.Cs_n (DDR_SDRAM_CSn_pin),
.Cke (DDR_SDRAM_CKE_pin),
.Ba (DDR_SDRAM_BankAddr_pin),
.Addr (DDR_SDRAM_Addr_pin),
.Ras_n (DDR_SDRAM_RASn_pin),
.Cas_n (DDR_SDRAM_CASn_pin),
.We_n (DDR_SDRAM_WEn_pin),
.Dm (DDR_SDRAM_DM_pin[0:1]),
.Dqs (DDR_SDRAM_DQS_pin[0:1]),
.Dq (DDR_SDRAM_DQ_pin[0:15]) );
When we rerun our simulation the signals to the memory looks like this. Looks good to me.
If we run the simulation a little bit longer we get the following message.
ETC_SYSTEM_TEST.ddr_sdram_0_15: at time 202273 ns MEMORY: Power Up and Initialization Sequence is complete
At time 202373 ns LMR : Load Mode Register
At time 202373 ns LMR : Burst Length = 2
At time 202373 ns LMR : CAS Latency = 2
After the power up sequence is complete the auto refresh starts.
Suppressing assert messages in IEEE packages
When we have an 'x" in our simulation the VHDL packages will print millions of assert messages telling you there is an 'x' in your simulation. To suppress these message we can use the following tcl commands to ncsim:
ncsim> set pack_assert_off ieee.NUMERIC_STD
ncsim> set pack_assert_off ieee.STD_LOGIC_ARITH
We will add these commands to the TCL input file : $ETC_VERIFICATION/tcl/ncsim_tcl_input.def and they will be executed every time we run ncsim.
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Posted at 03:38 pm by svenand
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FPGA design from scratch. Part 19 FPGA design from scratch. Part 18
Putting together a system simulation environment
This is probably the hardest part in our FPGA design from scratch journey. We have to do this job outside the Xilinx design environment and we can't expect much help from ISE or XPS.
Prerequisites
- Cadence Incisive Unified Simulator (IUS58) will be used
- The Mongoose Simulation Environment will be used to define the simulation setup
- All IP blocks are or will be compiled and storied in a simulation database
- All wrapper files and the top entity files will be compiled and stored in the database
- The verilog testbench template will be generated by the Topi Top Code Generator
- We have to find a verilog or VHDL model for the external SDRAM
To find out more about the Mongoose and Topi programs read the Zoo Design Platform documentation. Before we start let's see what help we can get from the Xilinx design flow. We will take a look in the EDK 9.1i Concepts, Tools and Techniques Guide, part 3 Introduction to Simulation in XPS.Simulation databaseAll IP blocks, macro libraries, wrapper files and testbench files are compiled and stored in the simulation library. When we ran the program compedklib all Xilinx IPs and Xilinx macro libraries were compiled. See Part 13 (Compiling everything) for information on how to compile the EDK libraries. Here is a view of the simulation database:
Library Name
| Directory Path
| Description | | unisim | ../database/macrolib/unisim | Unit delay macro library
| simprim
| ../database/macrolib/simprim
| Timing simulation macro library
| XilinxCoreLib
| ../database/macrolib/XilinxCoreLib
| Xilinx Core Functions
| | edklib | ../database/edklib/ip_name | Xilinx EDK IPs
| | userlib | ../database/userlib/user_ip_name | User IPs
| | top | ../database/top_design | Top entity, IP wrappers
| testbench
| ../database/testbench/testcase_name
| Testbench+testcases
| The cds.lib fileThe mapping of library names to physical file locations is done in the cds.lib file which must be referenced in the NCsim compile script. When we compiled the simulation libraries using compedklib this cds.lib was generated for us. This file contains all the available IPs and is overkill for us. Let's find out exactly which libraries we need and remove the unused ones. We will open the wrapper files and look for used libraries:
Wrapper file
| Libarary Name
| Design Document
| | clk90_inv_wrapper.vhd | util_vector_logic_v1_00_a |
| | dcm_0_wrapper.vhd | dcm_module_v1_00_b |
| | dcm_1_wrapper.vhd | dcm_module_v1_00_b | dcm_module.pdf | | ddr_clk90_inv_wrapper.vhd | util_vector_logic_v1_00_a |
| | ddr_sdram_64mx32_wrapper.vhd | opb_ddr_v2_00_c | opb_ddr.pdf | | debug_module_wrapper.vhd | opb_mdm_v2_00_a | opb_mdm.pdf | | dlmb_cntlr_wrapper.vhd | lmb_bram_if_cntlr_v2_00_a |
| | dlmb_wrapper.vhd | lmb_v10_v1_00_a |
| | ilmb_cntlr_wrapper.vhd | lmb_bram_if_cntlr_v2_00_a |
| ilmb_wrapper.vhd
| lmb_v10_v1_00_a
|
| leds_4bit_wrapper.vhd
| opb_gpio_v3_01_b
| opb_gpio.pdf | leds_positions_wrapper.vhd
| opb_gpio_v3_01_b |
| lmb_bram_wrapper.vhd
| lmb_bram_elaborate_v1_00_a
|
| mb_opb_wrapper.vhd
| opb_v20_v1_10_c
| opb_v20.pdf | microblaze_0_wrapper.vhd
| microblaze_v6_00_b
|
| push_buttons_position_wrapper.vhd
| opb_gpio_v3_01_b
|
| rs232_uart_wrapper.vhd
| opb_uartlite_v1_00_b
| opb_uartlite.pdf | sysclk_inv_wrapper.vhd
| util_vector_logic_v1_00_a
|
| After removing all unused libraries our cds.lib file looks like this.
Compiling the ETC IP
From now on we will use the Mongoose simulation environment for our simulation setup. Here everything is setup to compile the Embedded Test Controller IP block. ETC_block_verilog_v1_00_a.def contains all the Verilog HDL files defining the ETC.
Here is the compilation script generated from Mongoose.
/* Ncvlog compilation control file generated from Mongoose 15.5 */
/* Generation date : 2007-04-15 */
/* Generation time : 14:11:52 */
-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-work etc_v1_00_a
-file /home/svenand/root/projects/ETC/verification/designDefine/rtl/SYSTEM/etc/ETC_block_verilog_v1_00_a.def
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_block_verilog_v1_00_a.clog
-messages
This is the printout from the compilation.
The following line in the cds.lib file defines the name and the location of the compilation database.
define etc_v1_00_a /home/svenand/root/projects/ETC/verification/database/ncsim/userlib/etc_v1_00_a Compiling the block RAM
During the HDL generation a bram VHDL model (lmb_bram_elaborate.vhd) has been generated and stored in the directory: ../xps/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl. We will compile this model and store it in the simulation database: $ETC_VERIFICATION/database/ncsim/userlib/lmb_bram_elaborate_v1_00_a using the library name lmb_bram_elaborate_v1_00_a.
Compiling Verilog wrappers
The ETC_system_verilog_v1_00_a.def contains all the Verilog wrappers. In our case only the ETC wrapper.
When compiling Verilog code you almost every time get a message telling you that some modules are missing timescale directives. The easiest way to fix this problem is to have a separate timescale file only containing a timescale directive. Like this: timescale 1ns/10ps. I call this file timescale.v and put it as the first file in the Verilog compile script.
Compiling VHDL wrappers
The ETC_system_vhdl_v1_00_a.def contains all the VHDL wrappers and the top entity.
This line in the cds.lib file defines the name and the location of the wrapper simulation database:
define top /home/svenand/root/projects/ETC/verification/database/ncsim/top_design
Elaborating the design
We have now compiled the whole design and are ready to elaborate. Here is the elaboration script generated from Mongoose:
/* NCSIM elaboration control file generated from Mongoose 15.5 */
/* Generation date : 2007-04-22 */
/* Generation time : 04:57:52 */
-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_system_vhdl_v1_00_a.elog
-messages
-notimingchecks
-access +rwc
ETC_SYSTEM
Here is the result from the elaboration.
Warning messages
During the elaboration phase you will probably see a lot of warnings displayed in the terminal window. For example:
ncelab: *W,CUDEFB: default binding occurred for component instance (:ETC_system(STRUCTURE):etc_0) with verilog module (top.etc_0_wrapper:module).
and
ncelab: *W,CUNOTB: component instance is not fully bound (:ETC_system(STRUCTURE):iobuf_47) [File:ETC_system.vhd, Line:2075]
To find out more about these warnings we can execute the following commands:
==> nchelp ncelab CUDEFB
nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab/CUDEFB =
No explicit binding mechanism was found for the component instance
in the form of a configuration specification or a component
declaration. Default binding occurred with an entity having a
visible entity declaration which had the same simple name as that
of the instantiated component.I do remember overhearing something about this particular message. Default binding is a perfectly normal thing to
do, and is standard VHDL. However, some customer was trying to use a methodology of requiring explicit binding for
everything. To enforce this, they wanted a warning produced whenever default binding was used instead. As a result,
everyone else has to put up with a bunch of warnings that they didn't care about.
I think we can ignore this warning. We will add this line to the elaboration script: -nowarn CUDEFB
==> nchelp ncelab CUNOTB
nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab/CUNOTB =
The (hierarchically) named component instance was not bound
to an entity declaration along with a corresponding
architecture body [5.2.1.1]. When this occurs, the component
instantiation statement designated by the label in the
hierarchical name shown has no effect [12.4.3]. This may have
been due to a non-successful search through the binding search
order. Following is the search order for all default bindings
1) A design unit made visible with a USE clause visible to
the architecture instantiating the component.
2) A design unit made visible with a USE clause visible to
the entity of the architecture instantiating the component.
3) A design unit available in the library to which the
component was compiled.
4) A design unit in the WORK library.
One of the above rules must provide for an entity to which the
instance can be bound. Using other options to expand the search
for default bindings can impact the ncelab performance. The user
may first want to try modifying the design so that an entity can
be found using the above stated rules. In most cases, it would
imply adding appropriate USE clauses or compiling components into
the same library to which the corresponding entity has been
compiled.
This warning is a more serious one. We have things missing in our design. Here is the elaboration log file. We have to get rid of these warnings before we can continue.
I will ask Xilinx for help by creating a WebCase. The answer from Xilinx came the next day and was a reference to the Answer Database #19446. In that example they used the option -lib_binding to ncelab. That was the answer to my problems.
Using the -lib_binding and -relax options
In the NC-VHDL Simulator Help manual we can read the following:
By default, the elaborator adheres to a strict interpretation of the VHDL LRM, which states that you must use LIBRARY statements with corresponding USE clauses in the source code to provide visibility to the declarative region that an unbound instance resides in. To bind component instances to compiled design units in the libraries, the elaborator:
- Uses explicit binding indications
- If there is no explicit binding indication, the elaborator tries to bind the component to in order:
- A design unit made visable with a USE clause given to the architecture instantiating the component.
- A design unit made visable with a USE clause given to the entity of the architecture instantiating the component.
- A design unit available in the library into whjich the component was compiled.
- A design unit in the work library
If a binding cannot be found, the elaborator generates an error (unbound ...).
To extend the binding rules there are two options we can use:
-lib_binding
-relax
We will use the -relax option which extends the set of binding rules with the following rules:
- A design unit made visable with a LIBRARY clause given to the architecture instantiating the component (no corresponding USE clause).
- A design unit made visable with a LIBRARY clause given to the entity of the architecture instantiating the component (no corresponding USE clause)
- A design unit in a library defined in the cds.lib file. If a binding has not been found the elaborator opens the cds.lib file and searches all of the libraries that are defined.
Specify the timescale precision for VHDL
According to the IEEE 1076-1993 VHDL Language Reference Manual (Section 3.1.3.1), the primary unit of type TIME (1 femtosecond) is, by default, the resolution limit for type TIME. All simulations run in femtoseconds by default. Use the -vhdl_time_precision option to specify a secondary unit of type TIME as the resolution limit. Setting the timing resolution to a coarser value may increase simulation performance, as the simulator will not default to femtoseconds. We will use 1ps as our timing resolution.
-vhdl_time_precision 1ps
The modified elaboration script
/* NCSIM elaboration control file generated from Mongoose 15.5 */
/* Generation date : 2007-04-23 */
/* Generation time : 04:57:52 */
-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_system_vhdl_v1_00_a.elog
-messages
-notimingchecks
-nowarn CUDEFB
-relax
-vhdl_time_precision 1ps-access +rwc
ETC_SYSTEM
Here is the elaboration log file. No errors. Great news.
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FPGA design from scratch. Part 17
Posted at 06:59 pm by svenand
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FPGA design from scratch. Part 16
IP creation overview
Any piece of IP you create must be compliant with the system that is in place. To ensure compliance, the following must occur:
- The interface required by your IP must be determined.
The bus to which your custom peripheral will attach must be identified. For example:
a. Processor Local Bus (PLB). The PLB provides a high-speed interface between the processor and high-performance peripherals.
b. On-chip Peripheral Bus (OPB). The OPB allows processor access to low-speed, low-performance system resources. - Functionality must be implemented and verified.
Your custom functionality must be implemented and verified, with awareness that common functionality available from the EDK peripherals library can be reused. Your
stand-alone core must be verified. Isolating the core ensures easier debug in the future. - The IP must be imported to EDK.
Your peripheral must be copied to an EDK-appropriate directory, and the Platform
Specification Format (PSF) interface files (MPD and PAO) must be created, so other
EDK tools can recognize your peripheral. - Your peripheral must be added to the processor system created in XPS.
Create or import an user peripheral
One of the key advantages of building an embedded system in an FPGA is the ability to include customer IP and interface that IP to the processor. To start the Create and Import Peripheral Wizard select Hardware->Create or Import Peripheral.
Click the More Info button for more information. We will import an existing peripheral.
We will call our peripheral ETC (the name of the top module) and add a version to the name.
The peripheral is made up of Verilog files (.v).
We will use the ISE project file to define the Verilog source code.
Here are all the verilog source files.
The ETC peripheral will operate as an OPB slave (SOPB) and the OPB interface is already designed and verified. The On-chip Peripheral Bus (OPB) is an IBM standard and is also used in the Power PC processor.
The wizard tries to map the ETC interface names to the standard naming convention for OPB. All the names that don't match have to be manually inserted.
It seems like we are missing some of the optional OPB signals. I have to add these signals to the top module ETC.v. I will add the missing pins and also some parameter statements defining register and memory address ranges. Like this:
parameter REGISTER_BASE_ADDR = 32'h2000;
parameter REGISTER_HIGH_ADDR = 32'h200c;
parameter MEM_BANK0_BASE_ADDR = 32'h0;
parameter MEM_BANK0_HIGH_ADDR = 32'hffc;
parameter MEM_BANK1_BASE_ADDR = 32'h1000;
parameter MEM_BANK1_HIGH_ADDR = 32'h1ffc;
In this window we have to select the right parameters defining the address range for registers and memory banks.
Here we define the interrupt signal and the operation of the interrupt.
Congratulations! We have added our peripheral to the current XPS project. Good work.
Here are all files in the pcores directory.
File description
XPS provides an interactive development environment that allows you to specify all aspects of your hardware platform. XPS maintains your hardware platform description in a high-level form, known as the Microprocessor Hardware Specification (MHS) file. The MHS, an editable text file, is the principal source file representing the hardware component of your embedded system. XPS synthesizes the MHS source file into Hardware Description Language (HDL) netlists ready for FPGA place and route.
The MHS File
The MHS file is integral to your design process. It contains all peripherals along with their parameters. The MHS file defines the configuration of the embedded processor system and includes information on the bus architecture, peripherals, processor, connectivity, and address space. For more detailed information on the MHS file, refer to the "Microprocessor Hardware Specification (MHS)" chapter of the Platform Specification Format Reference Manual, available at http://www.xilinx.com/ise/embedded/edk_docs.htm.
XPS Project Files
Here are more information about the XPS project files used.
Xilinx IP center
There are many IP blocks available from Xilinx. Find out more in the Xilinx IP center.
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Posted at 10:02 pm by svenand
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FPGA design from scratch. Part 15
EDK is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx FPGA device. To run EDK, ISE must be installed as well. Think of it as an umbrella covering all things related to embedded processor systems and their design.
Xilinx Platform Studio (XPS)
XPS is the development environment or GUI used for designing the hardware portion of your embedded processor system.
Software Development Kit (SDK)
Platform Studio SDK is an integrated development environment, complimentary to XPS, that is used for C/C++ embedded software application creation and verification. SDK is built on the Eclipse™ open-source framework. Because many other software development tools are being built on the Eclipse infrastructure, this software development tool might already be familiar to you or members of your design team.
EDK includes other elements such as:
• Hardware IP for the Xilinx embedded processors
• Drivers and libraries for embedded software development
• GNU Compiler and debugger for C/C++ software development targeting the MicroBlaze™ and PowerPC™ processors
• Documentation
• Sample projects
The utilities provided with EDK are designed to assist in all phases of the embedded design process.
(Courtesy of Xilinx)
Using Xilinx Platform Studio
This is going to be fun. Let's start xps. We will use the EDK 9.1 MicroBlaze Tutorial in Virtex-4 and the EDK 9.1i Concepts, Tools and Techniques Guide (CTTG) as we go along.
For more documents go to the Xilinx Platform Studio Documentation.
XPS Design checklist
This page provides a summary of all necessary steps and commonly used optional steps to complete an embedded processor system design.
==> cd $ETC_PROJECT
==> xps&
[1] 4463
==>
Xilinx Platform Studio
Xilinx EDK 9.1 Build EDK_J.19
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Launching XPS GUI...
Overriding Xilinx file <mdtgui/images/xps-splash-screen.bmp> with local file
</home/svenand/cad/edk91i/data/mdtgui/images/xps-splash-screen.bmp>
We will create a new project using the Base System Builder wizard (see chapter 2 in CTTG).
First we have to create a new top-level project file (ETC_system.xmp). A Xilinx Microprocessor Project (XMP) file is the top-level file description of the embedded system under development. All XPS project information is saved in the XMP file, including the location of the Microprocessor Hardware Specification (MHS) and Microprocessor Software Specification (MSS) files. The MHS and MSS files are described in detail later.
When I click the OK button I get the following error message:
ERROR:PersonalityModule:7 - Unable to open Xilinx data file for Vendor/Device
Module "qrvirtex2". Please make sure that it has been correctly installed
before continuing.
I just realized there is a service pack 1 available for EDK 9.1i. I will download this sevice pack and see if it fixes the problem. The service pack fixed the problem. Sorry to bother you Xilinx.
We would like to create a new design for the ML403 evaluation board.
We will use the MicroBlaze soft processor.
We will use the 100MHz system clock available on the board, an active low reset signal and we will have an on-chip debug module. We don't need memory caches and a floating point unit.
In the next four pages we will select the peripherals to use:
We will change the baudrate to 57600 at a later stage.
The UART will be used for the serial communication between the board and the terminal.
Here are more information about available IO devices:
When we click the Generate button, we will start the generation of our embedded system.
We have now put together our embedded system. We can always go back and add or remove IO interfaces at a later stage. Here is the file tree generated from XPS.
- blkdiagram - contains the blockdiagram of our system that can be displayed in a web browser (ETC_system.html).
- data - contains the UCF (user constraints file) for the target board
- etc - contains system settings for JTAG configuration on the board that is used when downloading the bit file and the default parameters that are passed to the ISE tools
- pcores - is empty right now, but is utilized for custom peripherals
- TestApp_Memory - contains a user application in C code source, for testing the memory in the system
Look at project options
Select Project->Project Options to display the current project setup.
Generate a design report file
To generate a design report file select Project->Generate and view design report. The design report will be stored in the report directory and can be viewed in a web browser (ETC_system.html).
Now it's time to add our own IP block, the Embedded Test Controller (ETC). That is the subject of the next part.
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Posted at 08:59 am by svenand
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FPGA design from scratch. Part 14
Putting it all together
Here is a simple overview of the simulation setup we are going to use when verifying the operation of the full system.
Memory Architecture
MicroBlaze is implemented with a Harvard memory architecture, i.e. instruction and data accesses are done in separate address spaces. Each address space has a 32 bit range (i.e. handles up to 4 gigabytes of instructions and data memory respectively). The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory. The latter is useful for software debugging. Both instruction and data interfaces of MicroBlaze are 32 bit wide and use big endian, bit-reversed format. MicroBlaze supports word, halfword, and byte accesses to data memory.
MicroBlaze does not separate data accesses to I/O and memory (i.e. it uses memory mapped I/O). The processor has up to three interfaces for memory accesses: Local Memory Bus (LMB), On-Chip Peripheral Bus (OPB), and Xilinx CacheLink (XCL). The LMB memory address range must not overlap with OPB or XCL ranges.
In our simulation setup we will use two memory modules, one for storing the control program (instruction memory) and one for storing data (ETC test program and test result). The Embedded Test Controller will be connected to the DOPB bus using a reserved address space.
We need help
We have to figure out how to connect everything and we need help. We will take a look at the Xilinix tutorial web page to see if we can find some help there. EDK 9.1 MicroBlaze Tutorial Virtex-4 seems like a good start. This tutorial demonstrates the process of creating and testing a MicroBlaze system design using the Embedded Development Kit (EDK). The tutorial contains these sections:
- System Requirements
- MicroBlaze System Description
- Tutorial Steps
The tutorial illustrates an Windows XP setup but we will use Ubuntu Linux.
Xilinx Platform Studio
The Xilinx Platform Studio (XPS) integrated development environment contains a wide variety of embedded tools, IP, libraries, wizards, and design generators to quickly facilitate the creation of a custom embedded platform. Sounds good, let's try it.
==> xps
$XILINX does not point to an iSE 8.1 installation
Press enter to close.
Software upgrade
Here is the answer to the question I asked in part 1. It is not possible to run different versions of ISE and EDK. After talking to Xilinx I decided to upgrade to ISE WebPACK 9.1i. Now we will find out how easy an upgrade is. First we will visit the Xilinx Download Center to download ISE WebPACK 9.1i. You will be asked for a Product ID and you must use the one specified. I was confused and changed it to the Product ID for my old ISE 8.1i WebPACK DVD and I was not able to download anything. To download ISE WebPACK 9.1i follow the instructions here. When I started the installation I got the following error message: Archive could not be located
Here is the answer from Xilinx's Answer Database #23669:
This message is normally seen when WebInstall cannot connect to the Xilinx Web site. Please verify that your proxy settings are correct. If you have chosen to use IE proxy settings on Windows, try setting the proxy address and port manually in the WebInstaller instead.
Additionally, you can work around the issue by:
- Downloading the Single File Download version of WebPACK.
or
- Ordering a WebPACK DVD for a nominal fee.
It was not as easy as we thought. Let's try the single file download instead (1.4GB). Two hours later the file WebPACK_SFD_91i.zip is downloaded.
- Create a temporary directory: mkdir temp
- cd temp
- unzip WebPACK_SFD_91i.zip
- Become root : sudo -i
- ./setup to start installation
 We will install ISE 9.1i in a new directory (xilinx91i) and leave the old ISE 8.2 installation until we know that the new one works.
 When the installation has finished we can remove the temp directory and the WebPACK_SFD_91.i.zip file. Before we when can start ISE 9.1 we have to change to the new setting.sh file in our .bashrc startup script. Now we are ready to start ISE.
==> cd /home/svenand/root/projects/ETC
==> ise &
There is no turning back. Let's click the yes button.
Downloading the latest Service Pack.
When we thought we were finished it is time to download the latest Service Pack. We have to visit the Xilinx Download Center again and download the file 9_1_03i_lin.zip (468MB).
One hour later the file 9_1_03i_lin.zip is downloaded.
- Create a temporary directory: mkdir temp
- cd temp
- unzip 9_1_03i_lin.zip
- Become root : sudo -i
- ./setup to start installation of Service Pack 3
The installation takes time. Be patient.
When the installation is finished we start ISE and see the following startup window. We have the latest version of ISE installed. It took us half a day to fix.
Upgrading from EDK 8.1 to EDK 9.1i
Here is the last part of our upgrading odyssey. Let's first find out what's new in EDK 9.1i. It looks like a lot of good stuff, especially the new version (v6.0) of MicroBlaze is interesting to us. The only problem is that I can't find a place to download EDK v9.1i. I have looked all over Xilinx's web page but nowhere I can find a download page for EDK 9.1i. Read more.
When I can't find EDK 9.1i I will try to download EDK 8.2 instead. When I click the EDK 8.2 download link I am transfered to the Electronic Fulfillment page. Here is what the electronic fulfillment is all about:
Electronic Fulfillment is an online software delivery service provided by Xilinx to in-maintenance ISE™ and EDK design tool customers. Xilinx Electronic Fulfillment provides you with: - Email notifications and online access to software.
- Personalized download site for in-warranty customers.
- 24x7 access with four secure file transfer options.
- Immediate access to your software and registration ID.
Electronic Fulfillment is a service provided to in-maintenance customers only; new customers are not eligible. Electronic Fulfillment does not replace regular product update shipments, which will still be mailed to all in-warranty customers. When I proceed to the Electronic Fulfillment Download Center I get the following message: We encountered a problem with your request. Our system records indicate you are not entitled to access the Xilinx Download at this time. This is a case for Xilinx WebCase. Before we can start using WebCase we have to register and get an approval from Xilinx. One working day later I get an email telling me I can start using WebCase. Here are the questions I am going to send to Xilinx:
1. I bought a PowerPC and MicroBlaze development kit DO-ML403-EDK-ISE-USB-EC from Avnet including the software ISE WebPACK and EDK 8.1. Shouldn't I be entitled to a one year in-maintenance for this product.
2. Are all software updates distributed on DVD. Why haven't I received the EDK 8.2 DVD.
3. When will EDK 9.1i be available from the download center.
4. How can I extend the in-maintenance period after one year.
I am sitting here waiting for an answer. I can't continue my design. I can't use IES 9.1 together with EDK 8.1 and I can't download a newer version of EDK. I am stuck.
All of a sudden (on Good Friday) I received the following email from Xilinx:
Dear Valued Customer,
Thank you for choosing the Xilinx Embedded Development Kit (EDK) as your embedded hardware and software development solution for Virtex(tm)-5, Virtex-4, Virtex-II Pro and Spartan(tm) Series PowerPC(tm) and MicroBlaze(tm) processing systems. Your Xilinx EDK 9.1i software is now available for download!*
The Xilinx EDK software is built from much the same core technology as the industry's favorite FPGA design environment, Xilinx ISE(tm). The graphical user interface for EDK, DesignVision Award winning Xilinx Platform Studio(tm)(XPS), is the technology that integrates all the processes from design entry to debug and verification, helping you quickly get started with your embedded designs.
Please be aware that EDK 9.1i requires a valid installation of ISE 9.1i, including ISE Service Pack 1, to function properly.
You can navigate to your XEF site through the Software Download Center at the following link:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
Thanks Shelly. Here we go again! Let's start the download. This time nothing stops us.
We will download EDK 9.1i
One hour later the file EDK91.zip is downloaded.
- Create a temporary directory: mkdir temp
- cd temp
- unzip EDK91.zip
- Become root : sudo -i
- cd /home/svenand/temp/EDK
- ./setup to start installation of the Linux version of EDK 9.1i
- When finished source the file install_dir/setting.sh
After installing new software versions of ISE and EDK we have to compile all simulation libraries again. See part 13 Compiling everything for instructions.
We are now ready to start using EDK 9.1i and the Xilinx Platform Studio. Read part 15 to find out more.
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Posted at 09:49 am by svenand
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