Generating a Verilog testbench

The process of building a testbench from scratch is a tedious and error prone task. We will use the Topi Top Code Generator to create a skeleton for our testbench. This will save us time and headache. Here we go:

Start the Topi program:
==> topi &



Open the Design Setup window. Setup->Design and specify a name for our design.



Next open the Pin Table setup window and select the ASIC/FPGA Pin Definition format.



Open the Pin Table window and select Import from VHDL entity from the Edit menu. We will now import information about all signals used in the top entity that the testbench must access.



This is what the Pin Table looks like after the import has finished.



Some of the signals names are very long and contain information that we don't need. We will add shorter instance names. To do that we open the Add Instance Names window Edit->Add Instance Names and copy the selected signal names to the Instance Name column.



We can now edit the instance names in the Pin Table editor and the result looks like this:



Everything is now setup for generating a Verilog testbench: Generate->Verilog Testbench.



When we click the run button this testbench setup file is generated. The whole process took less than 30 minutes. Topi saved us several hours work. This file will be included in the main body testbench file. The testbench is now complete and we only need a simple testcase to  start our first simulation. For more information about testbench design read part 7 of this story.

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Putting together a system simulation environment

This is probably the hardest part in our FPGA design from scratch journey. We have to do this job outside the Xilinx design environment and we can't expect much help from ISE or XPS.

Prerequisites

• Cadence Incisive Unified Simulator (IUS58) will be used
• The Mongoose Simulation Environment will be used to define the simulation setup
  
• All IP blocks are or will be compiled and storied in a simulation database
• All wrapper files and the top entity files will be compiled and stored in the database
• The verilog testbench template will be generated by the Topi Top Code Generator
• We have to find a verilog or VHDL model for the external SDRAM
  

To find out more about the Mongoose and Topi programs read the Zoo Design Platform documentation. Before we start let's see what help we can get from the Xilinx design flow. We will take a look in the EDK 9.1i Concepts, Tools and Techniques Guide, part 3 Introduction to Simulation in XPS.

Simulation database

All IP blocks, macro libraries, wrapper files and testbench files are compiled and stored in the simulation library. When we ran the program compedklib all Xilinx IPs and Xilinx macro libraries were compiled. See Part 13 (Compiling everything) for information on how to compile the EDK libraries. Here is a view of the simulation database:

Library Name	Directory Path	Description
unisim	../database/macrolib/unisim	Unit delay macro library
simprim	../database/macrolib/simprim	Timing simulation macro library
XilinxCoreLib	../database/macrolib/XilinxCoreLib	Xilinx Core Functions
edklib	../database/edklib/ip_name	Xilinx EDK IPs
userlib	../database/userlib/user_ip_name	User IPs
top	../database/top_design	Top entity, IP wrappers
testbench	../database/testbench/testcase_name	Testbench+testcases

The cds.lib file

The mapping of library names to physical file locations is done in the cds.lib file which must be referenced in the NCsim compile script. When we compiled the simulation libraries using compedklib this cds.lib was generated for us. This file contains all the available IPs and is overkill for us. Let's find out exactly which libraries we need and remove the unused ones. We will open the wrapper files and look for used libraries:

Wrapper file	Libarary Name	Design Document
clk90_inv_wrapper.vhd	util_vector_logic_v1_00_a
dcm_0_wrapper.vhd	dcm_module_v1_00_b
dcm_1_wrapper.vhd	dcm_module_v1_00_b	dcm_module.pdf
ddr_clk90_inv_wrapper.vhd	util_vector_logic_v1_00_a
ddr_sdram_64mx32_wrapper.vhd	opb_ddr_v2_00_c	opb_ddr.pdf
debug_module_wrapper.vhd	opb_mdm_v2_00_a	opb_mdm.pdf
dlmb_cntlr_wrapper.vhd	lmb_bram_if_cntlr_v2_00_a
dlmb_wrapper.vhd	lmb_v10_v1_00_a
ilmb_cntlr_wrapper.vhd	lmb_bram_if_cntlr_v2_00_a
ilmb_wrapper.vhd	lmb_v10_v1_00_a
leds_4bit_wrapper.vhd	opb_gpio_v3_01_b	opb_gpio.pdf
leds_positions_wrapper.vhd	opb_gpio_v3_01_b
lmb_bram_wrapper.vhd	lmb_bram_elaborate_v1_00_a
mb_opb_wrapper.vhd	opb_v20_v1_10_c	opb_v20.pdf
microblaze_0_wrapper.vhd	microblaze_v6_00_b
push_buttons_position_wrapper.vhd	opb_gpio_v3_01_b
rs232_uart_wrapper.vhd	opb_uartlite_v1_00_b	opb_uartlite.pdf
sysclk_inv_wrapper.vhd	util_vector_logic_v1_00_a

After removing all unused libraries our cds.lib file looks like this.

Compiling the ETC IP

From now on we will use the Mongoose simulation environment for our simulation setup. Here everything is setup to compile the Embedded Test Controller IP block. ETC_block_verilog_v1_00_a.def contains all the Verilog HDL files defining the ETC.

Here is the compilation script generated from Mongoose.

/* Ncvlog compilation control file generated from Mongoose 15.5 */
/* Generation date :  2007-04-15                                */
/* Generation time :  14:11:52                                  */

-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-work etc_v1_00_a
-file /home/svenand/root/projects/ETC/verification/designDefine/rtl/SYSTEM/etc/ETC_block_verilog_v1_00_a.def
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_block_verilog_v1_00_a.clog
-messages



This is the printout from the compilation.



The following line in the cds.lib file defines the name and the location of the compilation database.

define etc_v1_00_a  /home/svenand/root/projects/ETC/verification/database/ncsim/userlib/etc_v1_00_a

Compiling the block RAM

During the HDL generation a bram VHDL model (lmb_bram_elaborate.vhd) has been generated and stored in the directory: ../xps/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl. We will compile this model and store it in the simulation database:  $ETC_VERIFICATION/database/ncsim/userlib/lmb_bram_elaborate_v1_00_a using the library name lmb_bram_elaborate_v1_00_a.

Compiling Verilog wrappers

The ETC_system_verilog_v1_00_a.def contains all the Verilog wrappers. In our case only the ETC wrapper.



When compiling Verilog code you almost every time get a message telling you that some modules are missing timescale directives. The easiest way to fix this problem is to have a separate timescale file only containing a timescale directive. Like this: timescale 1ns/10ps. I call this file timescale.v and put it as the first file in the Verilog compile script.

Compiling VHDL wrappers

The ETC_system_vhdl_v1_00_a.def contains all the VHDL wrappers and the top entity.



This line in the cds.lib file defines the name and the location of the wrapper simulation database:

define top   /home/svenand/root/projects/ETC/verification/database/ncsim/top_design

Elaborating the design

We have now compiled the whole design and are ready to elaborate. Here is the elaboration script generated from Mongoose:

/* NCSIM elaboration control file generated from Mongoose 15.5       */
/* Generation date :  2007-04-22                                     */
/* Generation time :  04:57:52                                       */

-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_system_vhdl_v1_00_a.elog
-messages
-notimingchecks
-access +rwc
ETC_SYSTEM

Here is the result from the elaboration.



Warning messages

During the elaboration phase you will probably see a lot of warnings displayed in the terminal window. For example:

ncelab: *W,CUDEFB: default binding occurred for component instance (:ETC_system(STRUCTURE):etc_0) with verilog module (top.etc_0_wrapper:module).

and

ncelab: *W,CUNOTB: component instance is not fully bound (:ETC_system(STRUCTURE):iobuf_47) [File:ETC_system.vhd, Line:2075]

To find out more about these warnings we can execute the following commands:

==> nchelp ncelab CUDEFB

nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab/CUDEFB =
    No explicit binding mechanism was found for the component instance
    in the form of a configuration specification or a component
    declaration. Default binding occurred with an entity having a
    visible entity declaration which had the same simple name as that
    of the instantiated component.

I do remember overhearing something about this particular message.  Default binding is a perfectly normal thing to
do, and is standard VHDL.  However, some customer was trying to use a methodology of requiring explicit binding for
everything.  To enforce this, they wanted a warning produced whenever default binding was used instead.  As a result,
everyone else has to put up with a bunch of warnings that they didn't care about.
I think we can ignore this warning. We will add this line to the elaboration script: -nowarn CUDEFB

==> nchelp ncelab CUNOTB

nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab/CUNOTB =
    The (hierarchically) named component instance was not bound
    to an entity declaration along with a corresponding
    architecture body [5.2.1.1]. When this occurs, the component
    instantiation statement designated by the label in the
    hierarchical name shown has no effect [12.4.3]. This may have
    been due to a non-successful search through the binding search
    order. Following is the search order for all default bindings
    1) A design unit made visible with a USE clause visible to
       the architecture instantiating the component.
    2) A design unit made visible with a USE clause visible to
       the entity of the architecture instantiating the component.
    3) A design unit available in the library to which the
       component was compiled.
    4) A design unit in the WORK library.
    One of the above rules must provide for an entity to which the
    instance can be bound. Using other options to expand the search
    for default bindings can impact the ncelab performance. The user
    may first want to try modifying the design so that an entity can
    be found using the above stated rules. In most cases, it would
    imply adding appropriate USE clauses or compiling components into
    the same library to which the corresponding entity has been
    compiled.

This warning is a more serious one. We have things missing in our design. Here is the elaboration log file. We have to get rid of these warnings before we can continue.

I will ask Xilinx for help by creating a WebCase. The answer from Xilinx came the next day and was a reference  to the Answer Database #19446. In that example they used the option -lib_binding to ncelab. That was the answer to my problems.

Using the -lib_binding and -relax options

In the NC-VHDL Simulator Help manual we can read the following:

By default, the elaborator adheres to a strict interpretation of the VHDL LRM, which states that you must use LIBRARY statements with corresponding USE clauses in the source code to provide visibility to the declarative region that an unbound instance resides in. To bind component instances to compiled design units in the libraries, the elaborator:

1. Uses explicit binding indications
2. If there is no explicit binding indication, the elaborator tries to bind the component to in order:

• A design unit made visable with a USE clause given to the architecture instantiating the component.
• A design unit made visable with a USE clause given to the entity of the architecture instantiating the component.
• A design unit available in the library into whjich the component was compiled.
• A design unit in the work library

If a binding cannot be found, the elaborator generates an error (unbound ...).

To extend the binding rules there are two options we can use:
-lib_binding
-relax

We will use the -relax option which extends the set of binding rules with the following rules:

1. A design unit made visable with a LIBRARY clause given to the architecture instantiating the component (no corresponding USE clause).
2. A design unit made visable with a LIBRARY clause given to the entity of the architecture instantiating the component (no corresponding USE clause)
3. A design unit in a library defined in the cds.lib file. If a binding has not been found the elaborator opens the cds.lib file and searches all of the libraries that are defined.

Specify the timescale precision for VHDL

According to the IEEE 1076-1993 VHDL Language Reference Manual (Section 3.1.3.1), the primary unit of type TIME (1 femtosecond) is, by default, the resolution limit for type TIME. All simulations run in femtoseconds by default. Use the -vhdl_time_precision option to specify a secondary unit of type TIME as the resolution limit. Setting the timing resolution to a coarser value may increase simulation performance, as the simulator will not default to femtoseconds. We will use 1ps as our timing resolution.

-vhdl_time_precision 1ps

The modified elaboration script

/* NCSIM elaboration control file generated from Mongoose 15.5       */
/* Generation date :  2007-04-23                                     */
/* Generation time :  04:57:52                                       */

-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_system_vhdl_v1_00_a.elog
-messages
-notimingchecks
-nowarn CUDEFB
-relax
-vhdl_time_precision 1ps
-access +rwc
ETC_SYSTEM

Here is the elaboration  log file. No errors. Great news.


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Adding the ETC IP

The IP catalog tab shows all of the IPs that are available to use in an EDK project. To add the ETC IP:

• Bring the IP catalog tab forward
• Expand the Project Repository hierarchy
• Drag and drop the ETC into the System Assembly View or double click on the ETC.
• Expand the ETC instance
• Highlite the slave OPB connection (SOPB)
• Select the No Connection pull down menu and change it to mb_opb

Port connection

All OPB signals have already been connected to OPB bus. The remaining signals can be connected using the port view. We will make all signals external. Some input signals not used will be connected to ground and some unused output signals will be left unconnected.




Generate addresses

Select the Address filter to define addresses for the newly added ETC peripheral. The address can be assigned by entering the Base Address or the tool can assign an address. We will let the tool generate addresses:

• Change the size of the memory blocks to 1K and for the register map to 4.
• Click the Generate Addresses

A message in the console window will state that the address map has been generated successfully. The design is now ready to be implemented.

Mixed language design

All IP blocks from Xilinx are written in VHDL. The ETC IP is written in Verilog and therefor this design will be a mixed language design. The synthesis and simulation tools have no problems dealing with mixed language designs and hopefully this will not complicate our design job.

Set project options

Select Project->Project Options and click the HDL and Simulation tab. Because the majority of the design is in VHDL we will generate a VHDL top entity file. We will use NCSim for our simulations and we will allow mixed language behavioral files.





Generate the system netlist

We can now generate the system netlist. Click Hardware->Generate Netlist. The generation starts and returns with the following error message:

ERROR:MDT - INST:ETC_0 PORT:I_OPB_BE CONNECTOR:mb_opb_OPB_BE -
   /home/svenand/root/projects/ETC/xps/pcores/ETC_v1_00_a/data/ETC_v2_1_0.mpd
   line 43 - calculated index is out of signal VEC range of [0:3]

Completion time: 1.00 seconds

ERROR:MDT - platgen failed with errors!

make:
*** [implementation/microblaze_0_wrapper.ngc] Error 2

Done!

Let's open the ETC_v2_1_o.mpd file and figure out what the problem is. The OPB_BE signal is a four bit bus and not a one bit signal as I thought. If we add VEC [0:3] to the OPB_BE definition this problem will be fixed and we can rerun the netlist generation.

This is incredible. The whole netlist generation runs without any problems and it took less than 10 minutes on my MacBook using a virtual machine (Parallels Desktop) and Ubuntu Linux. Here is the log file and here are all the warnings.

What happend during the netlist generation

When we start the netlist generation the following command is executed: platgen -p xc4vfx12ff668-10 -lang vhdl   ETC_system.mhs


                                                                                                 (Courtesy of Xilinx)

Hardware generation is accomplished with the Platform Generator (Platgen) tool. Platgen constructs the programmable system on a chip in the form of hardware netlists (HDL and implementation netlist files). Platgen creates a hardware platform using the Microprocessor Hardware Specification (MHS) file as input. In addition to netlist files in various formats such as NGC and EDIF, Platgen creates support files for downstream tools and top-level HDL wrappers to allow you to add other components to the automatically generated hardware platform. Read more about Platgen in the Embedded Systems Tools Guide  (chapter 2).

During the Platgen run the following directories have been created and filled with files.

• hdl
• implementation
• synthesis

The HDL directory contains all the HDL verilog and VHDL wrapper files that instantiates the IP blocks used in the design. The VHDL IPs always have VHDL wrappers and the Verilog IPs have Verilog wrappers. The top module ETC_system.vhd is a VHDL entity because we specified a VHDL netlist to be generated.



The implementation directory holds all the NGC files. The NGC file is a netlist that contains logical design data and constraints. This file replaces both EDIF and Netlist Constraints (NCF) files.




The synthesis directory holds all synthesis scripts used when running the syntesis tool XST.




We are now ready to program the FPGA on the evaluation board and start debugging the design. But before we do that we will setup a simulation environment and simulate the whole design. I am an old ASIC designer. Always simulate before implement.

Generate simulation HDL files

We will try the Xilinx HDL simulation environment. To generate the simulation setup goto the Simulation menu and select Generate Simulation HDL Files. The following script will start: make -f ETC_system.make simmodel. When the script has finished a new directory called simulation has been created.



Here is the simgen log file.

Why simulate an embedded design

• Using simulation, you don't have to wait for hardware to be complete before testing your software. The result: facilitated software development, which allows you meet more aggressive project deadlines.
• Simulation provides insight into the internal workings of your system. Signals and register values are more accessible in a simulated system than they are once a design is in hardware.
• Simulation also allows you complete control of your system. Conditions that may be difficult to create in a hardware setting are relatively easy to simulate.
  

Running a simulation in XPS

We will take these steps to start a simulation using NCSIM:

1. cd /home/svenand/root/projects/ETC/xps/simulation/behavioral
2. chmod 777 ETC_system.sh (make script executable)
   
3. chmod 777 ETC_system_setup.sh
4. Edit the ETC_system_setup.sh file and change -lib_binding to -relax
   
5. Start the simulation script: ./ETC_system_setup.sh
   

Here are instructions from Xilinx on how to use NCSIM.

Read chapter 7 in the EDK Concepts, Tools, and Techniques guide to find out more about simulating our design. Before we can start our simulation we need to write a simple software application that will run in our system. We will come back to simulation when we have finished this task.

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IP creation overview

Any piece of IP you create must be compliant with the system that is in place. To ensure compliance, the following must occur:

1. The interface required by your IP must be determined.
   The bus to which your custom peripheral will attach must be identified. For example:
   a. Processor Local Bus (PLB). The PLB provides a high-speed interface between the processor and high-performance peripherals.
   b. On-chip Peripheral Bus (OPB). The OPB allows processor access to low-speed, low-performance system resources.
2. Functionality must be implemented and verified.
   Your custom functionality must be implemented and verified, with awareness that common functionality available from the EDK peripherals library can be reused. Your
   stand-alone core must be verified. Isolating the core ensures easier debug in the future.
3. The IP must be imported to EDK.
   Your peripheral must be copied to an EDK-appropriate directory, and the Platform
   Specification Format (PSF) interface files (MPD and PAO) must be created, so other
   EDK tools can recognize your peripheral.
4. Your peripheral must be added to the processor system created in XPS.
   

Create or import an user peripheral

One of the key advantages of building an embedded system in an FPGA is the ability to include customer IP and interface that IP to the processor. To start the Create and Import Peripheral Wizard select Hardware->Create or Import Peripheral.



Click the More Info button for more information. We will import an existing peripheral.






We will call our peripheral ETC (the name of the top module) and add a version to the name.




The peripheral is made up of Verilog files (.v).



We will use the ISE project file to define the Verilog source code.



Here are all the verilog source files.



The ETC peripheral will operate as an OPB slave (SOPB) and the OPB interface is already designed and verified. The On-chip Peripheral Bus (OPB) is an IBM standard and is also used in the Power PC processor.




The wizard tries to map the ETC interface names to the standard naming convention for OPB. All the names that don't match have to be manually inserted.




It seems like we are missing some of the optional OPB signals. I have to add these signals to the top module ETC.v.  I will add the missing pins and also some parameter statements defining register and memory address ranges. Like this:

parameter REGISTER_BASE_ADDR    = 32'h2000;
parameter REGISTER_HIGH_ADDR    = 32'h200c;
parameter MEM_BANK0_BASE_ADDR   = 32'h0;
parameter MEM_BANK0_HIGH_ADDR   = 32'hffc;
parameter MEM_BANK1_BASE_ADDR   = 32'h1000;
parameter MEM_BANK1_HIGH_ADDR   = 32'h1ffc;

In this window we have to select the right parameters defining the address range for registers and memory banks.




Here we define the interrupt signal and the operation of the interrupt.




Congratulations! We have added our peripheral to the current XPS project. Good work.





Here are all files in the pcores directory.



File description

XPS provides an interactive development environment that allows you to specify all aspects of your hardware platform. XPS maintains your hardware platform description in a high-level form, known as the Microprocessor Hardware Specification (MHS) file. The MHS, an editable text file, is the principal source file representing the hardware component of your embedded system. XPS synthesizes the MHS source file into Hardware Description Language (HDL) netlists ready for FPGA place and route.

The MHS File

The MHS file is integral to your design process. It contains all peripherals along with their parameters. The MHS file defines the configuration of the embedded processor system and includes information on the bus architecture, peripherals, processor, connectivity, and address space. For more detailed information on the MHS file, refer to the "Microprocessor Hardware Specification (MHS)" chapter of the Platform Specification Format Reference Manual, available at http://www.xilinx.com/ise/embedded/edk_docs.htm.

XPS Project Files

Here are more information about the XPS project files used.

Xilinx IP center

There are many IP blocks available from Xilinx. Find out more in the Xilinx IP center.


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EDK is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx FPGA device. To run EDK, ISE must be installed as well. Think of it as an umbrella covering all things related to embedded processor systems and their design.

Xilinx Platform Studio (XPS)

XPS is the development environment or GUI used for designing the hardware portion of your embedded processor system.

Software Development Kit (SDK)

Platform Studio SDK is an integrated development environment, complimentary to XPS, that is used for C/C++ embedded software application creation and verification. SDK is built on the Eclipse™ open-source framework. Because many other software development tools are being built on the Eclipse infrastructure, this software development tool might already be familiar to you or members of your design team.

EDK includes other elements such as:
•    Hardware IP for the Xilinx embedded processors
•    Drivers and libraries for embedded software development
•    GNU Compiler and debugger for C/C++ software development targeting the MicroBlaze™ and PowerPC™ processors
•    Documentation
•    Sample projects

The utilities provided with EDK are designed to assist in all phases of the embedded design process.



                                                                                                                                         (Courtesy of Xilinx)
Using Xilinx Platform Studio

This is going to be fun. Let's start xps. We will use the EDK 9.1 MicroBlaze Tutorial in Virtex-4 and the EDK 9.1i Concepts, Tools and Techniques Guide (CTTG) as we go along.

For more documents go to the Xilinx Platform Studio Documentation.

XPS Design checklist

This page provides a summary of all necessary steps and commonly used optional steps to complete an embedded processor system design.

==> cd $ETC_PROJECT
==> xps&
[1] 4463
==>
Xilinx Platform Studio
Xilinx EDK 9.1 Build EDK_J.19
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Launching XPS GUI...
Overriding Xilinx file <mdtgui/images/xps-splash-screen.bmp> with local file
</home/svenand/cad/edk91i/data/mdtgui/images/xps-splash-screen.bmp>




We will create a new project using the Base System Builder wizard (see chapter 2 in CTTG).



First we have to create a new top-level project file (ETC_system.xmp). A Xilinx Microprocessor Project (XMP) file is the top-level file description of the embedded system under development. All XPS project information is saved in the XMP file, including the location of the Microprocessor Hardware Specification (MHS) and Microprocessor  Software Specification (MSS) files. The MHS and MSS files are described in detail later.




When I click the OK button I get the following error message:

ERROR:PersonalityModule:7 - Unable to open Xilinx data file for Vendor/Device
   Module "qrvirtex2".  Please make sure that it has been correctly installed
   before continuing.

I just realized there is a service pack 1 available for EDK 9.1i. I will download this sevice pack and see if it fixes the problem. The service pack fixed the problem. Sorry to bother you Xilinx.



We would like to create a new design for the ML403 evaluation board.



We will use the MicroBlaze soft processor.



We will use the 100MHz system clock available on the board, an active low reset signal and we will have an on-chip debug module. We don't need memory caches and a floating point unit.



In the next four pages we will select the peripherals to use:



We will change the baudrate to 57600 at a later stage.









The UART will be used for the serial communication between the board and the terminal.



Here are more information about available IO devices:

IO Device	Xilinx Name	Description
RS232 UART	UARTLITE	opb_uartlite.pdf
IIC EEPROM	IIC_EEPROM	xapp979.pdf
CompactFlash	SysACE_CompactFlash	opb_sysace.pdf
USB	Cypress_USB	xapp925.pdf
DDR SDRAM	DDR_SDRAM_64Mx32	DDR/DDR2 SDRAM
Ethernet MAC	Ethernet_MAC	ug074.pdf
SRAM	SRAM_256Kx32	Memory corner
Flash memory	FLASH_2Mx32

When we click the Generate button, we will start the generation of our embedded system.




We have now put together our embedded system. We can always go back and add or remove IO interfaces at a later stage. Here is the file tree generated from XPS.

• blkdiagram - contains the blockdiagram of our system that can be displayed in a web browser (ETC_system.html).
  
• data - contains the UCF (user constraints file) for the target board
• etc - contains system settings for JTAG configuration on the board that is used when downloading the bit file and the default parameters that are passed to the ISE tools
• pcores - is empty right now, but is utilized for custom peripherals
• TestApp_Memory - contains a user application in C code source, for testing the memory in the system

Look at project options

Select Project->Project Options to display the current project setup.



Generate a design report file

To generate a design report file select Project->Generate and view design report. The design report will be stored in the report directory and can be viewed in a web browser (ETC_system.html).


Now it's time to add our own IP block, the Embedded Test Controller (ETC). That is the subject of the next part.


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Putting it all together

Here is a simple overview of the simulation setup we are going to use when verifying the operation of the full system.




Memory Architecture

MicroBlaze is implemented with a Harvard memory architecture, i.e. instruction and data accesses are done in separate address spaces. Each address space has a 32 bit range (i.e. handles up to 4 gigabytes of instructions and data memory respectively). The instruction and data memory ranges can be made to overlap by mapping them both to the same physical memory. The latter is useful for software debugging. Both instruction and data interfaces of MicroBlaze are 32 bit wide and use big endian, bit-reversed format. MicroBlaze supports word, halfword, and byte accesses to data memory.

MicroBlaze does not separate data accesses to I/O and memory (i.e. it uses memory mapped I/O). The processor has up to three interfaces for memory accesses: Local Memory Bus (LMB), On-Chip Peripheral Bus (OPB), and Xilinx CacheLink (XCL). The LMB memory address range must not overlap with OPB or XCL ranges.

In our simulation setup we will use two memory modules, one for storing the control program (instruction memory) and one for storing data (ETC test program and test result). The Embedded Test Controller will be connected to the DOPB bus using a reserved address space.

We need help

We have to figure out how to connect everything and we need help. We will take a look at the Xilinix tutorial web page to see if we can find some help there. EDK 9.1 MicroBlaze Tutorial Virtex-4 seems like a good start. This tutorial demonstrates the process of creating and testing a MicroBlaze system design using the Embedded Development Kit (EDK). The tutorial contains these sections:

• System Requirements
• MicroBlaze System Description
• Tutorial Steps

The tutorial illustrates an Windows XP setup but we will use Ubuntu Linux.

Xilinx Platform Studio

The Xilinx Platform Studio (XPS) integrated development environment contains a wide variety of embedded tools, IP, libraries, wizards, and design generators to quickly facilitate the creation of a custom embedded platform. Sounds good, let's try it.

==> xps
$XILINX does not point to an iSE 8.1 installation

Press enter to close.

Software upgrade

Here is the answer to the question I asked in part 1. It is not possible to run different versions of ISE and EDK. After talking to Xilinx I decided to upgrade to ISE WebPACK 9.1i. Now we will find out how easy an upgrade is. First we will visit the  Xilinx Download Center to download ISE WebPACK 9.1i. You will be asked for a Product ID and you must use the one specified. I was confused and changed it to the Product ID for my old ISE 8.1i WebPACK DVD and I was not able to download anything. To download ISE WebPACK 9.1i follow the instructions here. When I started the installation I got the following error message: Archive could not be located

Here is the answer from Xilinx's Answer Database #23669:

This message is normally seen when WebInstall cannot connect to the Xilinx Web site. Please verify that your proxy settings are correct. If you have chosen to use IE proxy settings on Windows, try setting the proxy address and port manually in the WebInstaller instead.
Additionally, you can work around the issue by:
- Downloading the Single File Download version of WebPACK.
or
- Ordering a WebPACK DVD for a nominal fee.

It was not as easy as we thought. Let's try the single file download instead (1.4GB). Two hours later the file WebPACK_SFD_91i.zip is downloaded.

1. Create a temporary directory: mkdir temp
2. cd temp
3. unzip WebPACK_SFD_91i.zip
4. Become root : sudo -i
   
5. ./setup to start installation

We will install ISE 9.1i in a new directory (xilinx91i) and leave the old ISE 8.2 installation until we know that the new one works.



When the installation has finished we can remove the temp directory and the WebPACK_SFD_91.i.zip file. Before we when can start ISE 9.1 we have to change to the new setting.sh file in our .bashrc startup script. Now we are ready to start ISE.

==> cd /home/svenand/root/projects/ETC
==> ise &



There is no turning back. Let's click the yes button.

Downloading the latest Service Pack.

When we thought we were finished it is time to download the latest Service Pack. We have to visit the Xilinx Download Center again and download the file 9_1_03i_lin.zip (468MB).

One hour later the file 9_1_03i_lin.zip is downloaded.

1. Create a temporary directory: mkdir temp
2. cd temp
3. unzip 9_1_03i_lin.zip
4. Become root : sudo -i
   
5. ./setup to start installation of Service Pack 3
   

The installation takes time. Be patient.




When the installation is finished we start ISE and see the following startup window. We have the latest version of ISE installed. It took us half a day to fix.




Upgrading from EDK 8.1 to EDK 9.1i

Here is the last part of our upgrading odyssey. Let's first find out what's new in EDK 9.1i. It looks like a lot of good stuff, especially the new version (v6.0) of MicroBlaze is interesting to us. The only problem is that I can't find a place to download EDK v9.1i. I have looked all over Xilinx's web page but nowhere I can find a download page for EDK 9.1i. Read more.

When I can't find EDK 9.1i I will try to download EDK 8.2 instead. When I click the EDK 8.2 download link I am transfered to the Electronic Fulfillment page. Here is what the electronic fulfillment is all about:

Electronic Fulfillment is an online software delivery service provided by Xilinx to in-maintenance ISE™ and EDK design tool customers. Xilinx Electronic Fulfillment provides you with:

• Email notifications and online access to software.
• Personalized download site for in-warranty customers.
• 24x7 access with four secure file transfer options.
• Immediate access to your software and registration ID.

Electronic Fulfillment is a service provided to in-maintenance customers only; new customers are not eligible. Electronic Fulfillment does not replace regular product update shipments, which will still be mailed to all in-warranty customers. When I proceed to the Electronic Fulfillment Download Center I get the following message:

We encountered a problem with your request. Our system records indicate you are not entitled to access the Xilinx Download at this time.

This is a case for Xilinx WebCase. Before we can start using WebCase we have to register and get an approval from Xilinx. One working day later I get an email telling me I can start using WebCase. Here are the questions I am going to send to Xilinx:

1. I bought a PowerPC and MicroBlaze development kit DO-ML403-EDK-ISE-USB-EC from Avnet including the software ISE WebPACK and EDK 8.1. Shouldn't I be entitled to a one year in-maintenance for this product.

2. Are all software updates distributed on DVD. Why haven't I received the EDK 8.2 DVD.

3. When will EDK 9.1i be available from the download center.

4. How can I extend the in-maintenance period after one year.

I am sitting here waiting for an answer. I can't continue my design. I can't use IES 9.1 together with EDK 8.1 and I can't download a newer version of EDK. I am stuck.

All of a sudden (on Good Friday) I received the following email from Xilinx:

Dear Valued Customer,

Thank you for choosing the Xilinx Embedded Development Kit (EDK) as your embedded hardware and software development solution for Virtex(tm)-5, Virtex-4, Virtex-II Pro and Spartan(tm) Series PowerPC(tm) and MicroBlaze(tm) processing systems. Your Xilinx EDK 9.1i software is now available for download!*

The Xilinx EDK software is built from much the same core technology as the industry's favorite FPGA design environment, Xilinx ISE(tm). The graphical user interface for EDK, DesignVision Award winning Xilinx Platform Studio(tm)(XPS), is the technology that integrates all the processes from design entry to debug and verification, helping you quickly get started with your embedded designs.

Please be aware that EDK 9.1i requires a valid installation of ISE 9.1i, including ISE Service Pack 1, to function properly.

You can navigate to your XEF site through the Software Download Center at the following link:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

Thanks Shelly. Here we go again! Let's start the download. This time nothing stops us.




We will download EDK 9.1i



One hour later the file EDK91.zip is downloaded.

1. Create a temporary directory: mkdir temp
2. cd temp
3. unzip EDK91.zip
4. Become root : sudo -i
5. cd /home/svenand/temp/EDK
   
6. ./setup to start installation of the Linux version of EDK 9.1i
7. When finished source the file install_dir/setting.sh
   

After installing new software versions of ISE and EDK we have to compile all simulation libraries again. See part 13 Compiling everything for instructions.

We are now ready to start using EDK 9.1i and the Xilinx Platform Studio. Read part 15 to find out more.

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Links to information in English

• Al's world of ice skating
• Blades of glory
• English skating dictionary
• Flying feet
• Ice (Wikipedia)
• Ice skating (Wikipedia)
• Ice skating tours on natural ice in Sweden
• Kite skiing and kite skating
• Linköpings Långfärdsskridskoklubb
• Long distance ice skating
• Marathon skating is no longer a warm weather event
• Nordic skating
• Nordic skating: Top destinations
• NordicSkating.org
• On thick ice
• Skating the Swedish way
• The best natural ice in the world
• The rush of black ice
• Timo Salmi's long distance skating page
• Tour skating (Wikipedia)
• Wild skating on frozen lakes & rivers
• Wild skating takes the sport out of the rink

Links to information in Swedish

• Diskussionsforum långfärdsskridsko
• Isplanket
• Iskurser och långfärdsskridsko
• Kristers hemsida
• Långfärdsskridskoåkning
• Långfärdsåkning med lös häl
• Packlista
• Plogade och konstfrusna banor
• Skridskonätet
• Slipning (bryning) av långfärdsskridskor
• Smartson test av långfärdskridskor
• Snabelslash (Bo Gustavsson)
• Stockholm Skridskoseglarklubb (Wikipedia)
• Svenska Skridskoförbundet
• Utrustningstips
• Utsidan

Ice

• Ishandboken
• Is på dekis
• Praktisk isbedömning för långfärdsskridskoåkare
• Situationsanpassad isbedömning
• SSSK islära
• Think ice

Tour arrangements (guided tours)

• Activities in Sweden
• Baltic Ice Safaris
• Naturguiden
• Nature Travels
• Puls
• Swedish Skating Adventure
• Sweden skate & ski tour

Wild skating clubs in Sweden

• Skridskonätet
• Bråvallaskrinnarna
• Friluftsfrämjandet
• Friskis&Svettis
• Göteborgs Långfärdsskridskoklubb
• Linköpings Långfärdsskridskoklubb
• Långfärdsskrinnare i sydöst
• Långfärdsskridsko runt Siljan
• Långfärdsskridsko i Sundsvall
• Långfärdsskridsko i Västerås
• Mora Orsa Skating
• Stockholms Skridskoseglarklubb
• Stockholmsalliansen
• Södra Vätterns Långfärdsskridsko
• Vänerskridsko
• Östhammars Skrinnare

Wild skating around the world

• Tour skating clubs
• Baikal wild skating tour
• Baikal
• Canada
• Connecticut
• First Ice, Nova Scotia Canada
• HLSK Holland
• Mongolia
• Mono Lake California
• Montshire Skating Club of Vermont & New Hampshire
• Skating in the Czech Republic
• Weissensee Austria
• Wild skating on Lake Willoughby

Races

• Bothnia Loppet
• Finland Ice Marathon
• Järnrännet
• Marathon Skating International
• Ornäsrännet
• Runn Dagarna
• Skating Marathon of Kalevipoeg
• Sollentunaloppet
• Spitz Sylvan Lake Ice Marathon Alberta, Canada
• Storsjörännet, Östersund
• Vikingarännet

Links to equipment manufacturer

• Alpina
• Bergans of Norway
• Crispi
• Fjällräven
• Haglöfs
• Lundhags
• Pikmakarn
• Rottefella
• Salomon Nordic
• Skyllermarks
• Zandstra Sport
• Vaude

Links to outdoor equipment stores in Sweden

• addnature.com
• friluft.se
• GetOut AB
• KG Jonsson Sport&Outdoor
• Naturkompaniet
• outnet.se
• Playground
• Skridskospecialisten
• Skidsport
• Slipspecialisten
• Slipstället Cykelstallet

Equipment rentals in Stockholm

• Hellasgården
• KG Jonsson Sport&Outdoor
• Playground
• Slipstället Cykelstallet

Maps

• Allväderskartor
• Kartcentrum
• Lantmäteriet Kartbutiken
• Utekartan

Weather forecasts

• AccuWeather
• Aftonbladet
• ICM Weather Service
• NOAA ARL
• Swedish Meteorological and Hydrological Institute SMHI
• The Weather Channel
• Wetterzentrale
• yr.no

Top

Books

• Friluftsliv i Sverige
• Is : en fotobok för skridskoåkare och andra isfantaster
• Iskultur i skärgården
• Långfärdsåkning på skridskor
• När isen lockar
• På långfärdsskridsko
• På skridskor i Östra Svealand
• Stockholms skridskoseglarklubb 1901 - 2001

Magazines

• Outside
• Utemagasinet

Photos

• David Thyberg
• LLK photo album
• Skating photos Mark Harris
• Today's tour
• Tour skating in Finland
• Tour skating in Norway
• Tour skating pool
• Ulf Haase

Films

• Sven Rudberg
• Öjen 070113

Videos (YouTube)

• Biskopsöfjärden - Tour Skating (Map)
• Floatin' Downstream
• Gräsö - Tour Skating
• Superb Skating at Singö  (Map)
• Svenska Högarna - Tour Skating (Map)
• Windy ice skating

Top

After the successful porting of all my Zoo Design Platform programs from Solaris Unix to Ubuntu Linux I am ready for a new challenge; porting some of my programs from Linux to Mac OS X. Mac OS X is my favorite OS and having my programs running in Mac OS X would be a great thing. Before we can run a Linux or Unix program in Mac OS X we have to make sure we have the X11 software installed.

X11 for Mac OS X

X11 for Mac OS X offers a complete X Window System implementation for running X11-based applications on Mac OS X. The X11 program is part of the normal Mac OS X 10.5 installation and can be found in the /Application/Utilities directory. After starting the X11 program we can start the terminal program xterm from the Program menu.




From the xterm window it is now possible to run almost any X11 compliant program compiled for Max OS X.

Xcode development environment

To compile and link programs we have to install the Xcode development environment. The Xcode package includes the GNU Compiler Collection (GCC) and other useful tools. You can download the Xcode package from Apple's developer web site. You must be an Apple Developer Connection member to download Xcode. Online membership is free. If you have another account at Apple, enter your existing username (Apple ID) and password in the ADC Member Log In area and complete your membership registration. Or sign up today for your ADC online membership. The latest version of Xcode is 3.1.3 and it requires Mac OS X 10.5 The package is almost 1GB so you better look for a high-speed connection. The package will be installed in the Developer folder in Macintosh HD.

Get the source code

I will start by copying the Cobra source code to my MacBook.

Cobra.info              Cobra_globals.h         Cobra_stubs.c           Make_linux
Cobra_define.h          Cobra_include.h         Cobra_tree.c            Make_macosx
Cobra_find_mac.c        Cobra_main.c            Cobra_ui.c              RunCobra
Cobra_function.c        Cobra_popup.c           Cobra_ui.h             

Header files

Header files serve two purposes.

• System header files declare the interfaces to parts of the operating system. You include them in your program to supply the definitions and declarations you need to invoke system calls and libraries.
• Your own header files contain declarations for interfaces between the source files of your program. Each time you have a group of related declarations and macro definitions all or most of which are needed in several different source files, it is a good idea to create a header file for them.

The header files for the xview, olgx and slingshot library functions must be included in the compilation. The xview header files can be downloaded from Physionet. The slingshot header files can be downloaded from this site.

This screen plot shows the /usr/openwin directory which is the default installation directory for the header files used in the SUN OS. This is where I put the header fils.



Makefile

I use a makefile (Make_macosx) to compile and build the program. The following command is used to run the makefile:  make -f Make_macosx

Shared libraries

Cobra makes use of some shared libraries that are not part of the normal X11 installation. These libraries have to be compiled for Mac OS X. These libraries will be linked to the Cobra program when it is starting. The libraries can be downloaded from here. They are included in the file cobra_9.9macosx.tar.gz.

Library Name	Description
libxview.dylib	The XView toolkit
libolgx.dylib	The OLGX toolkit (used by XView)
libsspkg.dylib	The Slingshot toolkit

I add the following command in the startup script to tell the program where to find the shared libraries: export DYLD_LIBRARY_PATH=$INSTALL_DIR/libraries

Running Cobra

I compiled and linked the Cobra program and here it runs on my MacBook. I am happy as a child.



Download Cobra

You can download and try the Cobra program yourself. Here is the download site.

Running X11 applications in Mac OS X

You can read more about configuring and running X11 applications in Mac OS X here. xterm provides a significant advantage: when you start an xterm session, it sets up the X11 environment for you. You can then easily run X11 applications from the command-line. By contrast, in Terminal you need to run the /usr/bin/open-x11 script to set up the X11 environment and launch X11 applications, as shown here: /usr/bin/open-x11 ./cobra &

Launching Aqua apps from the Terminal window

One way to launch Aqua applications from the Terminal or xterm windows is the open command. To start Firefox use the following command:
open /Applications/firefox.app or
open -a /Application/firefox.app http://www.google.com


The Fink project

The Fink project wants to bring the full world of Unix Open Source software to Darwin and Mac OS X. We modify Unix software so that it compiles and runs on Mac OS X ("port" it) and make it available for download as a coherent distribution. Fink uses Debian tools like dpkg and apt-get to provide powerful binary package management. You can choose whether you want to download precompiled binary packages or build everything from source. Here is a good description of how to run X11 on Darwin and Mac OS X.


Useful links

• Unix FAQ

Top

A
Assembly code and hex machine code
B
Bitstream generation
Bitstream, downloading

C
Cable drivers, installing
C application program, creating
C header files
C prgram examples
C-program, access ETC registers
Configurable Logic Block (CLB)

D
Design object
Digital Clock Manager (DCM)
DDR SDRAM, adding
Download program

E
EDK 8.1 to EDK 9.1 upgrading
Embedded Development Kit (EDK) installation
Embedded Test Controller (ETC), adding
Ethernet MAC

F
Field Programmable Gate Array (FPGA)
Floorplanner, Xilinx

G
Generating memory blocks
Gmake
GNU Compiler Tools (GCC)

H
Hardware setup
HDL Analysis and Lint (HAL)
Hello World, program
Hello World, finished

I
iMPACT, FPGA configuration tool
iMPACT, using
Implementing the hardware platform
Introduction
Integrated Software Environment (ISE)
IP center, Xilinx
IP, import or create

J
JTAG, IEEE 1149.1

K

L
Learning-by-doing
Let's get started
LCD display controller, adding
LCD driver, simulation
LCD driver, timing
Libgen
Logic cell

M
MicroBlaze soft processor
MicroBlaze program execution simulation
ML403 evaluation board
ML403 Reference Systems on the CD
Mongoose
Mongoose setup
Mongoose user buttons

N
Netlist generation (ETC)
NCSIM, cds.lib file
NCSIM, compiling ETC
NCSIM, elaboration
NCSIM, first simulation
NCSIM system simulation

O
On-chip Peripheral Bus (OPB), debugging

P
PACE, Pin Area Constraints Editor
Parallels Desktop
Pin assingment closure
Pin constraints, specifying
PlanAhead, Xilinx
Power calculations
PowerPC processor block
Program disassembly

Q

R
Register software
Regression testing
Running a program

S
Service pack, downloading
Simgen
Simulation, compiling everything
Simulation environment
Simulation debugging
Simulation debugging, MicroBlaze reset
Simulation, generate HDL files
Simulation libraries
Simulation process
Simulating the design
Software Development Kit (SDK), using
Software installation (ISE)
Software setup
Synthesis contraints, adding
Synthesizing the design
System simulations
System simualtion, DDR SDRAM controller
System simualtion, LED display and push buttons
System simualtion, Embedded Test Controller

T
Testbench design
Testbench body
Timing constraints (synthesis)
Timing constraints, implementation
Topi, Top Code Generator, using

U
Using ISE

V
Verilog testbench generation
Verilog testcase
Verilog task files
Virtex-4 FPGA family
VMware Fusion

W

X
XFlow
Xilinx Microprocessor Debugger (XMD)
Xilinx Platform Studio (XPS)
XPS, using
Xilinx software upgrade
XPower
XtremeDSP Slices

Y

Z

Top