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Tour skating in Sweden and around the world
What's New
2009-03-06 Bothnialoppet will take place Saturday the 7th March.
2009-02-11 Vikingarännet will take place on Sunday the 15th February.
2009-01-04 The winter is here. Today it is -12 C outside my window. All the lakes around Stockholm are now covered with thick ice. Yesterday I made a skating tour together with SSSK from Skarholmen Uppsala to Sigtuna. Here is the tour track recorded on my Garmin Forerunner 301.
2008-04-19 Let's forget this winter a look forward to the next winter. Hopefully much colder and much more ice.
Wild skating on frozen water around Stockholm
Every winter hundreds of lakes around Stockholm will freeze and if there is no snow on the ice this is a perfect surface for skating. February 10th, 2007 was one of those days. The last week had been cold, below -10 C most of the time and no snow had fallen. On Friday evening I called and listened to the answering machine at SSSK (Stockholms Skridskoseglarklubb) to find out about the ice conditions. It said that Lake Mälaren had frozen and that the ice looked like a mirror. You can also find out about ice conditions and coming tours from Isnytt (SSSK members only).
Every weekend during the winter if there is skateable ice, SSSK will arrange tours to the best places for skating around Stockholm. Many times you can use public transportation to get you to the starting point and home from the finish point. When skating in more remote places they will arrange bus transportation. These tours are only open to members but you can join as guest if know someone who is a member.
SSSK
Stockholms skridskoseglarklubb, SSSK, founded in 1901, is the largest and oldest skating association in Scandinavia and the largest skating organization outside The Netherlands. It has about 13,000 members. In the beginning, ice skate sailing dominated, but today tour skating is the main activity. Here is more information about SSSK.
Other tour organizers
You can also go wild skating together with Friskis&Svettis and Friluftsfrämjandet or you can organize a private tour together with friends. Here you will find more tour arrangements.
Wild skating
Wild skating on ice (also called trip skating, tour skating, long-distance skating or Nordic skating, in Swedish "långfärdsskridskoåkning") is now a popular sport in Sweden. Maybe the best conditions in the world are those found around Stockholm with a considerable number of both large and small lakes plus the extensive nearby archipelago in the Baltic Sea. The smallest lakes may freeze normally in November, although the main season usually starts in December and lasts until March or April. Snow is not a major problem in this part of Sweden because in cold periods there are often areas of unfrozen water that can still freeze, and in mild periods the snow melts down to slush in the daytime and freezes to ice during the night. Watch this video (Ice is nice) to find out what it is all about.
Links
I have collected a number of links to informations about wild skating. Photos films and videos
Here are links showing you the beauty of wild skating.
 Tour day
Saturday morning at 9 am all the tour skaters meet at Centralen to take a commuter train to Kungsängen a suburb North West of Stockholm close to Lake Mälaren. From the train station at Kungsängen there is a short walk to the lake and the ice. At 10 am there are about 185 people on the ice getting ready for the tour. Now it's time to decide which group to join. You can choose between 5 groups. Group 1 is for the strongest and fittest skaters. They will cover more than 100km during one day. I went for group 3 and we gather around our tour leader for a last safety check before we leave. We are 16 expectant skaters in my group. Before we start our tour let's talk about safety.
Before you can join SSSK as a member you have to attend the "Welcome Program" where you will be introduced to SSSK and learn about ice conditions and how to skate safely. You will have two mentors (old members) who will introduce you to the club and follow you on the first tours. In this program you also have to jump in to the icy water and get out of the cut out hole using your ice claws.
Skating on natural ice is risky and safety issues are of great importance. The golden rules are never skate alone, never skate without at least one person in the group with proper experience, and never skate without safety equipment.
Safety Equipment
Safety equipment you always should have with you: - A floating aid. A backpack with spare clothes in waterproof bags. The backpack should have a waist belt.
- A complete set of spare clothes. In case the ice breaks and you end up in the water.
- Ice claws or ice-prods (Swedish "isdubbar"). These are a pair of screwdriver-like spikes. They are used to get a good grip when pulling yourself back on to the ice and they should be fastened high around your neck and secured with lines to prevent loss.
- A whistle to attract attention.
- An ice-pike (Swedish "ispik"). Used to check if the ice is strong enough. It looks like a heavy ski stick. Usually comes in pair and can also be used as poles when you need extra support.
- A rescue rope in a weighted throwing bag (Swedish "räddningslina"). Very useful in helping to pull people out of the water.
- To prevent injuries when falling it is also good to wear a helmet, knee and elbow protection.
After we passed the safety check the group is ready to skate out on Lake Mälaren.
It is the most perfect day for a skating tour. The temperature is -10 C (14 F) and after a short time the clouds disappear and the sun shines over a mirrorlike ice field that never seems to end. The only sound you hear is the ritsch-ratsch from skates moving forward at a speed of 20 km/h (12.5 miles/h) almost without effort.
 The tour leader is always in front of the group. No one is allowed to skate ahead of her/him. She or he has to decide when the ice is not safe and if we have to take another route or maybe take off the skates and walk on land. Before you can be a tour leader you have to have many years experience and take part in the tour leader courses. The tour leader is recognized by the red SSSK flag.
After two hours of skating it is time for a lunch break. We find a sunny place along the shore and unpack our lunch packages. This is the best time of the tour, relaxing in the sunshine with hot coffee and some good sandwiches together with a group of people you enjoy.
Tour description
Here is the tour description taken from the tour report:
Straight cross Görväln towards and through Klintsundet South of Landholmen. Crossing Näsfjärden aiming for Rönnskär, thereafter Broknapparna, and then Lagnö reaching Ormudden - turned back - over to the other side, short walk at Färjudden to pass Ormsundet - towards Smidö, walk over Granudden to Smidösundet - first break at Lagnö before Måskär - continuing along Smidö West side - to Gullhäll, 300 m walk - East of Svalgarn - big circle North of Fagerön - then returning the same way but only a 100 m walk at Gullhäll this time - second break at Ringudden, Smidö. At Ormsundet continuing South and rounding Dävensö via Skeppsbackasundet and Norrsundet - Näsfjärden - Älghorn - Lövstafjärden - North Lambarön and finishing at Hässelby Strand.
The tour took a full day and the sun starts to set before we reach our final aim, Hässelby Strand from where we can take the Metro back to Stockholm City. There is always someone in the group carrying a GPS receiver to record the tour and measure the exact distance covered. The tour started at 10:10 AM and finished at 16:30 PM and was 72 km (48 miles) long and it was one of my best skating tours ever.
Tour report
Already the same evening you can read the tour report written by the tour leader on your computer. Login to SSSKs member pages and click "Färdrapporter" and find your tour (Tokfina ytor på norra N Björkfjärden). There you will also find the tour track downloaded from one of the GPS receivers. One week later the tour report is open for non-members to read. Here are some photos from the tour. Show tour track in Google Earth (you must have Google Earth installed in your computer).
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A look at the equipment you need
First of all, a pair of skates. Touring skates (or Nordic skates) are long blades that can be attached, via bindings, to hiking or cross-country ski boots and are used for tour skating or long distance skating on natural ice. The blades are approximately 50 cm long with a radius of curvature (or rocker) of about 25 m. The blades are about 1 mm wide, with a flat cross-section. The length of the blades makes touring skates more stable on uneven natural ice than skates with shorter blades. Since tour skating often involves walking between lakes or around unskateable sections, the fact that the blades can be easily removed from one's boots is an asset. Although mainly used for non-competitive touring, touring skates are sometimes used in marathon speed skating races on natural ice (from Wikipedia).
There are two different systems to choose from, skates with a loose heel and skates with a fixed heel. I have been skating for more than 25 years using skates with a fixed heel but after talking to people who switched to loose heel I will buy a new pair of skates with a loose heel. The loose heel skates uses the same type of binding as used on skis; Salomon or Rottefella.
 
Here are some manufacturer of skates.
Manufacturer of bindings.
The boots must fit to the skates. For loose heel skates you use one type of boots and for fixed heel skates you use another type of boot.
 
Manufacturer of boots
The backpack acts as a lifejacket, and so needs to be firmly attached to your body by a waistbelt and leg straps, and gets its bouyancy from the sealed bags that contain the dry clothes. It should also have an outside pocket where the rescue rope can be easily reached in case of an emergency situation. Here is a list of things you should pack (in Swedish).
Manufacturer of backpacks
Safety equipmentIce claws Rescue rope Ice-pikes (pair)
  
Whistle Knee/elbow pads Wrist protection Helmet
   
Fully equipped
 Hello, here I am fully equipped and ready for a wild skating tour. Let's go through my equipment, starting from the top.
A helmet to protect my head from injuries when falling. Will also keep my head warm.
Ice claws around my neck as high up as possible, easy to grab when in water.
A whistle attached to the ice claws. Easy to find.
A carabiner (snap hook) attached to the rescue rope, placed on my shoulder so it can be easily found. Will be used to secure the rescue rope I will receive from my friends on the ice when I am in the water.
Elbow pads.
The yellow rescue rope is fixed to waist belt of the backpack.
A pair of ice-pikes. Used to check if the ice is strong enough. Can also be used as poles when I need extra support.
Knee pads. I use the same equipment when doing inline skating.
Boots and skates.
A backpack firmly attached to my body with a waist belt and leg straps.
The rescue rope throwing bag placed in an open pocket of the backpack, easy to find and easy to throw to my friends on the ice trying to rescue me.
SSSK equipment guidelines (in Swedish).
Where to skate
In the winter time there are frozen waters all over Sweden. You can use the SSSK atlas to find a water close to where you are. There is no guarantee the ice is skateable, it can be covered by half a meter of snow but at least you know where to look. It is all in Swdish but it is easy to understand and you can show it all in Google Earth. Here is a link to Mälardalens Isguide from an article in Utemagasinet. The book På skridskor i östra Svealand describes 75 tours in a radius of 150 km around Stockholm. Even when all lakes are covered with deep snow you can go skating on all the plowed tracks around Stockholm.
Ice reporting
How can you find out where there is skateable ice. Here are a few places to look.
Worlds's longest plowed wild skating track
 Every winter the 80 km (50 miles) wild skating race Vikingarännet will take place between Uppsala and Stockholm (map). The start is in Skarholmen at Lake Ekoln just south of Uppsala. The finish changes depending of the ice conditions. One year it can be Hässelby, the next year Rålambshovsparken downtown Stockholm and yet another year Kungsängen. More than 2000 skaters will participate every year and they come from all over the world.
A part of this track (Vikingaslingan 60 km) will be plowed the whole winter as long as the ice is at least 15 cm thick. You can choose to start in Hässelby and skate north or start in Uppsala and skate south, it all depends on the wind. You don't have to skate the whole distance, you can stop in Sigtuna, a small cosy town where you can have a cup of hot chocolate at Tant Bruns Kaffestuga and then take the bus back to Stockholm or Uppsala
Here is the history of Vikingarännet.
To know where you are
When skating on large lakes or in the Stockholm archipelago you need to bring a map and a compass. If you don't know the area you can easily get lost among all islands and narrow passages. The weather can change fast and a snow storm or fog can make it impossible to find the way without a compass or GPS.
SSSK's anniversary map (1:50 000) is a set of twelve maps covering Eastern Svealand with Lake Mälaren and the Stockholm archipelago. It is printed on synthetic paper (Tyvek) and is 100% water resistent and can be folded 1000 times without falling a part.
The Green map (Gröna kartan 1:50 000) covers all of Sweden and can be bought in book stores and in outdoor equipment stores. Lantmäteriverket is responsible for printing all the official maps in Sweden. Here you can find out which one of the 625 maps you need.
Here are links to places where you can find maps.
Skate maintenance
For a good skating experience it is important to have sharp blades on your skates. At least once a year you should have them sharpened by a professional skate sharpener. But in between you can sharpened the blades yourself using the proper sharpening stone. You can also use a hand-held Skatemate or Gnidde for a quick sharpening before you start the tour. Here is description on how to use Gnidde.
More information
 Photo: Sture Homström
You are invited
Write about a subject I missed or add more information to subjects already written about. All contributions are welcomed.
Sven-Åke Andersson
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Posted at 08:31 am by svenand
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FPGA design from scratch. Part 47
EDK 9.2i has been released
I got an email from Xilinx:
Dear Valued Customer,
Thank you for choosing the Xilinx Embedded Development Kit (EDK) as your embedded hardware and software development solution for Virtex(tm)-5, Virtex-4, Virtex-II Pro and Spartan(tm) Series PowerPC(tm) and MicroBlaze(tm) processing systems. Your Xilinx EDK 9.2i software is now available for download!*
The Xilinx EDK software is built from much the same core technology as the industry's favorite FPGA design environment, Xilinx ISE(™). The graphical user interface for EDK, DesignVision Award winning Xilinx Platform Studio(tm)(XPS), is the technology that integrates all the processes from design entry to debug and verification, helping you quickly get started with your embedded designs.
Please be aware that EDK 9.2i requires a valid installation of ISE 9.2i, including ISE Service Pack 2, to function properly.
To download your software update, select the following link and use your Xilinx login to access your personalized Xilinx Electronic Fulfillment (XEF) site:
http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=esd_oms
What is new in this release
Xilinx Platform Studio (XPS) Enhancements
This release includes the following XPS enhancements:
• Higher-performance processing systems due to:
o New optimized processor bus infrastructure based on CoreConnect PLB v4.6.
o Integration of MultiPort Memory Controller (MPMC3), complete with XPS configuration wizard,to easily configure high-performance memory interfaces.
o MicroBlaze version 7, which supports the optional Memory Management Unit (MMU).
o Updated processor IP catalog containing 50 new or redesigned IP cores, with IP optimized for new PLB v4.6 interconnect.
• Full-access support for Spartan-3A, Spartan-3AN, and Spartan-3A DSP.
• 64-bit Linux support.
• EDK project file (.xmp) support in ISE. An .xmp file can now be the top-level source file in ISE.
• Simpler Clock Generation.
• Improved timing on reset signals in embedded design.
• Support for 3rd party text editors.
• Multi-processor support with mutex and mailbox pcores.
Software Development Kit Improvements
This release includes the following improvements to Platform Studio SDK:
• Xilkernel support for run-time memory protection on MicroBlaze using the MMU • 64-bit Linux Support
• Support for Remote Debug
• Support for Initialization of Debug Session with Data files
• Support for Watchpoints
• MicroBlaze GNU tools have been upgraded to new versions as follows:
o GCC upgraded from 3.4.1 to 4.1.1
o GDB upgraded from 5.3 to 6.5
o Support for new MicroBlaze floating point instructions and MMU instructions
o GCC support for DWARF2 debug format
Let's install EDK 9.2i
Before we can start to install EDK 9.2i we should have already installed ISE 9.2i. We must always use the same version of ISE and EDK.
We click on the link EDK 9.2i - Embedded Development Kit (All Platforms) to start the download. The EDK92.zip file is almost 1.5Gb.
Read part 14 for more information about installing EDK.
Running EDK 9.2i
This wizard will help us upgrade the cores and drivers in our project.
We have to go through a number of updates.
Some of the new cores are not compatible with the older versions we are using. We will not update to these new versions.
The software device drivers have also been updated.
After we upgraded everything the ETC_system.mhs and ETC-system.mss files will be modified.
We are are ready to use EDK 9.2
When we start the bitstream generation the following error occurs:
At Local date and time: Wed Nov 7 17:55:10 2007
make -f ETC_system.make bits started...
*********************************************
Running Xilinx Implementation tools..
*********************************************
xilperl /home/svenand/cad/edk92i/data/fpga_impl/manage_fastruntime_opt.pl -reduce_fanout no
xilperl: error while loading shared libraries: libdb-4.1.so: cannot open shared object file: No such file or directory
make:
*** [__xps/ETC_system_routed] Error 127
Done!
We are missing the libdb-4.1.so library. The easy fix is to link to the libdb-4.2.so library.
sudo ln -s /usr/lib/lib-4.2.so /usr/lib/libdb-4.1.so
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Posted at 10:12 pm by svenand
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After more than one year of playing around with this blog I have got a real job. I have started to work for a company called ORSoC.
ORSoC is an electronic development company. We are specialized in FPGA/ASIC development and SoC (System on Chip) design based on open source, license free IPs. This technology offers many important advantages to developers – cost reduction is just one of many.
One of the fundamental IPs within the technology is the 32 bits RISC processor, the OR1200, which is very similar to the ARM9. The technology offers over 400 different IPs, including peripherals, crypto, processors, arithmetic IPs, etc.
Based on the technology ORSoC may design a unique SoC that includes all functionality required for a special product. In many designs we use a multi processor solution to divide different algorithms to different processors. The flexibility in the technology makes it possible to 100% fulfill the unique requirements for a special product (extreme low power consumption, high performance, accuracy, etc).
Another great advantage with the technology is that the designs are technology independent. You may port it between FPGAs, structured ASICs, standard ASICs. The technology also reduces the "end-of-life problems".
ORSoC are experts within the OpenCores technology, offering turn-key designs and support for the technology. ORSoC has a special design tool to our disposal which guaranties reliable and flexible design as well as very rapid development cycles.
Posted at 02:38 pm by svenand
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FPGA design from scratch. Part 46
Installing and running the Linux OS
Now when we have updated our hardware to meet all software requirements it is time to install and bootup the Linux kernel we finished in part 43. Let's go through the following steps:
- Connect everything (see part 29)
- Generate a new netlist (Hardware->Generate Netlist)
- Generate a new bitstream (Hardware->Generate Bitstream)
- Download the bitstream (Device Configuration->Download Bitstream)
Disassembly of the Linux kernel
We use the following command to generate an assembly listing of the Linux kernel code: mb-obdump -d /tftpboot/image.elf > kernel.asm
Here is the start.
44000000 <_start>:
44000000: 94208001 mfs r1, rmsr
44000004: a421fffd andi r1, r1, -3
44000008: 9401c001 mts rmsr, r1
4400000c: b000441f imm 17439
44000010: 31a0c000 addik r13, r0, -16384 // 441fc000 <__init_begin>
44000014: b000441e imm 17438
44000018: 30408000 addik r2, r0, -32768 // 441e8000 <_sdata>
4400001c: b000441f imm 17439
44000020: 3020bffc addik r1, r0, -16388
44000024: b000441e imm 17438
44000028: 33e082a8 addik r31, r0, -32088 // 441e82a8 <init_task>
4400002c: b0004400 imm 17408
44000030: 30c00c84 addik r6, r0, 3204 // 44000c84 <machine_early_init>
44000034: 99fc3000 brald r15, r6
44000038: 80000000 or r0, r0, r0
4400003c: b0004400 imm 17408
44000040: 31e00f68 addik r15, r0, 3944 // 44000f68 <machine_halt>
and here is the end.
4421162c <cleanup_sunrpc>:
4421162c: 3021ffe4 addik r1, r1, -28
44211630: f9e10000 swi r15, r1, 0
44211634: b000fff8 imm -8
44211638: b9f4e828 brlid r15, -6104 // 4419fe60 <cleanup_socket_xprt>
4421163c: 80000000 or r0, r0, r0
44211640: b000fff9 imm -7
44211644: b9f4ecc4 brlid r15, -4924 // 441b0308 <unregister_rpc_pipefs>
44211648: 80000000 or r0, r0, r0
4421164c: b000fff9 imm -7
44211650: b9f4053c brlid r15, 1340 // 441a1b8c <rpc_destroy_mempool>
44211654: 80000000 or r0, r0, r0
44211658: b000441f imm 17439
4421165c: 30a078d4 addik r5, r0, 30932 // 441f78d4 <ip_map_cache>
44211660: b000fff9 imm -7
44211664: b9f4bc30 brlid r15, -17360 // 441ad294 <cache_unregister>
44211668: 80000000 or r0, r0, r0
4421166c: b000441d imm 17437
44211670: 30a006a8 addik r5, r0, 1704
44211674: bc230028 bnei r3, 40 // 4421169c
44211678: b000fff9 imm -7
4421167c: b9f4f8a0 brlid r15, -1888 // 441b0f1c <rpc_unregister_sysctl>
44211680: 80000000 or r0, r0, r0
44211684: b000fff9 imm -7
44211688: b9f4f7b8 brlid r15, -2120 // 441b0e40 <rpc_proc_exit>
4421168c: 80000000 or r0, r0, r0
44211690: e9e10000 lwi r15, r1, 0
44211694: b60f0008 rtsd r15, 8
44211698: 3021001c addik r1, r1, 28
4421169c: b000ffdf imm -33
442116a0: b9f49504 brlid r15, -27388 // 4400aba4 <printk>
442116a4: 80000000 or r0, r0, r0
442116a8: b800ffd0 bri -48 // 44211678
Disassembly of section .init.ivt:
44211e50 <__ivt_start>:
44211e50: b0004400 b80821b0 b0004400 b80821c0 ..D...!...D...!.
44211e60: b0004400 b8081fa0 b0004400 b8082450 ..D.......D...$P
44211e70: b0004400 b80839f0 00000000 00000000 ..D...9.........
...
44211eb0: b0004400 b8082320 ..D...#
Download the Linux kernel
We will use the Xilinx Microprosser Debugger (XMD) to help us download the image file.
-> xmd
Xilinx Microprocessor Debug (XMD) Engine
Xilinx EDK 9.1.02 Build EDK_J_SP2.4
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
XMD% connect mb mdm..... ...... JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 0a001093 8 System_ACE
2 05059093 16 XCF32P
3 01e58093 10 XC4VFX12
4 09608093 8 xc95144xl
MicroBlaze Processor Configuration :
-------------------------------------
Version............................6.00.b
No of PC Breakpoints...............2
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........off
Data Cache Support.................off
Exceptions Support................off
FPU Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Connected to MDM UART Target
Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234
XMD% dow -data /tftpboot/image.bin 0x44000000
This command will download the Linux kernel image to the SDRAM starting at address 0x44000000
Let's read the first and last memory locations to find out if the download was successful.
XMD% mrd 0x44000000
mrd 0x44000000
44000000: 94208001
XMD% mrd 0x44211EB0mrd 0x44211eb0
44211EB0: B0004400
To start the Linux bootup sequence we use the following command:
XMD% con 0x44000000con 0x44000000
Info:Processor started. Type "stop" to stop processor
RUNNING> XMD% stop
stop
XMD% Info:User Interrupt, Processor Stopped at 0x440044c8
We are having a problem here. It seems like the bootup sequence hangs and never finishes. This is what the code looks like around address 0x440044c8:
440044c4 <early_printk_putc>:
440044c4: 90a50060 sext8 r5, r5
440044c8: b000a000 imm -24576
440044cc: e8600008 lwi r3, r0, 8
440044d0: a4630008 andi r3, r3, 8
440044d4: be23fff4 bneid r3, -12 // 440044c8
440044d8: a46500ff andi r3, r5, 255
440044dc: b000a000 imm -24576
440044e0: f8600004 swi r3, r0, 4
440044e4: b60f0008 rtsd r15, 8
440044e8: 80000000 or r0, r0, r0
Let's set a breakpoint at address 0x440044c4 and start from the beginning.
XMD% bps 0x440044c4
bps 0x440044c4
Setting breakpoint at 0x440044c4
XMD% con 0x44000000
con 0x44000000
Info:Processor started. Type "stop" to stop processor
RUNNING> XMD% Info:Software Breakpoint 0 Hit, Processor Stopped at 0x440044c4
Let's single step and see what happens.
XMD% stp
stp
440044C8: B000A000 imm -24576
XMD% stp
stp
440044D0: A4630008 andi r3 , r3 , 8
XMD% stp
stp
440044D4: BE23FFF4 bneid r3 , -12
XMD% stp
stp
440044C8: B000A000 imm -24576
XMD% stp
stp
440044D0: A4630008 andi r3 , r3 , 8
XMD% stp
stp
440044D4: BE23FFF4 bneid r3 , -12
We are caught in this loop. Here are the register values:
XMD% rr
rr
r0: 00000000 r8: 00000000 r16: 440044c4 r24: 00000000
r1: 441fbd94 r9: 00000000 r17: 00000000 r25: 00000000
r2: 441e8000 r10: 00000008 r18: ffffffda r26: 00000000
r3: 00000046 r11: ffffffff r19: 441fbdd4 r27: 00000000
r4: 441e8ee0 r12: 0000002d r20: 00000000 r28: 00000000
r5: 00000046 r13: 441fc000 r21: 00000000 r29: 00000000
r6: 441fbdd4 r14: 00000000 r22: 00000024 r30: 00000000
r7: 00000026 r15: 44004514 r23: 00000046 r31: 441e82a8
pc: 440044c8 msr: 00000000
XMD%
I am building a new kernel. See part 43.
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Posted at 03:37 pm by svenand
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FPGA design from scratch. Part 45
A computer cache
A CPU cache is a temporary storage area where frequently accessed data can be stored for rapid access. Once the data is stored in the cache, future use can be made by accessing the cached copy rather than re-fetching or recomputing the original data, so that the average access time is lower.
A cache is made up of a pool of entries. Each entry has a datum (a nugget of data) which is a copy of the datum in some backing store. Each entry also has a tag, which specifies the identity of the datum in the backing store of which the entry is a copy. When the cache client (a CPU, web browser, operating system) wishes to access a datum presumably in the backing store, it first checks the cache. If an entry can be found with a tag matching that of the desired datum, the datum in the entry is used instead. This situation is known as a cache hit. For more information about the MicroBlaze cache functionality read the MicroBlaze Processor Reference Guide.
Enabling MicroBlaze caches
To enable the instrcuction and data caches we open the MicroBlaze IP configure window and select Cache. We enable the Instruction cache and the Data cache by ticking the two check boxes.
Specify cacheable memory segment
Cache Base Address and Cache High Address determines the cacheable segment of the SDRAM. We will make the whole SDRAM cacheable setting Cache Base Address to 0x44000000 and Cache High Address to 0x47ffffff.
Instruction cache operation
For every instruction fetched, the instruction cache detects if the instruction address belongs to the cacheable segment. If the address is non-cacheable, the cache controller ignores the instruction and lets the OPB or LMB complete the request. If the address is cacheable, a lookup is performed on the tag memory to check if the requested address is currently cached. The lookup is successful if: the word and line valid bits are set, and the tag address matches the instruction address tag segment. On a cache miss, the cache controller requests the new instruction over the instruction CacheLink (IXCL) interface, and waits for the memory controller to return the associated cache line.
Data cache operation
The MicroBlaze data cache implements a write-through protocol. Provided that the cache is enabled, a store to an address within the cacheable range generates an equivalent byte, halfword, or word write over the data CacheLink (DXCL) to external memory. The write also updates the cached data if the target address word is in the cache (i.e. the write is a cache-hit). A write cache-miss does not load the associated cache line into the cache. Provided that the cache is enabled a load from an address within the cacheable range triggers a check to determine if the requested data is currently cached. If it is (i.e. on a cache-hit) the requested data is retrieved from the cache. If not (i.e. on a cache-miss) the address is requested over data CacheLink (DXCL), and the processor pipeline stalls until the cache line associated to the requested address is returned from the external memory controller.
Xilinx CacheLink (XCL)
Xilinx CacheLink (XCL) is a high performance solution for external memory accesses. The MicroBlaze CacheLink interface is designed to connect directly to a memory controller with integrated FSL buffers, e.g. the MCH OPB DDR SDRAM controller. This method has the lowest latency and minimal number of instantiations.
The interface is only available on MicroBlaze when caches are enabled. It is legal to use a CacheLink cache on the instruction side or the data side without caching the other. Memory locations outside the cacheable range are accessed over OPB or LMB. Cached memory range is accessed over OPB whenever the caches are software disabled (i.e. MSR[DCE]=0 or MSR[ICE]=0).
Adding the MCH_OPB_DDR_SDRAM controller
We will replace the current SDRAM controller OPB_DDR_SDRAM with the new MCH_OPB_DDR_SDRAM controller.
(Courtesy of Xilinx)
Connect IXCL and DXCL
We connect the MCH0 to the MicroBlaze IXCL port and the MCH1 to the MicroBlaze DXCL port.
Connecting ports
There are two new ports found in the mch_opb_ddr peripheral, DDR_Sleep and DDR_WakeUp.
Rising edge on DDR_Sleep enters the DDR SDRAM self refresh mode. A minimum period of 50uS after the assertion of DDR_Sleep is required before MCH_OPB_Rst can be asserted. We keep this signal low.
DDR_WakeUp indicates whether the DDR SDRAM must go through the power-up initialization after reset, or if only the sequence to exit the self refresh mode needs to be executed. This signal is sampled when reset negates and therefore should be asserted before MCH_OPB_Rst negates. We keep this signal low.
ETC_system.mhs
Here is the mch_opb_ddr setup part.
BEGIN mch_opb_ddr
PARAMETER INSTANCE = mch_opb_ddr_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_DDR_DWIDTH = 32
PARAMETER C_DDR_TMRD = 14997
PARAMETER C_MEM0_BASEADDR = 0x44000000
PARAMETER C_MEM0_HIGHADDR = 0x47ffffff
BUS_INTERFACE MCH0 = microblaze_0_IXCL
BUS_INTERFACE MCH1 = microblaze_0_DXCL
BUS_INTERFACE SOPB = mb_opb
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
PORT DDR_Sleep = net_gnd
PORT DDR_WakeUp = net_gnd
END
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Posted at 05:54 pm by svenand
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FPGA design from scratch. Part 44
Adding an External Memory Controller
We need a permanent storage for our Linux installation. The ML403 board contains a flash memory which is the perfect place to store our Linux OS to to be used during bootup of our system. To be able to read to and write from the flash memory we have to add an External Memory Controller (EMC). Let's do that.
The EMC supports up to four memory banks. We will use only one.
Generate addresses
The flash memory that comes with the ML403 board is 512 MB and with a 32 bit databus we will have a 128 MB address range.
Software platform settings
We have to tell the software where the flash is located. Open the Software->Software Platform Settings window and select OS and Libraries. Here we specify which memory bank we use (0) and the name of the external memory controller.
OPB External Memory Controller
The OPB EMC receives control signals from the OPB to read and write to external memory devices. The OPB EMC provides an interface between the OPB and one to four external banks of memory components. The EMC supports OPB data bus widths of 8,16 & 32 bits, and memory subsystem widths of 8,16 & 32 bits. The OPB EMC supports the OPB V2.0 byte enable architecture. Any access size up to the width of the OPB data bus is permitted. When the width of the memory is less than the width of the OPB, multiple memory cycles are performed to transfer the data width of the bus if data-width matching has been enabled for that memory bank.
The OPB EMC provides basic read/write control signals and the ability to configure the access times for read, write, and recovery times when switching from read to write or write to read. When the OPB EMC is set for flash memory control it is organized like an SRAM interface. The OPB EMC assumes that the Flash programming circuitry is built into the Flash components and that the command interface to the Flash is handled in software.
(Courtesy of Xilinx)
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Posted at 07:43 am by svenand
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FPGA design from scratch. Part 43
Installing a Linux OS
It has been a long and bumpy ride but now we start to see the light in the tunnel. So keep up, stay onboard, we will soon reach the final destination. We are ready for the real challenge, installing a Linux OS in our embedded system.
Why using a Linux OS
Linux use in future embedded, mobile, and real-time projects will grow 278 percent over that in past projects, suggests a recent survey by Venture Development Corp. (VDC). Meanwhile, proprietary commercial embedded operating systems are holding steady, gaining customers from do-it-yourself OS users, but losing them just as fast to Linux, the analyst firm reports.
Embedded Linux OS
The MicroBlaze procssor has one drawback, it doesn't include a Memory Management Unit (MMU). To overcome this limitation, development started early to come up with a Linux kernel that could be used on a MMU-less processor. This work lead to to the introduction of uClinux. Most of the work done in the uClinux was been incorporated into the Linux kernel development and the 2.6 Linux kernel is the first stable release with mainline support for processors, such as MicroBlaze, that do not have an MMU eliminating the need to apply and forward-port uClinux patches.
uClinux
The original uClinux was a derivative of Linux 2.0 kernel intended for microcontrollers without MMUs. However, the Linux/Microcontroller Project has grown both in brand recognition and coverage of processor architectures. Today's uClinux as an operating system includes Linux kernel releases for 2.0 2.4 and 2.6 as well as a collection of user applications, libraries and tool chains.Finding a Linux OSThis table shows some of the Linux OSes that runs on a MicroBlaze processor.
Third Party Real Time Operating Systems (RTOS) Support
This table and this table shows RTOS supporting PowerPC and MicroBlaze.
Application notes
You can find a number of application notes from Xilinx describing how to install an RTOS on a MicroBlaze processor.
- Getting Started with uClinux on the MicroBlaze Processor (XAPP730)
- Getting Started with the Nucleus PLUS RTOS and EDGE Tools on the MicroBlaze Processor (XAAP1016)
Choosing a Linux OS
We will use PetaLinux from PetaLogix. PetaLogix is an embedded Linux solution provider founded by Dr John Williams, architect and maintainer of the port of the uClinux operating system to the Xilinx MicroBlaze soft processor.
PetaLinux
PetaLogix has released PetaLinux v0.20, including Linux kernel 2.6.20 support for the Xilinx MicroBlaze soft-CPU architecture. PetaLinux is available as a free download from http://developer.petalogix.com, along with complete documentation, getting started guides and reference designs. Pre-built demo packages for the Xilinx ML401, Spartan3E-500 and Spartan3E-1600 allow a instant preview of the capabilities of Embedded Linux on the MicroBlaze.The "uClinux microblaze port" mailing list
John Williams has setup a mailing list where you can ask all kind of questions about uClinux and the port to MicroBlaze.
Embedded Linux developer forumuCdot is the place to find more information about embedded Linux.PetaLinux system requirements
The minimum system requirements to build a PetaLinux ready hardware platform are:
- MicroBlaze soft core processor
- Timer
- Interrupt Controller
- Standard input and output devices
- External memory controller
- RAM (DDR-SDRAM)
- ROM (Flash) optional
- Microprocessor Debug Module (for image download)
PetaLinux installation procedure
Let's read the installation guide.
Download
We will start by downloading petalinux-v0.20-rc3.tar.gz. The gzipped tar file is 317MB.
Select an installation directory
Create: mkdir /home/svenand/linux and goto the installation directory: cd /home/svenand/linux and move the tar file to this directory: mv /home/svenand/Desktop/petalinux-v0.20-rc3.tar.gz .
Unpacking
Unzip and unpack the file using the following command: tar zxvf petalinux-v0.20-rc3.tar.gz
After unpacking the following directory structure has been generated. The total size is 1.77GB
Environment setup
To set up our PetaLinux environment, change to the PetaLinux root directory and run the set up script. This script updates our path to point to the bundled gcc toolchain, and sets the $PETALINUX environment variable to point to the PetaLinux root.
-> cd petalinux-v0.20-rc3
-> source settings.sh (bash and sh)
-> source setting.csh (csh and tcsh)
We will add the following lines to .bashrc to make sure the script will always be run:
cd /home/svenand/linux/petalinux-v0.20-rc3source /home/svenand/linux/petalinux-v0.20-rc3/settings.sh
cd /home/svenand
Configure and build our Linux kernel
After we have everything setup it is time to configure and build our Linux kernel. Let's follow the PetaLinux Platform from Scratch tutorial.
Selecting a platform
Selecting a platform is the initial step in the build of a kernel for our target. A platform configuration is essentially a collection of kernel configurations that are associated with that particular platform. This process allows the user to configure for a target platform without having to go through all the configurations associated with that platform.
Create a New Vendor Platform variant
We will use the petalinux-new-platform script to create a new vendor and platform combination for our system.
-> cd $PETALINUX/software/petalinux-dist
-> petalinux-new-platform -v Xilinx -p ML403 -k 2.6
The ML403 board has been added to the Xilinx directory.
PetaLinux kernel configuration
To start the configuration program execute the following commands:
-> cd software/petalinux-dist
-> make xconfig
Vendor/Product Selection We select vendor Xilinx and the ML403 platform.
Kernel/Library/Defaults selection
 We will use the default settings and click Save and Exit. The configuration setup is stored in the file $PETALINUX/software/petalinux-dist/.config. Later on we will change the configuration to match the hardware in our system.Hardware modification
MicroBlaze
Instruction cache : Enabled
Data cache : Enabled
RS232 UART
Baudrate : 115200
Interrupt : Enable
Debug module
Enable the UART Interface on OPB: Disable
Interrupt : Enable
For more information about the hadware setup read the PetaLinux Platform from Scratch tutorial.
Auto configuration
PetaLinux AutoConfig framework allows the hardware configurations to be propagated to the bootloader and Linux kernel configurations. A few simple parameters in the EDK project's MSS (MicroProcessor Software Specification) file are all that is required to automatically configure the kernel and bootloader for our specific hardware platform.
Briefly, the steps are: - Create a new linux platform.
- Create a EDK hardware project
- Edit the MSS file to specifiy the PetaLinux autoconfiguration BSP tools (see below)
- Use XPS to build the hardware project and generate libraries and BSPs
- Use the petalinux-copy-autoconfig helpder script to propagate the system settings from your hardware project, across to your new Linux platform
- Rebuild PetaLinux, to get your fully configured bootloader, Linux kernel and root filesystem image, ready for download.
Editing the MSS file
See the PetaLinux User Guide AutoConfig. Let' take a look in the ETC_system.mss file. This is what the OS part looks like:
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = RS232_Uart
PARAMETER STDOUT = RS232_Uart
END
We will change it like this:
BEGIN OS
PARAMETER OS_NAME = petalinux
PARAMETER OS_VER = 1.00.b
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = RS232_Uart
PARAMETER STDOUT = RS232_Uart
PARAMETER MAIN_MEMORY = DDR_SDRAM_64Mx32
PARAMETER MAIN_MEMORY_BANK = 0
END
Generate netlist and libraries
Let's start Xilinx Platform Studio and generate a new netlist and libraries and BSPs.
--> xps ETC_system.xmp &
The following error stops us from loading our project.
ERROR:MDT - Can not find MLD for the os petalinux 1.00.b
INFO:MDT - Directories Searched :
- /home/svenand/root/projects/ETC/xps/bsp/petalinux_v1_00_b/data
- /home/svenand/cad/edk91i/sw/ThirdParty/bsp/petalinux_v1_00_b/data
- /home/svenand/cad/edk91i/sw/XilinxProcessorIPLib/bsp/petalinux_v1_00_b/data
- /home/svenand/cad/edk91i/sw/lib/bsp/petalinux_v1_00_b/data
To fix this problem we have to find the petalinux .mld file and copy it to the XPS project directory. The .mld file can be found here: $PETALINUX/hardware/edk_user_repository/PetaLogix/bsp/petalinux_v1_00_b/data. We will make a link to the bsp directory from our EDK project directory.
-> cd $EDK_PROJECT
-> ln -s bsp $PETALINUX/hardware/edk_user_repository/PetaLogix/bsp
We use the menu command Hardware->Generate Netlist to generate a new netlist. No configuration files are generated during the netlist generation. We then generate the libraries using the menu command Software->Generate Libraries and BSPs. This process will create the following directory structure.
Here we find the auto-config.in (Linux 2.4.x) and the Kconfig.auto (Linux 2.6.x) configuration files.
Copying the AutoConfig file
To copy the configuration file across to our currently selected PetaLinux platform, we use the petalinux-copy-autoconfig command as follows: petalinux-copy-autoconfig ETC_system.xmp
==>petalinux-copy-autoconfig ETC_system.xmp
INFO: Attempting vendor/platform auto-detect
INFO: Auto-detected Xilinx/ML403 combination.
Auto-config file successfully updated for Xilinx ML403
The script will automatically detect which platform and which Linux kernel we have specified by reading the.config file and copy the right configuration file to the right place.
Platform reconfiguration
Next we have to reconfigure the platform settings of our custom platform into PetaLinux. This step requires us to run through the following configuration options.
More to be added.
Changing the default shell
In Ubuntu 7.04 the default shell (/bin/sh) is defined as /bin/dash instead of /bin/bash. The build process script relays on the bash shell to function. To change the default shell to bash execute the following commands:
--> sudo rm -f /bin/sh
--> sudo ln -s /bin/bash /bin/sh
To change back to dash execute the following commands:
--> sudo rm -f /bin/sh
--> sudo ln -s /bin/dash /bin/sh
Adding the /tftpboot directory
When working with network-enabled embedded Linux systems, it is often convenient to update Linux images and other files over the TCP/IP network. The directory /tftpboot is commonly used as a transfer directory for this purpose. The PetaLinux tools can optionally copy Linux and bootloader files into this (or another) directory automatically. To create the /tftpboot directory, you must have root access.
-> sudo mkdir /tftpboot
-> sudo chmod -R 777 /tftpboot
Installing zlib1g-dev
We need zlib to be able to build the Linux kernel: sudo apt-get install zlib1g-dev
Build the 2.6 kernel and user applications
The build process entails the following tasks. - Build the Linux Kernel
- Build GNU tools
- Build the Root Filesystem
- Build the U-Boot bootloader
To start the build process for the newly added platform, in the $PETALINUX/software/petalinux-dist directory execute the following commands.
-> cd $PETALINUX/software/petalinux-dist
1. Build the project dependencies.-> yes "" │ make oldconfig dep
2. Build images.
-> make all
The logfile
.......
Image Name: PetaLinux Kernel 2.6
Created: Sun Sep 30 17:36:28 2007
Image Type: MicroBlaze Linux Kernel Image (uncompressed)
Data Size: 3289251 Bytes = 3212.16 kB = 3.14 MB
Load Address: 0x44000000
Entry Point: 0x44000000
# Run mkimage to build u-boot autoscr script
/home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/u-boot/tools/mkimage -A microblaze -O linux -T script -C none
-a 0 -e 0 -n "PetaLinux Autoscr Script"
-d /home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/u-boot/board/petalogix/microblaze-auto/ub.config /home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/images/ub.config.img
Image Name: PetaLinux Autoscr Script
Created: Sun Sep 30 17:36:29 2007
Image Type: MicroBlaze Linux Script (uncompressed)
Data Size: 1412 Bytes = 1.38 kB = 0.00 MB
Load Address: 0x00000000
Entry Point: 0x00000000
Contents:
Image 0: 1404 Bytes = 1 kB = 0 MB
# Copy image files into /tftpboot, if requested
if [ "y" == 'y' ] ; then
cp /home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/images/* "/tftpboot";
fi
make[2]: Leaving directory `/home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/vendors/Xilinx/ML401'
make[1]: Leaving directory `/home/svenand/linux/petalinux-v0.20-rc3/software/petalinux-dist/vendors'
==>
Congratulations to all of us. We made it!!!!
Output images
Once the build process is completed, all the images are located in both the $PETALINUX/software/petalinux-dist/images and the /tftpboot directory.
tftpboot directory content Image Name
| Description | File Size
| Linux Kernel
| | | | image.bin | The Linux kernel and root filesystem image in binary format
| 3.1 MB
| | image.elf | The Linux kernel and root filesystem image in ELF format | 3.4 MB
| | image.srec | The Linux kernel and root filesystem image in SREC format
| 9.3 MB
| | image.ub | The Linux kernel and root filesystem image in U-Boot format | 3.1 MB
| | linux.bin | ?? | 1.9 MB
| | romfs.img | The ROMFS image in binary format
| 1.2 MB | | U-Boot | | | | u-boot.bin | The U-Boot image in binary format
| 119 KB
| | u-boot.srec | The U-Boot image in SREC format | 358 KB
| | u-boot-s.bin | The relocatable U-Boot image in binary format | 119 KB | | u-boot-s.elf | The relocatable U-Boot image in ELF format | 120 KB | | u-boot-s.rec | The relocatable U-Boot image in SREC format | 358 KB
| | ub.config.img | U-Boot platform configuration script in binary format
| 1.4 KB
| Top Next Previous
Posted at 07:20 am by svenand
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Some of you have asked me why I didn't write a book instead of this blog. Here are a few reasons:
Time to market
It takes 10 minutes to setup a blog account at one of the many companies offering blog services. It may take a year to have a book published.
Simplicity
You can start from day one writing your blog. You don't have know anything about web design or html. Write the text and click publish. It is that easy.
Flexibility
You have a lot of freedom when designing your blog. You can use any font style and font size you like. There are hundreds of page designs you can choose from and if you don't like them you can design one yourself. You can add as many images you like and you can link to other web pages and documents.
Extend and update
At any time you can introduce more information to your blog, fix mistakes and add updates.
Interaction
A blog is the best way to interact with your readers. They can ask questions and add comments and you can answer and make comments.
Presence/Exposure
This blog can be read all over the world. The only thing you need is a computer and an internet connection.
And here is one reason for not writing a blog:
No food on the table
Writing a blog doesn't bring food on the table. You have to find a way to make some money out of your blog.
Posted at 07:19 am by svenand
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FPGA design from scratch. Part 42
Adding a timer
Before we can install a Linux OS in our embedded system we have to add a timer IP. Now when we know how to add a new peripheral it will only take us a few minutes. We start by selecting the OPB Timer Counter from the IP catalog.
We add it and configure it.
We generate addresses and connect the ports and we are done.
Connect the interrupt signal
We will add the interrupt signal coming from the timer/counter to the interrupt controller. We give the highest priority to the timer interrupt. Select the Ports display and click the first port to display this window.
OPB Timer/Counter
The OPB Timer/Counter is a 32-bit timer module that attaches to the OPB (On-Chip Peripheral Bus). It includes two programmable interval timers with interrupt, event generation, and event capture capabilities. It also includes a Pulse Width Modulator (PWM) output and a configurable counter width. Each of the two timer modules is capable of holding the initial value of the counter for event generation or capture a value based on the mode of the timer.
 (Courtesy of Xilinx)
Register address map
Register Name
| Abbreviation | OPB Offset
| Type
| Control/Status Register 0
| TSCR0 | 0x00 | R/W | Load Register 0
| TLR0 | 0x04 | R/W | Timer/Counter Register 0
| TCR0 | 0x08 | R | Control/Status Register 1
| TSCR1 | 0x10 | R/W | Load Regster 1
| TLR1 | 0x14 | R/W | Timer/Counter Register 1
| TCR1 | 0x18 | R | The registers are organized as big-endian data.
Library Generation
After running libgen we have copied the following source files to the libsrc directory.
xparameters.h
/* Definitions for driver TMRCTR */
#define XPAR_XTMRCTR_NUM_INSTANCES 1
/* Definitions for peripheral OPB_TIMER_0 */
#define XPAR_OPB_TIMER_0_BASEADDR 0x43505000
#define XPAR_OPB_TIMER_0_HIGHADDR 0x435050FF
#define XPAR_OPB_TIMER_0_DEVICE_ID 0
xtmrctr_l.h
/************************** Constant Definitions *****************************/
/**
* Defines the number of timer counters within a single hardware device. This
* number is not currently parameterized in the hardware but may be in the
* future.
*/
#define XTC_DEVICE_TIMER_COUNT 2
/* Each timer counter consumes 16 bytes of address space */
#define XTC_TIMER_COUNTER_OFFSET 16
/** @name Register Offset Definitions
* Register offsets within a timer counter, there are multiple
* timer counters within a single device
* @{
*/
#define XTC_TCSR_OFFSET 0 /**< control/status register */
#define XTC_TLR_OFFSET 4 /**< load register */
#define XTC_TCR_OFFSET 8 /**< timer counter register */
/** @name Control Status Register Bit Definitions
* Control Status Register bit masks
* Used to configure the timer counter device.
* @{
*/
#define XTC_CSR_ENABLE_ALL_MASK 0x00000400 /**< Enables all timer counters */
#define XTC_CSR_ENABLE_PWM_MASK 0x00000200 /**< Enables the Pulse Width
Modulation */
#define XTC_CSR_INT_OCCURED_MASK 0x00000100 /**< If bit is set, an interrupt has
occured.*/
/**< If set and '1' is written
to this bit position,
bit is cleared. */
#define XTC_CSR_ENABLE_TMR_MASK 0x00000080 /**< Enables only the specific timer */
#define XTC_CSR_ENABLE_INT_MASK 0x00000040 /**< Enables the interrupt output. */
#define XTC_CSR_LOAD_MASK 0x00000020 /**< Loads the timer using the load
value provided earlier in the
Load Register, XTC_TLR_OFFSET. */
#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010 /**< In compare mode, configures the
timer counter to reload from the
Load Register. The default mode
causes the timer counter to hold
when the compare value is hit. In
capture mode, configures the
timer counter to not hold the
previous capture value if a new
event occurs. The default mode
cause the timer counter to hold
the capture value until
recognized. */
#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008 /**< Enables the external input to
the timer counter. */
#define XTC_CSR_EXT_GENERATE_MASK 0x00000004 /**< Enables the external generate
output for the timer. */
#define XTC_CSR_DOWN_COUNT_MASK 0x00000002 /**< Configures the timer counter to
count down fromstart value, the
default is to count up. */
#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001 /**< Enables the timer to capture the
timer counter value when the
external capture line is asserted.
The default mode is compare mode.*/
Application program
We have taken the application program from the examples directory found in the EDK installation (..../edk91i/sw/XilinxProcessorIPLib/drivers/tmrctr_v1_00_b/examples).
XStatus TmrCtrLowLevelExample(Xuint32 TmrCtrBaseAddress, Xuint8 TmrCtrNumber)
{
Xuint32 Value;
Xuint32 ControlStatus;
Xuint32 i;
/*
* Set the master enable bit and enable hardware interrupts. We must set the
* master enable bit before enabling interrupts otherwise we will get a spurious interrrupt (IRQ goes high) ???
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK);
/*
* Enable interrupts from the timer/counter and the ETC
*/
XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_OPB_TIMER_0_INTERRUPT_MASK | XPAR_ETC_0_O_INTERRUPT_MASK);
/*
* Clear the Timer Control Status Register
*/
XTmrCtr_mSetControlStatusReg(TmrCtrBaseAddress, TmrCtrNumber,0x0);
/*
* Set the value that is loaded into the timer counter and cause it to
* be loaded into the timer counter
*/
XTmrCtr_mSetLoadReg(TmrCtrBaseAddress, TmrCtrNumber, 0x100);
XTmrCtr_mLoadTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber);
/*
* Clear the Load Timer bit in the Control Status Register
*/
ControlStatus = XTmrCtr_mGetControlStatusReg(TmrCtrBaseAddress,
TmrCtrNumber);
/*
* Setup the counter to count down and enable interrupt when counter rolls over
*/
XTmrCtr_mSetControlStatusReg(TmrCtrBaseAddress, TmrCtrNumber,
ControlStatus & (~XTC_CSR_LOAD_MASK)| XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_ENABLE_INT_MASK);
/*
* Start the timer counter such that it's decrementing.
*/
XTmrCtr_mEnable(TmrCtrBaseAddress, TmrCtrNumber);
/*
* Read the value of the timer counter and wait for an interrupt
*/
while (1)
{
/*
* If the interrupt occurred which is indicated by the global
* variable which is set in the device driver handler, then
* stop waiting
*/
Value = XTmrCtr_mGetTimerCounterReg(TmrCtrBaseAddress, TmrCtrNumber); if (InterruptProcessed)
{
break;
}
}
/*
* Disable the timer counter such that it stops incrementing
*/
XTmrCtr_mDisable(TmrCtrBaseAddress, TmrCtrNumber);
return XST_SUCCESS;
}
Simulation results
The counter will count down from 0x100 (256 decimal) to 0, when an interrupt will be generated. It takes 2590 ns from starting the timer to when the interrupt is generated. Clock frequency is 100 MHz (256*10 ns = 2560 ns).
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Posted at 07:14 am by svenand
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FPGA design from scratch. Part 41
Adding an interrupt controller
The ETC will generate an interrupt when the test has finished, if enabled (see Simvision plot). Instead of waiting a fixed time for the test to complete we could use the interrupt signal to tell the application program that the test has finished. Sounds like a good idea. Let's implement an interrupt controller to handle our interrupt. The MicroBlaze processor can handle one interrupt but we will probably have more than one interrupt in our final system.
Finding an interrupt controller
Let's try the Xilinx IP center and see what we find. The first thing I found was an application note, XAPP778 Using and Creating Interrupt-Based Systems.
As it says in the Xilinx documentation:This application note describes how to properly set up external and internal interrupts in an
embedded hardware system. Use of an interrupt controller to manage more than one interrupt
is also included. The application note discusses the software use model, including initializing
the interrupt controller and peripherals, registering the interrupt handlers, and enabling
interrupts.
Here is a definition of an interrupt taken from this application note:
Interrupts are automatic control transfers that occur as a result of an exception. An interrupt
occurs when the processor suspends execution of a program after detecting an exception. The
processor saves the suspended-program machine state and a return address into the
suspended program. This information is stored in a pair of special registers, called save/restore
registers. A predefined machine state is loaded by the processor, which transfers control to an
interrupt handler. An interrupt handler is a system-software routine that responds to the
interrupt, often by correcting the condition causing the exception. System software places
interrupt handlers at predefined addresses in physical memory and the interrupt mechanism
automatically transfers control to the appropriate handler based on the exception condition.
Because the MicroBlaze core only supports one external interrupt, designs which require more than one interrupt, must include an OPB Interrupt Controller (OPB_INTC).
 (Courtesy of Xilinx)
OPB_INTC
(Courtesy of Xilinx)
Register map
Register Name
| Abbreviation | OPB Offset
| Interrupt Status Register
| ISR | 0 (0x00)
| Interrupt Pending Register
| IPR | 4 (0x04)
| Interrupt Enable Register
| IER | 8 (ox08)
| Interrupt Acknowledge Register
| IAR | 12 (0x0c) | Set Interrupt Enable Bits
| SIE | 16 (0x10)
| Clear Interrupt Enable Bits
| CIE | 20 (0x14)
| Interrupt Vector Register
| IVR | 24 (0x18)
| Master Enable Register
| MER | 28 (0x1c)
|
We will use Xilinx Platform Studio and add the IP. For more information about adding an IP read Part 17 and Part 31 of this tutorial.
Configuring the interrupt controller
Right-click the opb_intc_0 entry in the System Assembly View and select Configure IP. It seems we don't have to configure anything. Everything is auto computed.
Making connections
We select Ports in the System Assembly View and click the plus sign to display the ports available in opb_intc_0.
We connect the IRQ output of the interrrupt controller to the interrupt input on MicroBlaze and we are done with the hardware setup. The rest is software.
Software setup
After running library generation (libgen) the intc_v1_00_c software device driver has been added to the libsrc directory. The source code has been compiled and stored in the libxil.a library.
xparameters.h
The following parameters have been added to xparameters.h:
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 1
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral OPB_INTC_0 */
#define XPAR_OPB_INTC_0_BASEADDR 0x43505000
#define XPAR_OPB_INTC_0_HIGHADDR 0x4350503F
#define XPAR_OPB_INTC_0_DEVICE_ID 0
#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000001
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x43505000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4350503F
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define XPAR_ETC_0_O_INTERRUPT_MASK 0X000001
#define XPAR_OPB_INTC_0_ETC_0_O_INTERRUPT_INTR 0
/******************************************************************/
xintc_l.h
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 28 /* Master Enable Register */
/* Bit definitions for the bits of the MER register */
#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
Generate a software interrupt
Here is an example of a c-program to setup the interrupt controller and to generate a software interrupt. We will use the software interrupt to test our interrupt handling routine. When we are satisfied, we will enable the hardware interrupt and at the same time disable all further software interrupts.
/*
* Enable interrupts for all devices that cause interrupts.
* Write to Interrupt Enable Register
*/
XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_ETC_0_O_INTERRUPT_MASK);
/*
* Set the master enable bit. Note that we do not enable hardware
* interrupts yet since we want to simulate an interrupt from software
* down below. WRite to Master Enable Register
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK);
/*
* This step is processor specific, connect the handler for the interrupt
* controller to the interrupt source for the processor. Will be added later on.
*/
// SetupInterruptSystem();
/*
* Cause (simulate) an interrupt so the handler will be called. This is
* done by writing a 1 to the interrupt status bit for the device interrupt.
* Write to Interrupt Status Register
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_ISR_OFFSET, XPAR_ETC_0_O_INTERRUPT_MASK);
Here is an Simvision plot from our simulation. We can see that the irq output signal from the interrrupt controller goes high indicating an interrupt request.
Generate a hardware interrupt
Here is an example of a c-program to setup the interrupt controller and to generate a hardware interrupt.
/*
* Enable interrupts for all devices that cause interrupts.
* Write to Interrupt Enable Register
*/
XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_ETC_0_O_INTERRUPT_MASK);
/*
* Set the master enable bit. Enable hardware interrupts.
* Write to Master Enable Register
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK);
/*
* This step is processor specific, connect the handler for the interrupt
* controller to the interrupt source for the processor. Will be added later on.
*/
// SetupInterruptSystem();
/*
* Wait for the interrupt to be processed, if the interrupt does not
* occur this loop will wait forever
*/
while (1)
{
/*
* If the interrupt occurred which is indicated by the global
* variable which is set in the device driver handler, then
* stop waiting
*/
if (InterruptProcessed)
{
break;
}
}
Here is an Simvision plot from our simulation. We can see that the irq output signal from the interrrupt controller goes high after the ETC_INTERRUPT signal goes high, indicating a hardware interrupt request.
MicroBlaze interrupt handling
As it says in the Xilinx documentation:The MicroBlaze processor supports one external interrupt source via a connection to the
Interrupt input port. The processor will only react to interrupts if the interrupt enable (IE) bit in
the machine status register (MSR) is set to 1. On an interrupt the instruction in the execution
stage will complete, while the instruction in the decode stage is replaced by a branch to the
interrupt vector (address 0x10). The interrupt return address (the PC associated with the
instruction in the decode stage at the time of the interrupt) is automatically loaded into general
purpose register R14.
In addition the processor also disables future interrupts by clearing the IE bit in the MSR. In
order for an Interrupt to interrupt the currently executing Interrupt, the interrupt handler code
must re-enable interrupts. If an OPB_INTC controller has been utilized, the INTC driver code
must be modified to re-enable interrupts.
The processor ignores interrupts, if the break in progress (BIP) bit in the MSR register is set to 1.
Enable MicroBlaze interrupt handling
We will use the following c-program function to enable MicroBlaze interrupt handling: microblaze_enable_interrupts();
MicroBlaze interrupt timing
This Simvision plot shows the MicroBlaze interrupt handling. It takes 70ns from when the ETC generates an interrupt until the MicroBlaze processor reacts.
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