New Horizons






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Table of content

New Horizons
What's new
Starting a blog
Writing a blog
I got a job

SystemC
SystemC from scratch. Part 1
SystemC from scratch. Part 2
SystemC from scratch. Part 3

ASIC/FPGA Design
Table of content
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Links
Acronyms and abbreviations
XCell Journals
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Ubuntu Linux on a MacBook
Customizing Ubuntu Linux 1
Customizing Ubuntu Linux 2
Upgrading to Ubuntu 7.04
Install Ubuntu 7.04 with VMware
Making the virtual machine run faster
Ubuntu Links
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Wireless freedom
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts
Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state


Example Files
Verilog Testbench Body
Verilog Testcase
Verilog Setup
Simulation Result File
Simulation Report File




Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice


Favorites
Adventures in ASIC
ChipHit
Computer History Museum
Community of Sweden
DeepChip
Design & Reuse
Dilbert
EDA Cafe
EDA DesignLine
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA Journal
FPGA World
MacApper
Mac geekery
Mac 2 Ubuntu
Get Perpendicular
Programmable Logic DesignLine
History of Linux
OpenCores
ORSoC
Simplehelp
SOCcentral
World of ASIC



New York City Marathon




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Nov 5, 2007
FPGA design from scratch. Part 47
EDK 9.2i has been released

I got an email from Xilinx:

Dear Valued Customer,

Thank you for choosing the Xilinx Embedded Development Kit (EDK) as your embedded hardware and software development solution for Virtex(tm)-5, Virtex-4, Virtex-II Pro and Spartan(tm) Series PowerPC(tm) and MicroBlaze(tm) processing systems. Your Xilinx EDK 9.2i software is now available for download!*

The Xilinx EDK software is built from much the same core technology as the industry's favorite FPGA design environment, Xilinx ISE(™). The graphical user interface for EDK, DesignVision Award winning Xilinx Platform Studio(tm)(XPS), is the technology that integrates all the processes from design entry to debug and verification, helping you quickly get started with your embedded designs.

Please be aware that EDK 9.2i requires a valid installation of ISE 9.2i, including ISE Service Pack 2, to function properly.

To download your software update, select the following link and use your Xilinx login to access your personalized Xilinx Electronic Fulfillment (XEF) site:

http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=esd_oms

What is new in this release

Xilinx Platform Studio (XPS) Enhancements


This release includes the following XPS enhancements:
    • Higher-performance processing systems due to:
          o New optimized processor bus infrastructure based on CoreConnect PLB v4.6.
          o Integration of MultiPort Memory Controller (MPMC3), complete with XPS configuration wizard,to easily configure high-performance memory interfaces.
          o MicroBlaze version 7, which supports the optional Memory Management Unit (MMU).
          o Updated processor IP catalog containing 50 new or redesigned IP cores, with IP optimized for new PLB v4.6 interconnect.
    • Full-access support for Spartan-3A, Spartan-3AN, and Spartan-3A DSP.
    • 64-bit Linux support.
    • EDK project file (.xmp) support in ISE. An .xmp file can now be the top-level source file in ISE.
    • Simpler Clock Generation.
    • Improved timing on reset signals in embedded design.
    • Support for 3rd party text editors.
    • Multi-processor support with mutex and mailbox pcores.

Software Development Kit Improvements

This release includes the following improvements to Platform Studio SDK:
   • Xilkernel support for run-time memory protection on
MicroBlaze using the MMU
   • 64-bit Linux Support
   • Support for Remote Debug
   • Support for Initialization of Debug Session with Data files
   • Support for Watchpoints
   • MicroBlaze GNU tools have been upgraded to new versions as follows:
          o GCC upgraded from 3.4.1 to 4.1.1
          o GDB upgraded from 5.3 to 6.5
          o Support for new MicroBlaze floating point instructions and MMU instructions
          o GCC support for DWARF2 debug format



Let's install EDK 9.2i

Before we can start to install EDK 9.2i we should have already installed ISE 9.2i. We must always use the same version of ISE and EDK.





We click on the link EDK 9.2i - Embedded Development Kit (All Platforms) to start the download. The EDK92.zip file is almost 1.5Gb.





Read
part 14 for more information about installing EDK.




Running EDK 9.2i

This wizard will help us upgrade the cores and drivers in our project.




We have to go through a number of updates.







Some of the new cores are not compatible with the older versions we are using. We will not update to these new versions.



The software device drivers have also been updated.



After we upgraded everything the ETC_system.mhs and ETC-system.mss files will be modified.




We are are ready to use EDK 9.2

When we start the bitstream generation the following error occurs:


At Local date and time: Wed Nov  7 17:55:10 2007
 make -f ETC_system.make bits started...
*********************************************
Running Xilinx Implementation tools..
*********************************************
xilperl /home/svenand/cad/edk92i/data/fpga_impl/manage_fastruntime_opt.pl -reduce_fanout no
xilperl: error while loading shared libraries: libdb-4.1.so: cannot open shared object file: No such file or directory
make:
*** [__xps/ETC_system_routed] Error 127
Done!


We are missing the libdb-4.1.so library. The easy fix is to link to the libdb-4.2.so library.

sudo ln -s /usr/lib/lib-4.2.so /usr/lib/libdb-4.1.so


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Posted at 10:12 pm by svenand

 

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