New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Bicycling
Stockholm by bike

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



If you want to be updated on this weblog Enter your email here:



rss feed



 
Saturday, September 29, 2007
FPGA design from scratch. Part 45
A computer cache

A CPU cache is a temporary storage area where frequently accessed data can be stored for rapid access. Once the data is stored in the cache, future use can be made by accessing the cached copy rather than re-fetching or recomputing the original data, so that the average access time is lower.

A cache is made up of a pool of entries. Each entry has a datum (a nugget of data) which is a copy of the datum in some backing store. Each entry also has a tag, which specifies the identity of the datum in the backing store of which the entry is a copy. When the cache client (a CPU, web browser, operating system) wishes to access a datum presumably in the backing store, it first checks the cache. If an entry can be found with a tag matching that of the desired datum, the datum in the entry is used instead. This situation is known as a cache hit. For more information about the MicroBlaze cache functionality read the MicroBlaze Processor Reference Guide.

Enabling MicroBlaze caches

To enable the instrcuction and data caches we open the MicroBlaze IP configure window and select Cache. We enable the Instruction cache and the Data cache by ticking the two check boxes.



Specify cacheable memory segment

Cache Base Address and Cache High Address determines the cacheable segment of the SDRAM. We will make the whole SDRAM cacheable setting Cache Base Address to 0x44000000 and Cache High Address to 0x47ffffff.

Instruction cache operation

For every instruction fetched, the instruction cache detects if the instruction address belongs to the cacheable segment. If the address is non-cacheable, the cache controller ignores the instruction and lets the OPB or LMB complete the request. If the address is cacheable, a lookup is performed on the tag memory to check if the requested address is currently cached. The lookup is successful if: the word and line valid bits are set, and the tag address matches the instruction address tag segment. On a cache miss, the cache controller requests the new instruction over the instruction CacheLink (IXCL) interface, and waits for the memory controller to return the associated cache line.

Data cache operation

The MicroBlaze data cache implements a write-through protocol. Provided that the cache is enabled, a store to an address within the cacheable range generates an equivalent byte, halfword, or word write over the data CacheLink (DXCL) to external memory. The write also updates the cached data if the target address word is in the cache (i.e. the write is a cache-hit). A write cache-miss does not load the associated cache line into the cache. Provided that the cache is enabled a load from an address within the cacheable range triggers a check to determine if the requested data is currently cached. If it is (i.e. on a cache-hit) the requested data is retrieved from the cache. If not (i.e. on a cache-miss) the address is requested over data CacheLink (DXCL), and the processor pipeline stalls until the cache line associated to the requested address is returned from the external memory controller.

Xilinx CacheLink (XCL)

Xilinx CacheLink (XCL) is a high performance solution for external memory accesses. The MicroBlaze CacheLink interface is designed to connect directly to a memory controller with integrated FSL buffers, e.g. the
MCH OPB DDR SDRAM controller. This method has the lowest latency and minimal number of instantiations.

The interface is only available on MicroBlaze when caches are enabled. It is legal to use a CacheLink cache on the instruction side or the data side without caching the other. Memory locations outside the cacheable range are accessed over OPB or LMB. Cached memory range is accessed over OPB whenever the caches are software disabled (i.e. MSR[DCE]=0 or MSR[ICE]=0).



Adding the MCH_OPB_DDR_SDRAM controller

We will replace the current SDRAM controller OPB_DDR_SDRAM with the new MCH_OPB_DDR_SDRAM controller.



                                                                                                                                  
(Courtesy of Xilinx)




Connect IXCL and DXCL

We connect the MCH0 to the MicroBlaze IXCL port and the MCH1 to the MicroBlaze DXCL port.



Connecting ports

There are two new ports found in the mch_opb_ddr peripheral, DDR_Sleep and DDR_WakeUp.

Rising edge on DDR_Sleep enters the DDR SDRAM self refresh mode. A minimum period of 50uS after the assertion of DDR_Sleep is required before MCH_OPB_Rst can be asserted. We keep this signal low.

DDR_WakeUp indicates whether the DDR SDRAM must go through the power-up initialization after reset, or if only the sequence to exit the self refresh mode needs to be executed. This signal is sampled when reset negates and therefore should be asserted before MCH_OPB_Rst negates. We keep this signal low.


ETC_system.mhs

Here is the mch_opb_ddr setup part.

BEGIN mch_opb_ddr
 PARAMETER INSTANCE = mch_opb_ddr_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_DDR_DWIDTH = 32
 PARAMETER C_DDR_TMRD = 14997
 PARAMETER C_MEM0_BASEADDR = 0x44000000
 PARAMETER C_MEM0_HIGHADDR = 0x47ffffff
 BUS_INTERFACE MCH0 = microblaze_0_IXCL
 BUS_INTERFACE MCH1 = microblaze_0_DXCL
 BUS_INTERFACE SOPB = mb_opb
 PORT Device_Clk = sys_clk_s
 PORT Device_Clk_n = sys_clk_n_s
 PORT Device_Clk90_in = clk_90_s
 PORT Device_Clk90_in_n = clk_90_n_s
 PORT DDR_Clk90_in = ddr_clk_90_s
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
 PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk
 PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn
 PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE
 PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn
 PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn
 PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn
 PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn
 PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr
 PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr
 PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ
 PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS
 PORT DDR_Sleep = net_gnd
 PORT DDR_WakeUp = net_gnd
END



Top  Previous  Next



Posted at 17:54 by

 

Leave a Comment:

Name


Homepage (optional)


Comments




Previous Entry Home Next Entry