A CPU cache is a temporary storage area where frequently accessed data can be stored for rapid access. Once the data is stored in the cache, future use can be made by accessing the cached copy rather than re-fetching or recomputing the original data, so that the average access time is lower.
A cache is made up of a pool of entries. Each entry has a datum (a nugget of data) which is a copy of the datum in some backing store. Each entry also has a tag, which specifies the identity of the datum in the backing store of which the entry is a copy. When the cache client (a CPU, web browser, operating system) wishes to access a datum presumably in the backing store, it first checks the cache. If an entry can be found with a tag matching that of the desired datum, the datum in the entry is used instead. This situation is known as a cache hit. For more information about the MicroBlaze cache functionality read the MicroBlaze Processor Reference Guide.
Enabling MicroBlaze caches
To enable the instrcuction and data caches we open the MicroBlaze IP configure window and select Cache. We enable the Instruction cache and the Data cache by ticking the two check boxes.
Specify cacheable memory segment
Cache Base Address and Cache High Address determines the cacheable segment of the SDRAM. We will make the whole SDRAM cacheable setting Cache Base Address to 0x44000000 and Cache High Address to 0x47ffffff.
Instruction cache operation
For every instruction fetched, the instruction cache detects if the instruction address belongs to the cacheable segment. If the address is non-cacheable, the cache controller ignores the instruction and lets the OPB or LMB complete the request. If the address is cacheable, a lookup is performed on the tag memory to check if the requested address is currently cached. The lookup is successful if: the word and line valid bits are set, and the tag address matches the instruction address tag segment. On a cache miss, the cache controller requests the new instruction over the instruction CacheLink (IXCL) interface, and waits for the memory controller to return the associated cache line.
Data cache operation
The MicroBlaze data cache implements a write-through protocol. Provided that the cache is enabled, a store to an address within the cacheable range generates an equivalent byte, halfword, or word write over the data CacheLink (DXCL) to external memory. The write also updates the cached data if the target address word is in the cache (i.e. the write is a cache-hit). A write cache-miss does not load the associated cache line into the cache. Provided that the cache is enabled a load from an address within the cacheable range triggers a check to determine if the requested data is currently cached. If it is (i.e. on a cache-hit) the requested data is retrieved from the cache. If not (i.e. on a cache-miss) the address is requested over data CacheLink (DXCL), and the processor pipeline stalls until the cache line associated to the requested address is returned from the external memory controller.
Xilinx CacheLink (XCL)
Xilinx CacheLink (XCL) is a high performance solution for external memory accesses. The MicroBlaze CacheLink interface is designed to connect directly to a memory controller with integrated FSL buffers, e.g. the MCH OPB DDR SDRAM controller. This method has the lowest latency and minimal number of instantiations.
The interface is only available on MicroBlaze when caches are enabled. It is legal to use a CacheLink cache on the instruction side or the data side without caching the other. Memory locations outside the cacheable range are accessed over OPB or LMB. Cached memory range is accessed over OPB whenever the caches are software disabled (i.e. MSR[DCE]=0 or MSR[ICE]=0).
Adding the MCH_OPB_DDR_SDRAM controller
We will replace the current SDRAM controller OPB_DDR_SDRAM with the new MCH_OPB_DDR_SDRAM controller.
(Courtesy of Xilinx)
Connect IXCL and DXCL
We connect the MCH0 to the MicroBlaze IXCL port and the MCH1 to the MicroBlaze DXCL port.
Connecting ports
There are two new ports found in the mch_opb_ddr peripheral, DDR_Sleep and DDR_WakeUp.
Rising edge on DDR_Sleep enters the DDR SDRAM self refresh mode. A minimum period of 50uS after the assertion of DDR_Sleep is required before MCH_OPB_Rst can be asserted. We keep this signal low.
DDR_WakeUp indicates whether the DDR SDRAM must go through the power-up initialization after reset, or if only the sequence to exit the self refresh mode needs to be executed. This signal is sampled when reset negates and therefore should be asserted before MCH_OPB_Rst negates. We keep this signal low.
ETC_system.mhs
Here is the mch_opb_ddr setup part.
BEGIN mch_opb_ddr PARAMETER INSTANCE = mch_opb_ddr_0 PARAMETER HW_VER = 1.00.c PARAMETER C_DDR_DWIDTH = 32 PARAMETER C_DDR_TMRD = 14997 PARAMETER C_MEM0_BASEADDR = 0x44000000 PARAMETER C_MEM0_HIGHADDR = 0x47ffffff BUS_INTERFACE MCH0 = microblaze_0_IXCL BUS_INTERFACE MCH1 = microblaze_0_DXCL BUS_INTERFACE SOPB = mb_opb PORT Device_Clk = sys_clk_s PORT Device_Clk_n = sys_clk_n_s PORT Device_Clk90_in = clk_90_s PORT Device_Clk90_in_n = clk_90_n_s PORT DDR_Clk90_in = ddr_clk_90_s PORT DDR_Clk90_in_n = ddr_clk_90_n_s PORT DDR_Clk = fpga_0_DDR_SDRAM_64Mx32_DDR_Clk PORT DDR_Clkn = fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn PORT DDR_CKE = fpga_0_DDR_SDRAM_64Mx32_DDR_CKE PORT DDR_CSn = fpga_0_DDR_SDRAM_64Mx32_DDR_CSn PORT DDR_RASn = fpga_0_DDR_SDRAM_64Mx32_DDR_RASn PORT DDR_CASn = fpga_0_DDR_SDRAM_64Mx32_DDR_CASn PORT DDR_WEn = fpga_0_DDR_SDRAM_64Mx32_DDR_WEn PORT DDR_DM = fpga_0_DDR_SDRAM_64Mx32_DDR_DM PORT DDR_BankAddr = fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr PORT DDR_Addr = fpga_0_DDR_SDRAM_64Mx32_DDR_Addr PORT DDR_DQ = fpga_0_DDR_SDRAM_64Mx32_DDR_DQ PORT DDR_DQS = fpga_0_DDR_SDRAM_64Mx32_DDR_DQS PORT DDR_Sleep = net_gnd PORT DDR_WakeUp = net_gnd END
