New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.

View Sven Andersson's profile on LinkedIn

Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Cobra Command Tool
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Wednesday, November 22, 2006
A hardware designer's best friend
When designing an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) you use a hardware description language (HDL) like Verilog or VHDL. To verify that your design is correct you need a hardware simulator. To find a hardware simulator you have to contact a company that makes computer-aided design (CAD) tools. The three major companies developing CAD tools are Cadence, Mentor Graphics and Synopsys. Cadence has the Incisive Functional Verification Platform, Mentor has the Questa Scalable Verification, and Synopsys has the Discovery Verification Platform.
Ever since I started as an ASIC designer in 1990 I have been using Cadence tools. Back then Verilog-XL was one of the few hardware modeling language available and Cadence owned Verilog-XL.
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
Now it's time to install the Cadence hardware simulator. Let's go to the Cadence
software download page. Before you can start the download you have to register as a Cadence user. To register you must already have a Cadence product installed. To run the simulator you also need an evaluation license. There is no freeware when it comes to CAD software but try to convince Cadence that you are a presumptive buyer of their software and they may give you access to their download page and an evaluation license. After signing up, go to the Electronic Distribution page and follow these steps:
  1. Go to the Linux page.
  2. Download and install the program InstallScape. InstallScape lets you download and install selected Cadence products in a release in a single step. Create an install directory and download the compressed tar file to this directory. Use the command <tar -zxvf Iscape03.40-s012lnx86.t.z> to unzip and unpack the file at the same time.
  3. Before starting the installation create two directories, one to temporarily store the downloaded files (archive) and one directory where the final installation will be stored.
  4. Start Iscape in a terminal window using the script file ../iscape/bin/iscape.sh
  5. Click <Select Release> and choose a server near you. Protocol should be <http>.
  6. Click the <Select Release> button. Enter user name and password.
  7. Select Release and Platform. Click the Linux tab and select IUS58 or later from the list. Click next.
  8. Select Release : What do you want to do and select <Download a Release>. Click next.
  9. Select Release : Select Source Site to Download. Select one of the releases from the list. Click the download button.
  10. Download : What do you want to do. Select <Save Archive and Install>. Click next.
  11. Download : Save Archive & Install. Choose <I will select products manually>. Click next.
  12. Download : Specify Archive Directory. Select the archive directory. Click next.
  13. Download : Specify Install Directory. Select the install directory. Click next.
  14. Select Product. Select the full Incisive Unified Simulator (29300) from the list. Click next.
  15. Start the installation. You will need 2.7 GB of disk space for the archive and the install directories. When the installation has finished you can delete the archive directory. With a high speed connection the installation will take about 30 minutes. When finished quit the window.
  16. Before you can start to use the simulator it must be configured. Select <Configure Product> from the main Installscape window. Select <Install Directory> and click next button.
  17. Select product <29300 Incisive Unified Simulator> and click next. The configuration script will start and you have to enter IAGREE before it kicks off. When finished close the report window. The installation is now finished and you can exit InstallScape.
  18. To find out if the installation was successful you can start the verilog compiler <ncvlog>. Use the command install_dir/tools/bin/ncvlog. The compiler should start and print the following message:
    ncvlog : 05.82-p002 : ......
    Usage : ncvlog [options] source.file ....
The simulator will not start without a license file. Cadence uses the FLEXlm software license manager and you have to have the license  manager daemon running before starting the simulator (ncsim). You can ask Cadence for an evaluation license file that will last for 45 days. To generate a license file that will only run on your computer (node-locked) they need the MAC address of your machine. To find out the MAC address, execute the following command in a Linux terminal window.
<sudo ifconfig -a>. Look for eth0 and the HWaddr. The MAC address will look like this 00:91:B8:DF:D3:C0. Send the MAC address to Cadence and they will generate a license file for you. When you receive the license file you have to make two changes to the file. The file is in ASCII format and can be edited with a standard text editor. The first three lines of the file will look like this:
SERVER Cadence-SERVER 0091B8DFD3C0 5280
DAEMON cdslmd ./cdslmd
USE_SERVER
........
Replace "Cadence-SERVER" with the hostname of your machine. To find out the hostname execute the following command in a terminal window: <hostname>
Replace ./cdslmd with the full path name of the license daemon program located in the bin directory of the IUS58 installation.
My license file looks like this after the changes:
SERVER svenand-desktop 0091B8DFD3C0 5280
DAEMON cdslmd /home/svenand/cad/Cadence/ius58/tools/bin/cdslmd
USE_SERVER
.........
After editing the license file you start the license daemon using the following command:
install_dir/tools/bin/lmgrd -c license_file
When the license daemon is up and running you can start using the simulator. Good luck.
Don't forget to define the environment variable CDS_LIC_FILE before starting. Use the following command, replacing <hostname> with the host name of your host:
setenv CDS_LIC_FILE 5280@hostname (csh and tcsh)
export CDS_LIC_FILE=5280@hostname (bash)
or
setenv CDS_LIC_FILE license_file
export CDS_LIC_FILE=license_file



The picture shows a screenshot from my MacBook running Mac OS X with
Parallels Desktop installed. The virtual machine has Ubuntu Linux booted. In the Ubuntu Linux OS the Cadence waveform viewer Simvision is running. The same thing goes for VMware Fusion.

Top


Posted at 07:37 by svenand

Svenand
April 22, 2014   08:01 PM PDT
 
Hi Dan,

You can use Icarus Verilog. http://iverilog.icarus.com/

Sven
Dan Gabbay
April 22, 2014   05:28 PM PDT
 
Date: Apr. 22, 2014

I have worked as an FPGA/ ASIC design more than ten years ago and also used Verilog XL and other simulators. I would like to go back to it if possible…
My question is, is it possible to find a free Verilog simulator with limited capabilities (say student version) but for unlimited time (45 days is not enough)?

Thank you,
Dan Gabbay
 

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