New Horizons






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Table of content

New Horizons
What's new
Starting a blog
Writing a blog
I got a job

SystemC
SystemC from scratch. Part 1
SystemC from scratch. Part 2
SystemC from scratch. Part 3

ASIC/FPGA Design
Table of content
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Links
Acronyms and abbreviations
XCell Journals
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Ubuntu Linux on a MacBook
Customizing Ubuntu Linux 1
Customizing Ubuntu Linux 2
Upgrading to Ubuntu 7.04
Install Ubuntu 7.04 with VMware
Making the virtual machine run faster
Ubuntu Links
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Wireless freedom
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts
Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state


Example Files
Verilog Testbench Body
Verilog Testcase
Verilog Setup
Simulation Result File
Simulation Report File




Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice


Favorites
Adventures in ASIC
ChipHit
Computer History Museum
Community of Sweden
DeepChip
Design & Reuse
Dilbert
EDA Cafe
EDA DesignLine
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA Journal
FPGA World
MacApper
Mac geekery
Mac 2 Ubuntu
Get Perpendicular
Programmable Logic DesignLine
History of Linux
OpenCores
ORSoC
Simplehelp
SOCcentral
World of ASIC



New York City Marathon




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Nov 22, 2006
A hardware designer's best friend
When designing an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) you use a hardware description language (HDL) like Verilog or VHDL. To verify that your design is correct you need a hardware simulator. To find a hardware simulator you have to contact a company that makes computer-aided design (CAD) tools. The three major companies developing CAD tools are Cadence, Mentor Graphics and Synopsys. Cadence has the Incisive Functional Verification Platform, Mentor has the Questa Scalable Verification, and Synopsys has the Discovery Verification Platform.
Ever since I started as an ASIC designer in 1990 I have been using Cadence tools. Back then Verilog-XL was one of the few hardware modeling language available and Cadence owned Verilog-XL.
With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.
Now it's time to install the Cadence hardware simulator. Let's go to the Cadence
software download page. Before you can start the download you have to register as a Cadence user. To register you must already have a Cadence product installed. To run the simulator you also need an evaluation license. There is no freeware when it comes to CAD software but try to convince Cadence that you are a presumptive buyer of their software and they may give you access to their download page and an evaluation license. After signing up, go to the Electronic Distribution page and follow these steps:
  1. Go to the Linux page.
  2. Download and install the program InstallScape. InstallScape lets you download and install selected Cadence products in a release in a single step. Create an install directory and download the compressed tar file to this directory. Use the command <tar -zxvf Iscape03.40-s012lnx86.t.z> to unzip and unpack the file at the same time.
  3. Before starting the installation create two directories, one to temporarily store the downloaded files (archive) and one directory where the final installation will be stored.
  4. Start Iscape in a terminal window using the script file ../iscape/bin/iscape.sh
  5. Click <Select Release> and choose a server near you. Protocol should be <http>.
  6. Click the <Select Release> button. Enter user name and password.
  7. Select Release and Platform. Click the Linux tab and select IUS58 or later from the list. Click next.
  8. Select Release : What do you want to do and select <Download a Release>. Click next.
  9. Select Release : Select Source Site to Download. Select one of the releases from the list. Click the download button.
  10. Download : What do you want to do. Select <Save Archive and Install>. Click next.
  11. Download : Save Archive & Install. Choose <I will select products manually>. Click next.
  12. Download : Specify Archive Directory. Select the archive directory. Click next.
  13. Download : Specify Install Directory. Select the install directory. Click next.
  14. Select Product. Select the full Incisive Unified Simulator (29300) from the list. Click next.
  15. Start the installation. You will need 2.7 GB of disk space for the archive and the install directories. When the installation has finished you can delete the archive directory. With a high speed connection the installation will take about 30 minutes. When finished quit the window.
  16. Before you can start to use the simulator it must be configured. Select <Configure Product> from the main Installscape window. Select <Install Directory> and click next button.
  17. Select product <29300 Incisive Unified Simulator> and click next. The configuration script will start and you have to enter IAGREE before it kicks off. When finished close the report window. The installation is now finished and you can exit InstallScape.
  18. To find out if the installation was successful you can start the verilog compiler <ncvlog>. Use the command install_dir/tools/bin/ncvlog. The compiler should start and print the following message:
    ncvlog : 05.82-p002 : ......
    Usage : ncvlog [options] source.file ....
The simulator will not start without a license file. Cadence uses the FLEXlm software license manager and you have to have the license  manager daemon running before starting the simulator (ncsim). You can ask Cadence for an evaluation license file that will last for 45 days. To generate a license file that will only run on your computer (node-locked) they need the MAC address of your machine. To find out the MAC address, execute the following command in a Linux terminal window.
<sudo ifconfig -a>. Look for eth0 and the HWaddr. The MAC address will look like this 00:91:B8:DF:D3:C0. Send the MAC address to Cadence and they will generate a license file for you. When you receive the license file you have to make two changes to the file. The file is in ASCII format and can be edited with a standard text editor. The first three lines of the file will look like this:
SERVER Cadence-SERVER 0091B8DFD3C0 5280
DAEMON cdslmd ./cdslmd
USE_SERVER
........
Replace "Cadence-SERVER" with the hostname of your machine. To find out the hostname execute the following command in a terminal window: <hostname>
Replace ./cdslmd with the full path name of the license daemon program located in the bin directory of the IUS58 installation.
My license file looks like this after the changes:
SERVER svenand-desktop 0091B8DFD3C0 5280
DAEMON cdslmd /home/svenand/cad/Cadence/ius58/tools/bin/cdslmd
USE_SERVER
.........
After editing the license file you start the license daemon using the following command:
install_dir/tools/bin/lmgrd -c license_file
When the license daemon is up and running you can start using the simulator. Good luck.
Don't forget to define the environment variable CDS_LIC_FILE before starting. Use the following command, replacing <hostname> with the host name of your host:
setenv CDS_LIC_FILE 5280@hostname (csh and tcsh)
export CDS_LIC_FILE=5280@hostname (bash)
or
setenv CDS_LIC_FILE license_file
export CDS_LIC_FILE=license_file



The picture shows a screenshot from my MacBook running Mac OS X with
Parallels Desktop installed. The virtual machine has Ubuntu Linux booted. In the Ubuntu Linux OS the Cadence waveform viewer Simvision is running. The same thing goes for VMware Fusion.

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Posted at 07:37 am by svenand

 

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