FPGA design from scratch. Part 41
Adding an interrupt controller
The ETC will generate an interrupt when the test has finished, if enabled (see Simvision plot). Instead of waiting a fixed time for the test to complete we could use the interrupt signal to tell the application program that the test has finished. Sounds like a good idea. Let's implement an interrupt controller to handle our interrupt. The MicroBlaze processor can handle one interrupt but we will probably have more than one interrupt in our final system.
Finding an interrupt controller
Let's try the Xilinx IP center and see what we find. The first thing I found was an application note, XAPP778 Using and Creating Interrupt-Based Systems.
As it says in the Xilinx documentation:This application note describes how to properly set up external and internal interrupts in an
embedded hardware system. Use of an interrupt controller to manage more than one interrupt
is also included. The application note discusses the software use model, including initializing
the interrupt controller and peripherals, registering the interrupt handlers, and enabling
interrupts.
Here is a definition of an interrupt taken from this application note:
Interrupts are automatic control transfers that occur as a result of an exception. An interrupt
occurs when the processor suspends execution of a program after detecting an exception. The
processor saves the suspended-program machine state and a return address into the
suspended program. This information is stored in a pair of special registers, called save/restore
registers. A predefined machine state is loaded by the processor, which transfers control to an
interrupt handler. An interrupt handler is a system-software routine that responds to the
interrupt, often by correcting the condition causing the exception. System software places
interrupt handlers at predefined addresses in physical memory and the interrupt mechanism
automatically transfers control to the appropriate handler based on the exception condition.
Because the MicroBlaze core only supports one external interrupt, designs which require more than one interrupt, must include an OPB Interrupt Controller (OPB_INTC).
(Courtesy of Xilinx)
OPB_INTC
(Courtesy of Xilinx)
Register map
Register Name
| Abbreviation | OPB Offset
|
Interrupt Status Register
| ISR | 0 (0x00)
|
Interrupt Pending Register
| IPR | 4 (0x04)
|
Interrupt Enable Register
| IER | 8 (ox08)
|
Interrupt Acknowledge Register
| IAR | 12 (0x0c) |
Set Interrupt Enable Bits
| SIE | 16 (0x10)
|
Clear Interrupt Enable Bits
| CIE | 20 (0x14)
|
Interrupt Vector Register
| IVR | 24 (0x18)
|
Master Enable Register
| MER | 28 (0x1c)
|
We will use Xilinx Platform Studio and add the IP. For more information about adding an IP read Part 17 and Part 31 of this tutorial.
Configuring the interrupt controller
Right-click the opb_intc_0 entry in the System Assembly View and select Configure IP. It seems we don't have to configure anything. Everything is auto computed.
Making connections
We select Ports in the System Assembly View and click the plus sign to display the ports available in opb_intc_0.
We connect the IRQ output of the interrrupt controller to the interrupt input on MicroBlaze and we are done with the hardware setup. The rest is software.
Software setup
After running library generation (libgen) the intc_v1_00_c software device driver has been added to the libsrc directory. The source code has been compiled and stored in the libxil.a library.
xparameters.h
The following parameters have been added to xparameters.h:
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 1
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral OPB_INTC_0 */
#define XPAR_OPB_INTC_0_BASEADDR 0x43505000
#define XPAR_OPB_INTC_0_HIGHADDR 0x4350503F
#define XPAR_OPB_INTC_0_DEVICE_ID 0
#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000001
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0x43505000
#define XPAR_INTC_SINGLE_HIGHADDR 0x4350503F
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
#define XPAR_ETC_0_O_INTERRUPT_MASK 0X000001
#define XPAR_OPB_INTC_0_ETC_0_O_INTERRUPT_INTR 0
/******************************************************************/
xintc_l.h
#define XIN_ISR_OFFSET 0 /* Interrupt Status Register */
#define XIN_IPR_OFFSET 4 /* Interrupt Pending Register */
#define XIN_IER_OFFSET 8 /* Interrupt Enable Register */
#define XIN_IAR_OFFSET 12 /* Interrupt Acknowledge Register */
#define XIN_SIE_OFFSET 16 /* Set Interrupt Enable Register */
#define XIN_CIE_OFFSET 20 /* Clear Interrupt Enable Register */
#define XIN_IVR_OFFSET 24 /* Interrupt Vector Register */
#define XIN_MER_OFFSET 28 /* Master Enable Register */
/* Bit definitions for the bits of the MER register */
#define XIN_INT_MASTER_ENABLE_MASK 0x1UL
#define XIN_INT_HARDWARE_ENABLE_MASK 0x2UL /* once set cannot be cleared */
Generate a software interrupt
Here is an example of a c-program to setup the interrupt controller and to generate a software interrupt. We will use the software interrupt to test our interrupt handling routine. When we are satisfied, we will enable the hardware interrupt and at the same time disable all further software interrupts.
/*
* Enable interrupts for all devices that cause interrupts.
* Write to Interrupt Enable Register
*/
XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_ETC_0_O_INTERRUPT_MASK);
/*
* Set the master enable bit. Note that we do not enable hardware
* interrupts yet since we want to simulate an interrupt from software
* down below. WRite to Master Enable Register
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK);
/*
* This step is processor specific, connect the handler for the interrupt
* controller to the interrupt source for the processor. Will be added later on.
*/
// SetupInterruptSystem();
/*
* Cause (simulate) an interrupt so the handler will be called. This is
* done by writing a 1 to the interrupt status bit for the device interrupt.
* Write to Interrupt Status Register
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_ISR_OFFSET, XPAR_ETC_0_O_INTERRUPT_MASK);
Here is an Simvision plot from our simulation. We can see that the irq output signal from the interrrupt controller goes high indicating an interrupt request.
Generate a hardware interrupt
Here is an example of a c-program to setup the interrupt controller and to generate a hardware interrupt.
/*
* Enable interrupts for all devices that cause interrupts.
* Write to Interrupt Enable Register
*/
XIntc_mEnableIntr(XPAR_OPB_INTC_0_BASEADDR, XPAR_ETC_0_O_INTERRUPT_MASK);
/*
* Set the master enable bit. Enable hardware interrupts.
* Write to Master Enable Register
*/
XIntc_Out32(XPAR_OPB_INTC_0_BASEADDR + XIN_MER_OFFSET, XIN_INT_MASTER_ENABLE_MASK | XIN_INT_HARDWARE_ENABLE_MASK);
/*
* This step is processor specific, connect the handler for the interrupt
* controller to the interrupt source for the processor. Will be added later on.
*/
// SetupInterruptSystem();
/*
* Wait for the interrupt to be processed, if the interrupt does not
* occur this loop will wait forever
*/
while (1)
{
/*
* If the interrupt occurred which is indicated by the global
* variable which is set in the device driver handler, then
* stop waiting
*/
if (InterruptProcessed)
{
break;
}
}
Here is an Simvision plot from our simulation. We can see that the irq output signal from the interrrupt controller goes high after the ETC_INTERRUPT signal goes high, indicating a hardware interrupt request.
MicroBlaze interrupt handling
As it says in the Xilinx documentation:The MicroBlaze processor supports one external interrupt source via a connection to the
Interrupt input port. The processor will only react to interrupts if the interrupt enable (IE) bit in
the machine status register (MSR) is set to 1. On an interrupt the instruction in the execution
stage will complete, while the instruction in the decode stage is replaced by a branch to the
interrupt vector (address 0x10). The interrupt return address (the PC associated with the
instruction in the decode stage at the time of the interrupt) is automatically loaded into general
purpose register R14.
In addition the processor also disables future interrupts by clearing the IE bit in the MSR. In
order for an Interrupt to interrupt the currently executing Interrupt, the interrupt handler code
must re-enable interrupts. If an OPB_INTC controller has been utilized, the INTC driver code
must be modified to re-enable interrupts.
The processor ignores interrupts, if the break in progress (BIP) bit in the MSR register is set to 1.
Enable MicroBlaze interrupt handling
We will use the following c-program function to enable MicroBlaze interrupt handling: microblaze_enable_interrupts();
MicroBlaze interrupt timing
This Simvision plot shows the MicroBlaze interrupt handling. It takes 70ns from when the ETC generates an interrupt until the MicroBlaze processor reacts.
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Posted at 01:59 pm by
svenand
