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Table of content

New Horizons
What's new
Starting a blog
Writing a blog
I got a job

SystemC
SystemC from scratch. Part 1
SystemC from scratch. Part 2
SystemC from scratch. Part 3

ASIC/FPGA Design
Table of content
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Links
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XCell Journals
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Installing Ubuntu Linux on a MacBook
Customizing Ubuntu Linux 1
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Upgrading to Ubuntu 7.04
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Ubuntu Links
A processor benchmark
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Jun 19, 2007
FPGA design from scratch. Part 36
The LCD drivers (once more)

Now it's time to return to the LCD driver application program again. We will start by running a simulation to find out how everything is connected. Let's use a really simple program.

int main(void) {

    XStatus Status;
   
    // Initialize the GPIO component
    Status = XGpio_Initialize(&GpioLCD, GPIO_LCD_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
 
    // Set the direction for all bits to be outputs
    XGpio_SetDataDirection(&GpioLCD,    LCD_CHANNEL, 0x00);  
 
    // Display one character
    XromWriteData(0x6,0x1);


    return XST_SUCCESS;
   
    }


Here is the simulation waveform plot showing the GPIO bus connected to the LCD.



From this plot we can find out how the GPIO signals should be connected to the LCD driver. It was not the way we thought. Here is what it should look like.

 Signal Name
 Description  GPIO pin
FPGA pin location 
LCD_E Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled

0 AE13
LCD_RS Register Select
0:Instruction register during write
1:Data for read or write operation
1
AC17
LCD_RW Read/Write Control
0:Write, LCD accepts data
1:Read, LCD presents data
2 AB17
LCD_DB7 Data Bus bit 7
3 AF12
LDC_DB6  Data Bus bit 6
4 AE12
LCD_DB5 Data Bus bit 5
5 AC10
LCD_DB4 Data Bus bit 4
AB10

Editing the user constraints file

We will change the pin mapping in the ETC_system.ucf file.

#### Module LCD_16x2 constraints

NET LCD_16x2_GPIO_IO_pin<0> LOC="AE13";
NET LCD_16x2_GPIO_IO_pin<0> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<0> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<0> TIG;
NET LCD_16x2_GPIO_IO_pin<1> LOC=AC17;
NET LCD_16x2_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<1> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<1> TIG;
NET LCD_16x2_GPIO_IO_pin<2> LOC=AB17;
NET LCD_16x2_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<2> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<2> TIG;
NET LCD_16x2_GPIO_IO_pin<3> LOC=AF12;
NET LCD_16x2_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<3> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<3> TIG;
NET LCD_16x2_GPIO_IO_pin<4> LOC=AE12;
NET LCD_16x2_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<4> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<4> TIG;
NET LCD_16x2_GPIO_IO_pin<5> LOC=AC10;
NET LCD_16x2_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<5> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<5> TIG;
NET LCD_16x2_GPIO_IO_pin<6> LOC=AB10;
NET LCD_16x2_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<6> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<6> TIG;

Generate a new bitstream

We use the menu command Hardware->Generate Bitstream in Xilinx Platform Studio to
generate a new bitstream.

Device configuration

We use the menu command Device Configuration->Download Bitstream to configure the FPGA.

Application program


Here is our "Hello World" program again.

int main(void) {

    XStatus Status;
   
    // Initialize the GPIO component
    Status = XGpio_Initialize(&GpioLCD, GPIO_LCD_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
 
    // Set the direction for all bits to be outputs
    XGpio_SetDataDirection(&GpioLCD,LCD_CHANNEL, 0x00);  

    //Initialize LCD
    XromLCDInit();
    XromLCDOn();
    XromLCDClear();
    XromLCDPrintString("Hello World");

    return XST_SUCCESS;
   
    }

We compile and link the program in Xilinx Platform Studio SDK and use the command Device Configuration->Program Hardware to load and execute the program. We keep staring at the LCD display and after a few seconds it displays:

                         
Hello World


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Posted at 01:35 pm by svenand

 

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