New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.

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Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Cobra Command Tool
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Tuesday, June 19, 2007
FPGA design from scratch. Part 36
The LCD drivers (once more)

Now it's time to return to the LCD driver application program again. We will start by running a simulation to find out how everything is connected. Let's use a really simple program.

int main(void) {

    XStatus Status;
   
    // Initialize the GPIO component
    Status = XGpio_Initialize(&GpioLCD, GPIO_LCD_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
 
    // Set the direction for all bits to be outputs
    XGpio_SetDataDirection(&GpioLCD,    LCD_CHANNEL, 0x00);  
 
    // Display one character
    XromWriteData(0x6,0x1);


    return XST_SUCCESS;
   
    }


Here is the simulation waveform plot showing the GPIO bus connected to the LCD.



From this plot we can find out how the GPIO signals should be connected to the LCD driver. It was not the way we thought. Here is what it should look like.

 Signal Name
 Description  GPIO pin
FPGA pin location 
LCD_E Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled

0 AE13
LCD_RS Register Select
0:Instruction register during write
1:Data for read or write operation
1
AC17
LCD_RW Read/Write Control
0:Write, LCD accepts data
1:Read, LCD presents data
2 AB17
LCD_DB7 Data Bus bit 7
3 AF12
LDC_DB6  Data Bus bit 6
4 AE12
LCD_DB5 Data Bus bit 5
5 AC10
LCD_DB4 Data Bus bit 4
AB10

Editing the user constraints file

We will change the pin mapping in the ETC_system.ucf file.

#### Module LCD_16x2 constraints

NET LCD_16x2_GPIO_IO_pin<0> LOC="AE13";
NET LCD_16x2_GPIO_IO_pin<0> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<0> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<0> TIG;
NET LCD_16x2_GPIO_IO_pin<1> LOC=AC17;
NET LCD_16x2_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<1> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<1> TIG;
NET LCD_16x2_GPIO_IO_pin<2> LOC=AB17;
NET LCD_16x2_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<2> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<2> TIG;
NET LCD_16x2_GPIO_IO_pin<3> LOC=AF12;
NET LCD_16x2_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<3> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<3> TIG;
NET LCD_16x2_GPIO_IO_pin<4> LOC=AE12;
NET LCD_16x2_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<4> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<4> TIG;
NET LCD_16x2_GPIO_IO_pin<5> LOC=AC10;
NET LCD_16x2_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<5> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<5> TIG;
NET LCD_16x2_GPIO_IO_pin<6> LOC=AB10;
NET LCD_16x2_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;
NET LCD_16x2_GPIO_IO_pin<6> PULLDOWN;
NET LCD_16x2_GPIO_IO_pin<6> TIG;

Generate a new bitstream

We use the menu command Hardware->Generate Bitstream in Xilinx Platform Studio to
generate a new bitstream.

Device configuration

We use the menu command Device Configuration->Download Bitstream to configure the FPGA.

Application program


Here is our "Hello World" program again.

int main(void) {

    XStatus Status;
   
    // Initialize the GPIO component
    Status = XGpio_Initialize(&GpioLCD, GPIO_LCD_DEVICE_ID);
    if (Status != XST_SUCCESS) return XST_FAILURE;
 
    // Set the direction for all bits to be outputs
    XGpio_SetDataDirection(&GpioLCD,LCD_CHANNEL, 0x00);  

    //Initialize LCD
    XromLCDInit();
    XromLCDOn();
    XromLCDClear();
    XromLCDPrintString("Hello World");

    return XST_SUCCESS;
   
    }

We compile and link the program in Xilinx Platform Studio SDK and use the command Device Configuration->Program Hardware to load and execute the program. We keep staring at the LCD display and after a few seconds it displays:

                         
Hello World


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