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My name is Sven Andersson and I
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system design, implemented in ASIC
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Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
Evaluation kits and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
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Installing Cobra Command Tool
A processor benchmark
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100 Power Tips for FPGA Designers

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Thursday, July 12, 2007
FPGA design from scratch. Part 38

Writing software for our embedded system

I think we are ready to start writing some software to drive our embedded test controller. To make the application software easier to write and understand we will first come up with a software device driver for the ETC.

Writing a software device driver

As it says in the Xilinx Documentation:
Many of you have used embedded microprocessors in your recent FPGA designs. Some of you are experienced embedded processor users, and some of you are beginners to this method of design in FPGAs. Most embedded processor designers will at some stage decide that they need to incorporate a block of custom hardware into the processor system and then control it from software running on the processor. This is often a daunting task, and one that causes much confusion to the designer. This TechXclusive takes a step-by-step approach to designing a custom peripheral for use in an embedded processor system, then looks at some more advanced topics, including writing software device drivers for the created peripheral.


Software development overview

The embedded software platform defines, for each processor, the drivers associated with the peripherals we include in our hardware platform (the board support package), selected libraries, standard input/output devices, interrupt handler routines, and other related software features. Your Xilinx Platform Studio (XPS) project further defines software applications to run on each processor, which are based on the software platform.

Device Driver Programmer Guide

The purpose of this document is to describe the Xilinx device driver environment. This includes the device driver architecture, the
Application Programmer Interface (API) conventions, the scheme for configuring the drivers to work with reconfigurable hardware devices, and the infrastructure that is common to all device drivers.
This document is intended for the software engineer that is using the Xilinx device drivers. It contains design and implementation details necessary for using the drivers. The guide can be found here: EDK_install_dir/doc/usenglish/xilinx_drivers_guide.pdf and in html format :
EDK_install_dir/doc/usenglish/xilinx_drivers.htm

We will use this guide and the TechXclusive to help us write a device driver for the ETC peripheral.

Platform Specification Format Reference Manual

EDK tools are designed to operate in a data-driven manner. There are various meta-data files that capture information, for example, about various IPs, drivers, and software libraries being used in the EDK tools. Files are also used to capture both hardware and software aspects of our design information. These are ASCII files. The set of all these meta-data formats is referred to as the
Platform Specification Format or PSF.

Microprocessor Driver Definition (MDD)

An MDD file contains directives for customizing software drivers. Each device driver has an MDD file and a Tcl (Tool Command Language) file associated with it. The MDD file is used by the Tcl file to customize the driver, depending on different options configured in the MSS file.

Libraries and driver generation

As it says in the Xilinx Documentation:
The MHS and the MSS files define a system. For each processor in the system, Libgen finds the list of addressable peripherals. For each processor, a unique list of drivers and libraries are built. Libgen does the following for each processor:
  • Builds the directory structure as shown here below.
  • Copies the necessary source files for the drivers, OSs, and libraries into the processor instance specific area: OUTPUT_DIR/processor_instance_name/libsrc.
  • Calls the design rule check (defined as an option in the MDD or MLD file) procedure for each of the drivers, OSs, and libraries visible to the processor.
  • Calls the generate Tcl procedure (if defined in the Tcl file associated with an MDD or MLD file) for each of the drivers, OSs, and libraries visible to the processor. This generates the necessary configuration files for each of the drivers, OSs, and libraries in the include directory of the processor.
  • Calls the post_generate Tcl procedure (if defined in the Tcl file associated with an MDD or MLD file) for each of the drivers, OSs, and libraries visible to the processor.
  • Runs make (with targets include and libs) for the OSs, drivers, and libraries specific to the processor. On Unix platforms (Linux and Solaris), the gmake utility is used, while on NT platforms, make is used for compilation.
  • Calls the execs_generate Tcl procedure (if defined in the Tcl file associated with an MDD or MLD file) for each of the drivers, OSs, and libraries visible to the processor.
For more information about library generation read chapter 4 in the  Embedded System Tools Reference Manual.


Device driver architecture

The architecture of the device drivers is designed as a layered architecture as shown in the figure . The layered architecture accommodates the many use cases of device drivers while at the same time providing portability across operating systems, toolsets, and processors. The layered architecture provides seamless integration with an
RTOS (Layer 2), high-level device drivers that are full-featured and portable across operating systems and processors (Layer 1), and low-level drivers for simple use cases (Layer 0).

 Layer 2, RTOS adaptation
 Layer 1, High level drivers
 Layer 0, Low level drivers


xparameters.h


This source file centralizes basic configuration constants for all drivers within the system. Browsing this file gives the user an overall view of the system architecture. The device drivers and Board Support Package (BSP) utilize the information contained here to configure the system at runtime.
The amount of configuration information varies by device, but at a minimum the following items should be defined for each device:
  • Number of device instances
  • Device ID for each instance
  • A Device ID uniquely identifies each hardware device which maps to a device driver. A Device ID is used during initialization to perform the mapping of a device driver to a hardware device.
  • Device IDs are typically assigned either by the user or by a system generation tool. It is currently defined as a 16-bit unsigned integer.
  • Device base address for each instance
  • Device interrupt assignment for each instance if interrupts can be generated.
Here is an example:

/* Definitions for peripheral RS232_UART */

#define XPAR_RS232_UART_BASEADDR 0x40600000
#define XPAR_RS232_UART_HIGHADDR 0x4060FFFF
#define XPAR_RS232_UART_DEVICE_ID 1
#define XPAR_RS232_UART_BAUDRATE 9600
#define XPAR_RS232_UART_USE_PARITY 0
#define XPAR_RS232_UART_ODD_PARITY 0
#define XPAR_RS232_UART_DATA_BITS 8

The xparameters.h file can be found in the include directory.




Software driver source code

During the library generation (
libgen) run, the source code for every driver used, is copied to the SDK project directory libsrc, from the Xilinx source code repository. The old code will be overwritten and therefore we will never make any changes to the code in the libsrc directory. Here is the libgen log file.

Source code repository




Software device drivers used

To find out which software device drivers are used we can open Software Platform Settings and select Drivers. In the Xilinx Platform Studio SDK select Xilinx Tools->Software Platform Settings. The ETC peripheral has a generic driver assigned as default. We will add our own driver.




SDK project directory


The specified version of the driver source code is stored in the libsrc directory.





Let's take the GPIO driver as an example and look at different source files and their usage.

Header source file (xgpio.h and xgpio_l.h)

The
header files contain the interfaces for a component. There will always be external interfaces which is what an application that utilizes the component invokes.
  • The external interfaces for the high level drivers (Layer 1) are contained in a header file with the file name format x<component name>.h.
  • The external interfaces for the low level drivers (Layer 0) are contained in a header file with the file name format x<component name>_l.h.
The xgpio.h file contains the follwing type definitions.

/**************************** Type Definitions ******************************/


/**
 * This typedef contains configuration information for the device.
 */
typedef struct
{
    Xuint16  DeviceId;          /* Unique ID  of device */
    Xuint32  BaseAddress;       /* Device base address */
    Xboolean InterruptPresent;  /* Are interrupts supported in h/w */
    Xboolean IsDual;            /* Are 2 channels supported in h/w */
} XGpio_Config;

/**
 * The XGpio driver instance data. The user is required to allocate a
 * variable of this type for every GPIO device in the system. A pointer
 * to a variable of this type is then passed to the driver API functions.
 */
typedef struct
{
    Xuint32  BaseAddress;       /* Device base address */
    Xuint32  IsReady;           /* Device is initialized and ready */
    Xboolean InterruptPresent;  /* Are interrupts supported in h/w */
    Xboolean IsDual;            /* Are 2 channels supported in h/w */
} XGpio;

It also contains a number of
function prototypes. The functions themselves are defined in the different .c files found in the gpio source directory.

/************************** Function Prototypes *****************************/

/*
 * Initialization functions in xgpio_sinit.c
 */
XStatus XGpio_Initialize(XGpio *InstancePtr, Xuint16 DeviceId);
XGpio_Config *XGpio_LookupConfig(Xuint16 DeviceId);

/*
 * API Basic functions implemented in xgpio.c
 */
XStatus XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config *Config,
                            Xuint32 EffectiveAddr);
void    XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
                               Xuint32 DirectionMask);
Xuint32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
void    XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, Xuint32 Mask);


Configuration table xgpio_g.c

This file contains configuration tables for all devices that uses the GPIO device driver.

/*
* The configuration table for devices
*/

XGpio_Config XGpio_ConfigTable[] =
{
    {
        XPAR_LEDS_4BIT_DEVICE_ID,
        XPAR_LEDS_4BIT_BASEADDR,
        XPAR_LEDS_4BIT_INTERRUPT_PRESENT,
        XPAR_LEDS_4BIT_IS_DUAL
    },
    {
        XPAR_LEDS_POSITIONS_DEVICE_ID,
        XPAR_LEDS_POSITIONS_BASEADDR,
        XPAR_LEDS_POSITIONS_INTERRUPT_PRESENT,
        XPAR_LEDS_POSITIONS_IS_DUAL
    },
    {
        XPAR_PUSH_BUTTONS_POSITION_DEVICE_ID,
        XPAR_PUSH_BUTTONS_POSITION_BASEADDR,
        XPAR_PUSH_BUTTONS_POSITION_INTERRUPT_PRESENT,
        XPAR_PUSH_BUTTONS_POSITION_IS_DUAL
    },
    {
        XPAR_LCD_16X2_DEVICE_ID,
        XPAR_LCD_16X2_BASEADDR,
        XPAR_LCD_16X2_INTERRUPT_PRESENT,
        XPAR_LCD_16X2_IS_DUAL
    }
};

Adding the ETC software device driver


From the Xilinx documentation it isn't 100% clear how to add a new device driver. Here is how I did it and it seems to work.

1. Edit the ETC_system.mss file and add the etc driver. Like this:

   BEGIN DRIVER
     PARAMETER DRIVER_NAME = etc
     PARAMETER DRIVER_VER = 1.00.a
     PARAMETER HW_INSTANCE = ETC_0
  END

2. Add a new directory called drivers and the subdirectories as shown here:




3. Copy template files to src and data directories. We will use the gpio device driver source code as our template files. It is important to copy the .tcl and .mdd files to the data directory. Libgen will complain if it doesn't find these files.

4. Rename and edit the template files. For the moment we will not bother about writing working code. We will only rename everything called <gpio> to <etc>. Don't forget to make changes to the Makefile. Libgen will use the Makefile during library generation to compile and link the ETC device driver source code.

5. Edit the .mdd and .tcl files. Find out more
here.

6. Run library generation. Select Software->Generate Libraries and BSPs in the Xilinx Platform Studio. Libgen will search inside the drivers or pcores directories for device driver source code.

7. The ETC software device driver source code will be compiled into the library libxil.a together with all other device drivers.


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Posted at 09:34 by svenand

Goran
August 30, 2007   09:10 PM PDT
 
Hi Svend,
I like your work.
You should listen to your wife and publish a book.
Thanks,
Goran
Charles
August 30, 2007   05:19 PM PDT
 
Super great Svend. A resource like this is one young engineers need to catch the trade. Don't you think it will be a good idea to make all these resources downloadable by one click. i mean like a pdf zip file where all the resouces can be downloaded and read at convenience without sitting in front of the computer all the time
svenand
August 9, 2007   08:26 AM PDT
 
Thanks,
I have no plans today to add more vendors like Altera and Actel. I will finish this tutorial and then we will see. I spend a lot of unpaid time blogging and my wife thinks I should bring home some money instead. I have looked at www.gaisler.com and I open source is always good.
mikrodator
August 1, 2007   01:10 AM PDT
 
Hey,

this is a great resource. I'm sure that many curious hobbyists will get their hands dirty with FPGAs after reading your tutorials!

I have only skimmed through a couple of your tutorial pages.. But I still have a comment or two;

Are you planning to include some information about, or comparisions with, other vendors such as Altera? I understand that it might be difficult considering the cost of development boards. Also, have you checked out GRLIB from http://www.gaisler.com? I have high hopes for a bright future with many hobbyists releasing open hardware designs...
 

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