FPGA design from scratch. Part 27
Pin assignment closure process
Closing on a pin assignment that will meet requirements from both the PCB and FPGA environments is becoming more challenging. On one side of the interface, ever-increasing FPGA performance, density, and I/O count are placing tighter board constraints on the layout of the signal to and from the FPGA. On the other side, timing, congestion, and signal integrity of ever-faster signals on the PCB are placing constraints on FPGA pin assignment. Here is an article by Philippe Garrault from Xilinx describing the pin assignment closure process.
(Courtesy of Xilinx)
Tools to help you in pin assignment closure
PACE Pin and Area Constraint Editor
ISE includes PACE (Pinout and Area Constraints Editor), a powerful, yet fast and easy way to map design pins to your device, and floorplan logic areas. Drag-and-drop pins onto a graphical display of the device, group pins logically by color-coding for easy recognition, specify I/O standards and banks, assign and place differential I/Os, and much more. As devices grow ever larger, PACE brings a new level of ease to the difficult task of assigning design pins.
Running PACE
Let's start the PACE program.
==> pace &
/home/svenand/cad/xilinx91i/bin/lin/_pace: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory
To fix this problem we have to load the following Ubuntu packages:
libmotif3
libmotif-dev
==> pace &
Wind/U X-toolkit Error: wuDisplay: Can't open display
We have to change the DISPLAY variable from :0.0 to :0
==> export DISPLAY=:0
==> pace &
We specify our constraints file ETC_system.ucf as the input file to PACE and click OK.
PACE allows you to edit both location and area constraints, define logic areas graphically, and display I/Os on the periphery for connectivity checking. PACE allows area mapping by examining the defined HDL hierarchy and checks logic areas against expected gate size, making area definitions quick, accurate, and easy. Pins can be assigned using PACE before HDL coding has even started, and then write the HDL starting templates for you to edit. Pin information can be exported or imported to PCB layout editors through standard CSV files, greatly simplifying the design planning stage.
PACE contains built-in design rule checks like Simultaneous Switching Outputs to help predict ground bounce problems, unique displays like Package Flight Time allow you to see I/O to package lead delays for super-accurate timing.
Topi the Top Code Generator
Ever heard of table driven design. That is exactly what Topi is all about. When designing an FPGA with more than 1000 signal pins you need an exact and precise way of adding all the signal names. Topi will help you generate the top testbench, the top instantiation and the FPGA pin layout, all in the same tool.
Topi Setup
Using Topi to modify the Xilinx user constraints file
Let's start Topi.
==> topi &
We open the Setup->Pin Table window and select the Xilinx CSV table format.
Let's load the Xilinx CSV file into the Topi Spreadsheet Editor.
Here is the result.
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The next step is to import the pin layout information into the Topi Pin Layout Editor. From the Load menu we select Pin Names (Match Package Balls).
In the pin layout editor we can easily change the pin placement by editing each indivudual signal name or by moving pins around using the move function. When we are satisfied with the result we can save the information in a Xilinx user constraints file (ucf).
Xilinx Floorplanner
Xilinx Floorplanner is a graphical placement tool that provides "drag and drop" control over design placement within an FPGA. Floorplanning is particularly useful on structured designs and data path logic. With the Xilinx Floorplanner, designers can see where to place logic for optimal results, placing data paths exactly at the desired location on the die. The Xilinx Floorplanner enables designers to plan a design prior to or after using Place-and-Route (PAR) software. Invoking Floorplanner after a design has been placed and routed allows designers to view and possibly improve the results of the automatic implementation. In an iterative floorplan design flow, designers floorplan and place and route interactively.
When we started the PACE program we were told it will be replaced by the Floorplanner program. Why not give it a try.
==> floorplanner &
We enter the name of the ngd file and all the other files are found automatically. Click OK.
Viewing pin placement
If we select view Package Pins from the View menu we get the following display.
Xilinx PlanAhead
Here is an article about using PlanAhead Design and Analysis Tool.
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Posted at 09:52 am by
svenand
