New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Tuesday, May 29, 2007
FPGA design from scratch. Part 27
Pin assignment closure process

Closing on a pin assignment that will meet requirements from both the PCB and FPGA environments is becoming more challenging. On one side of the interface, ever-increasing FPGA performance, density, and I/O count are placing tighter board constraints on the layout of the signal to and from the FPGA. On the other side, timing, congestion, and signal integrity of ever-faster signals on the PCB are placing constraints on FPGA pin assignment. Here is an article by Philippe Garrault from Xilinx describing the
pin assignment closure process.

                                                                                                                             (Courtesy of Xilinx)
Tools to help you in pin assignment closure

PACE Pin and Area Constraint Editor

ISE includes PACE (Pinout and Area Constraints Editor), a powerful, yet fast and easy way to map design pins to your device, and floorplan logic areas. Drag-and-drop pins onto a graphical display of the device, group pins logically by color-coding for easy recognition, specify I/O standards and banks, assign and place differential I/Os, and much more. As devices grow ever larger, PACE brings a new level of ease to the difficult task of assigning design pins.

Running PACE

Let's start the PACE program.

==> pace &

/home/svenand/cad/xilinx91i/bin/lin/_pace: error while loading shared libraries: cannot open shared object file: No such file or directory

To fix this problem we have to load the following Ubuntu packages:

==> pace &

 Wind/U X-toolkit Error: wuDisplay: Can't open display

We have to change the DISPLAY variable from :0.0 to :0

==> export DISPLAY=:0
==> pace &

We specify our constraints file ETC_system.ucf as the input file to PACE and click OK.

PACE allows you to edit both location and area constraints, define logic areas graphically, and display I/Os on the periphery for connectivity checking. PACE allows area mapping by examining the defined HDL hierarchy and checks logic areas against expected gate size, making area definitions quick, accurate, and easy. Pins can be assigned using PACE before HDL coding has even started, and then write the HDL starting templates for you to edit. Pin information can be exported or imported to PCB layout editors through standard CSV files, greatly simplifying the design planning stage.

PACE contains built-in design rule checks like Simultaneous Switching Outputs to help predict ground bounce problems, unique displays like Package Flight Time allow you to see I/O to package lead delays for super-accurate timing.

Topi the Top Code Generator

Ever heard of table driven design. That is exactly what Topi is all about. When designing an FPGA with more than 1000 signal pins you need an exact and precise way of adding all the signal names. Topi will help you generate the top testbench, the top instantiation and the FPGA pin layout, all in the same tool.

Topi Setup

Using Topi to modify the Xilinx user constraints file

Let's start Topi.
==> topi &

We open the Setup->Pin Table window and select the Xilinx CSV table format.

Let's load the Xilinx CSV file into the Topi Spreadsheet Editor.

Here is the result.

The next step is to import the pin layout information into the Topi Pin Layout Editor. From the Load menu we select Pin Names (Match Package Balls).

In the pin layout editor we can easily change the pin placement by editing each indivudual signal name or by moving pins around using the move function. When we are satisfied with the result we can save the information in a Xilinx user constraints file (ucf).

Xilinx Floorplanner

Xilinx Floorplanner is a graphical placement tool that provides  "drag and drop" control over design placement within an FPGA. Floorplanning is particularly useful on structured designs and data path logic. With the Xilinx Floorplanner, designers can see where to place logic for optimal results, placing data paths exactly at the desired location on the die.

The Xilinx Floorplanner enables designers to plan a design prior to or after using Place-and-Route (PAR) software. Invoking Floorplanner after a design has been placed and routed allows designers to view and possibly improve the results of the automatic implementation. In an iterative floorplan design flow, designers floorplan and place and route interactively.

When we started the PACE program we were told it will be replaced by the Floorplanner program. Why not give it a try.

==> floorplanner &

We enter the name of the ngd file and all the other files are found automatically. Click OK.

Viewing pin placement

If we select view Package Pins from the View menu we get the following display.

Xilinx PlanAhead

Here is an article about using
PlanAhead Design and Analysis Tool.

Top  Next  Previous

Posted at 09:52 by svenand

September 1, 2008   02:28 PM PDT
I have installed Xilinx ISE 9.2i with Ubuntu 8.04 Hardy and everything works fine except the floorplanner. From within ISE, when i double click the floorplanner i get a message that floorplanning was succesful but i don't see the editor itself. Ihave added the export DISPLAY=:0 to my file but i don't know how to execute it. I have also installed libmotiv3 nad libmotif-dev. Any ideas?

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