New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Saturday, May 26, 2007
FPGA design from scratch. Part 26
Using the iMPACT configuration tool

After we have connected the USB JTAG programming cable and started iMPACT it will detect the JTAG chain on the ML403 evaluation board and display it in the boundary scan window.



The FPGA, Platform Flash memory, and CPLD can be configured through the
JTAG
port. The JTAG chain of the board is illustrated in this figure.


                                                                                                                        (Courtesy of Xilinx)
Boundary -Scan and JTAG configuration

Virtex-4 devices support the new
IEEE 1532 standard for In-System Configuration (ISC), based on the IEEE 1149.1 standard. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture is commonly referred to as JTAG. JTAG is an acronym for the Joint Test Action Group, the technical subcommittee initially responsible for developing the standard. This standard provides a means to ensure the integrity of individual components and the interconnections between them at the board level. With multi-layer PC boards becoming increasingly dense and more sophisticated surface mounting techniques in use, Boundary- Scan testing is becoming widely used as an important debugging standard.

IEEE standard 1149.1 (JTAG)


The Virtex-4 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the instruction register, the instruction decoder, the Boundary-Scan register, and the bypass register. The Virtex-4 family also supports a 32-bit identification register and a configuration register in full compliance with the standard.


                                                                                                                               (Courtesy of Xilinx)
The identification register


Virtex devices have a 32-bit identification register called the IDCODE register. The IDCODE is based on the IEEE 1149.1 standard, and is a fixed, vendor-assigned value that is used to identify electrically the manufacturer and the type of device that is being addressed. This register allows easy identification of the part being tested or programmed by Boundary-Scan, and it can be shifted out for examination by using the IDCODE instruction.

Read IDCODE

Select one of the devices displayed in the Boundary Scan window and and double-click the Get Device ID entry in the Operations window. The result is displayed in the Output window.

// *** BATCH CMD : ReadIdcode -p 3
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'3': IDCODE is '00100001111001011000000010010011'
'3': IDCODE is '21e58093' (in hex).
'3': : Manufacturer's ID =Xilinx xc4vfx12, Version : 2


Read the FPGA status register

Select the Virtex-4 device in the Boundary Scan window and double-click the Read Status Register entry in the Operations window, The result is displayed in the Output window.

// *** BATCH CMD : ReadStatusRegister -p 3
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'3': Reading status register contents...
CRC error                                                :         0
Decryptor security set                                   :         0
DCM locked                                               :         1
DCI matched                                              :         1
End of startup signal from Startup block                 :         1
status of GTS_CFG_B                                      :         1
status of GWE                                            :         1
status of GHIGH                                          :         1
value of MODE pin M0                                     :         1
value of MODE pin M1                                     :         1
Value of MODE pin M2                                     :         1
Internal signal indicates when housecleaning is completed:         1
Value driver in from INIT pad                            :         1
Internal signal indicates that chip is configured        :         1
Value of DONE pin                                        :         1
Indicates when ID value written does not match chip ID   :         0
Decryptor error Signal                                   :         0
System Monitor Over-Temperature Alarm                    :         0

Device configuration

Configuring and programming are often used interchangeably. However, there is a distinction between these two terms. Configuration refers to the process of loading design-specific data into one or more volatile FPGAs using an external data source such as a PROM. Programming refers to the process of loading design-specific data into one or more non-volatile PROMs or CPLD devices. Configuring or programming a device defines the functional operations of the device. For simplification, we refer both configuring and programming as the device configuration. For general configuration guidelines, see XAPP501 Application Note.

Using Xilinx Platform Studio

Now when we are confident about our usb cable connection we are ready for the final step, downloading the bitstream to the FPGA device. We will start Xilinx Platform Studio (xps) to help us do the job.

==> cd $ETC_PROJECT
==> xps



To start the bitstream download select Device Configuration->Download Bitstream. The result is displayed in the output window. It says Programmed successfully.
Huzzah!


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Posted at 15:47 by svenand

 

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