New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

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New Horizons
What's new
Starting a blog
Writing a blog
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Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
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Installing Cobra Command Tool
A processor benchmark
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Saturday, May 05, 2007
FPGA design from scratch. Part 25
Implementing the hardware platform

After more than 5 month of hard work we have reached
the point of no return, it is time to program the FPGA. After completing hardware platform design entry, we are ready to:
  • Specify design constraints
  • Generate the bitstream (BIT) file that represents the completed hardware platform

User Constraints File

To create the BIT file for downloading and implement the design, we must first set up our User Constraints File (UCF). As in ISE, an FPGA design implemented using EDK requires a UCF. Primarily, the UCF specifies pinouts and timing constraints. It can also control a variety of other hardware implementation features, such as the configurable electrical characteristics of our  FPGA I/O signals.

Setting up our User Constraints File

To access the UCF file for our XPS project:

  1. Click the Project tab in the Project Information Area of the main window and look for the UCF file under the Project Files heading.
  2. Double-click the UCF file to open it in the System Assembly panel.


The UCF has the same base filename as the Xilinx Microprocessor Project (XMP) file, and it must reside in the data subfolder of our project directory.


Specifying Pin Constraints

We must often provide a Location (LOC) constraint to define the FPGA pin location for each external port. To view the list of the external ports, do the following:

  1. In the XPS main window, click the System Assembly tab.
  2. Select the Ports filter.


LOC constraints take the following form:

NET RS232_RX_pin LOC=U4;

Specifying Timing Constraints

For most embedded processor designs, we need only specify the input (reference) clock period to ensure that your system meets performance requirements. In some cases, our design might contain off-chip peripherals, such as memory controllers, that have particular input and output timing requirements. We should also declare Timing IGnore (TIG) constraints on signals that are not timing critical to allow better place and route tools to optimize other timing paths. The following are typical of the basic timing constraints we must provide in our UCF file:

Net sys_clk_pin PERIOD = 20000 ps;
Net sys_rst_pin TIG;

The implementation directory

The result from netlist generation is stored in the implemenation directory. All the NGC files from the synthesis runs are collected here. The bitstream generation program will include all the netlist files to generate the final bitstream. We have to make sure all netlist files can be found in the implementation directory before we start the bitstream generation. When we generated the ETC_DUAL_PORT_1024x32 memory using Coregen (
see part 4) the netlist file ETC_DUAL_PORT_1024x32.edn was created. This file will also be copied to the implementation directory.



Start bitstream generation


From the XPS Hardware menu we choose Generate Bitstream to start the bitstream generation.

Here is a printout from the startup of the program.

At Local date and time: Fri May 25 16:18:25 2007
 make -f ETC_system.make bits started...
*********************************************

Running Xilinx Implementation tools..

*********************************************

xflow -wd implementation -p xc4vfx12ff668-10 -implement xflow.opt ETC_system.ngc

Release 9.1.02i - Xflow J.30

Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

xflow -wd implementation -p xc4vfx12ff668-10 -implement xflow.opt ETC_system.ngc
 
Using Flow File: /home/svenand/root/projects/ETC/xps/implementation/fpga.flw

Using Option File(s):

 /home/svenand/root/projects/ETC/xps/implementation/xflow.opt

Creating Script File ...

#----------------------------------------------#

# Starting program ngdbuild

# ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm ETC_system.bmm
"/home/svenand/root/projects/ETC/xps/implementation/ETC_system.ngc" -uc
ETC_system.ucf ETC_system.ngd

#----------------------------------------------#

Release 9.1.02i - ngdbuild J.33
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.


Command Line: ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm ETC_system.bmm
/home/svenand/root/projects/ETC/xps/implementation/ETC_system.ngc -uc
ETC_system.ucf ETC_system.ngd

Bitstream generation flow

The Bitstream generation uses the XFLOW program to setup and run the complete program flow. XFLOW is a command line program that automates Xilinx synthesis, implementation, and simulation flows. XFLOW reads a design file as input as well as a flow file and an option file. Xilinx provides a default set of flow files that automate which Xilinx programs are run to achieve a specific design flow. For example, a flow file can specify that NGDBuild, MAP, PAR, and TRACE are run to achieve an implementation flow for an FPGA. Here is the 
xflow log file from our bitstream generation run.
For more information about XFLOW read the
Xilinx Development System Reference Guide.


                                                                                                 (Courtesy of Xilinx)

The NGC files are processed, along with the system constraints, through Xilinx tools (NGDBuild, MAP, PAR, and TRACE) when XPS invokes the XFlow command-line program.

Script file to run XFlow

Here is the script file that are generated when we start the bitstream generation.

#!/bin/csh -f
###########################################
# Script file to run the flow
#
###########################################
#
# Command line for ngdbuild
#
ngdbuild -p xc4vfx12ff668-10 -nt timestamp -bm ETC_system.bmm "/home/svenand/root/projects/ETC/xps/implementation/ETC_system.ngc" -uc ETC_system.ucf ETC_system.ngd

#
# Command line for map
#
map -o ETC_system_map.ncd -pr b ETC_system.ngd ETC_system.pcf

#
# Command line for par
#
par -w -ol high ETC_system_map.ncd ETC_system.ncd ETC_system.pcf

#
# Command line for post_par_trce
#
trce -e 3 -xml ETC_system.twx ETC_system.ncd ETC_system.pcf


Bitstream generation result

During the bitstream generation a number of files have been generated.

 File Name
 Description Readable
ETC_system.bgn Bitgen log file
Yes
ETC_system.bit Bitstream download file
No
ETC_system.bld Ngdbuild log file
Yes
ETC_system.bmm Address map bram
Yes
ETC_system.drc Drc log file
Yes 
ETC_system.ncd Mapping output file
No
ETC_system.ngc XST synthesis output file
No
ETC_system.ngd Xilinx native generic database format
No
ETC_system.pad Pin definition file (spreadsheet import file)  Yes 
ETC_system.par
Placer report file
Yes
ETC_system.pcf
Map report file
Yes
ETC_system.twr
Trace report file (timing constraints)
Yes
ETC_system.twx
Trace XML file
Yes
ETC_system.ucf
User constraints file (copied from data dir)
Yes
ETC_system.unroutesDisplays unrouted netsYes
ETC_system_pad.cvs
Pin definition file (spreadsheet import file)
Yes
ETC_system_pad.txt
Pin definition file (text format)
Yes
ETC_system_map.mrp
Mapping report file
Yes


Configuration of the FPGA

Virtex-4 devices are configured by loading application-specific configuration data�the bitstream�into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:
  • Master-serial configuration mode
  • Slave-serial configuration mode
  • Master SelectMAP (parallel) configuration mode
  • Slave SelectMAP (parallel) configuration mode
  • In addition, the bitstream can be loaded through the JTAG interface
Read more in the Virtex-4 Configuration Guide.

Using the Platform Cable USB

Platform Cable USB is a high-performance download cable attaching to user hardware for the purpose of programming or configuring any of the following Xilinx devices:
  • ISP Configuration PROMs
  • CPLDs
  • FPGAs
Platform Cable USB attaches to the USB port on a desktop or laptop PC with an off-the-shelf Hi-Speed USB A-B cable. It derives all operating power from the hub port controller. No external power supply is required. A sustained slave-serial FPGA configuration transfer rate of 24 Mb/s is possible in a Hi-Speed USB environment. Actual transfer rates can vary if bandwidth of the hub is being shared with other USB peripheral devices. Platform Cable USB attaches to target systems using a 14-conductor ribbon cable designed for high-bandwidth data transfers.





ML403 evaluation board


                                                                                                                         (Courtesy of Xilinx)

Read the
ML403 user guide to find out what the numbers stand for. Here are some known issues with this board. Here is all the documentation about the ML403 board.


ML403 block diagram


                                                                                                                         (Courtesy of Xilinx)
ML403 blocks and busses


                                                                                                                    (Courtesy of Xilinx)
Installing cable drivers

In the Xilinx answers database we find answer
#22648: 9.1i iMPACT - Installing Xilinx cable drivers on Linux operating system/kernel version 2.6. We will install the drivers in our Ubuntu Linux 7.04 system. To find out which version of the kernel we have installed we use the command:

==> uname -a
Linux svenand-desktop 2.6.20-15-generic #2 SMP Sun Apr 15 07:36:31 UTC 2007 i686 GNU/Linux

When I was out on the web looking for information about installing the cable drivers I came across the following link:  http://www.rmdir.de/~michael/xilinx/

XILINX JTAG tools on Linux without proprietary kernel modules

When using Xilinx JTAG software like Impact, Chipscope and XMD on Linux, the proprietary kernel module windrvr from  Jungo is needed to access the parallel- or usb-cable. As this module does not work with current linux kernel versions (> 2.6.18) a library was developed, which emulates the module in userspace and allows the tools to access the JTAG cable without the need for a proprietary kernel module.

Let's give it a try. To me it sounds like a much better solution than the one Xilinx provides. We will follow the instructions found in this README file.
  1. Install the libusb-dev package using the command: sudo apt-get install libusb-dev
  2. Download usb-driver-HEAD.tar.gz and save the file in a temp directory
  3. Goto the temp directory cd .../temp
  4. Unpack the file using the command: tar zxvf usb-driver-HEAD.tar.gz
  5. Goto the usb-driver directory: cd usb-driver
  6. Install the package build-essential (contains make) sudo apg-get install build-essential
  7. Build the libusb-driver.so library file using the command: make
  8. Copy libusb-driver.so to the /usr/lib directory: sudo cp libusb-driver.so  /usr/lib/.
  9. To use this library we have to preload it before starting impact: 
  10. export LD_PRELOAD=/usr/lib/libusb-driver.so (sh and bash)
  11. setenv LD_PRELOAD /usr/lib/libusb-driver.so (csh and tcsh)
Setting up the USB cable
  1. To use the device as an ordinary user, put the following line in the file /etc/udev/rules.d/50-xilinx-usb-pav.rules (or use any file name you like) ACTION=="add",BUS=="usb",SYSFS{idVendor}=="03fd",MODE="666"
  2. sudo gedit /etc/udev/rules.d/50-xilinx-usb-pav.rules and add the line above
  3. Restart udev: sudo /etc/init.d/udev restart
  4. Execute the command: lsusb
  5. Bus 002 Device 002: ID 03fd:000f Xilinx, Inc.
    Bus 002 Device 001: ID 0000:0000 
    Bus 001 Device 001: ID 0000:0000
  6. If your cable does not have the ID 03fd:0008 in the output of lsusb the initial firmware has not been loaded (loading it changes the product-ID from another value to 0008
  7. To load the firmware follow these steps:
  8. If you have no /etc/udev/rules.d/xusbdfwu.rules file, copy it from /ISE_install_dir/bin/lin/xusbdfwu.rules
  9. Install the package fxload using the command: sudo apt-get install fxload
  10. Copy the file /ISE_install_dir/bin/lin/xusbdfwu.hex to /usr/share/xusbdfwu.hex
  11. Restart udev: sudo /etc/init.d/udev restart
  12. Execute the command: lsusb
  13. Bus 002 Device 001: ID 0000:0000 
    Bus 001 Device 003: ID 0e0f:0002 
    Bus 001 Device 002: ID 03fd:0008 Xilinx, Inc.
    Bus 001 Device 001: ID 0000:0000
  14. The ID is 03fd:0008
  15. Replug the usb cable
  16. Make sure the green status light is on. The USB cable interface must be connected during  VMware Fusion Ubuntu bootup. WMware will detect the USB cable interface and automatically connect it.

Permission denied. Change owner

Can't open /dev/parport0: Permission denied

If this message is displayed in the terminal when starting iMPACT, we have to change the owner of this file from root to the current user. Like this: sudo chown svenand /dev/parport0. This has to repeated every time after we have booted the Linux OS.

Unlocking the cable interface

Use the following commands to unlock the cable interface if needed:

==>  impact -batch
  > setMode -bscan
  > cleancablelock
  > quit


iMPACT FPGA configuration tool

iMPACT allows designers to easily perform device configuration and programming either as a batch operation or through a convenient graphical user interface. iMPACT is a full featured software tool used for configuration and programming of all Xilinx PLDs (FPGAs and CPLDs) and PROMs. iMPACT features a series of design wizards that easily guide the user through each step of the configuration process.

Starting iMPACT

==> impact & (xilinx_install_dir/bin/lin/impact)



We will create a new project in iMPACT and give it a name ETC_system.icf



We will use Boundary-Scan (JTAG) to configure the FPGA.




When we click Finish the program connects to our evaluation board. Here is the printout from iMPACT:

Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /home/svenand/cad/xilinx91i/bin/lin/xusbdfwu.hex = 1025(dec), 0x0401.
File version of /usr/share/xusbdfwu.hex = 1025(dec), 0x0401.
 libusb-driver.so version: 2007-05-27 00:37:02.
 Cable PID = 0008.
 Max current requested during enumeration is 280 mA.
 Cable Type = 3, Revision = 0.
 Cable Type = 0x0605.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1025.
CPLD file version = 0012h.
CPLD version = 0006h.
WARNING:iMPACT:2356 - Platform Cable USB firmware must be updated. This operation may take up to 10 minutes on a USB 2.0 port or up to 30 minutes on a USB 1.1 port.
Please do not stop the process or disconnect the cable prior to completion. The cable

STATUS LED will be RED for the duration of the update process.

Updating the cable firmware...
PROGRESS_START - Starting Operation.
Firmware update completed successfully.
PROGRESS_END - End Operation.
Elapsed time =   1943 sec.
Attempting to identify devices in the boundary-scan chain configuration...// *** BATCH CMD : Identify
PROGRESS_START - Starting Operation.
Identifying chain contents ....'1': : Manufacturer's ID =Xilinx xc95144xl, Version : 5
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/xc9500xl/data/xc95144xl.bsd...
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'2': : Manufacturer's ID =Xilinx xc4vfx12, Version : 2
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/virtex4/data/xc4vfx12.bsd...
INFO:iMPACT:501 - '1': Added Device xc4vfx12 successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'3': : Manufacturer's ID =Xilinx xcf32p, Version : 15
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/xcfp/data/xcf32p.bsd...
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'4': : Manufacturer's ID =Xilinx xccace, Version : 0
INFO:iMPACT:1777 -
Reading /home/svenand/cad/xilinx91i/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
PROGRESS_END - End Operation.
Elapsed time =      4 sec.
// *** BATCH CMD : identifyMPM

Congratulations! We have a working cable connection to our evaluation board. Thanks Michael, you saved our day.


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Posted at 11:34 by svenand

4rx
November 2, 2011   06:41 PM PDT
 
Just wanted to thank you, not just because the nice post, but pretty much more because my grandfather is nearly recovering from his surgery and he has almost nothing to do but staying on bed all day, his best source of entertainment has been this blog and I feel this is something good for him and his recovery.
Per Bj. BRO
October 2, 2009   05:34 PM PDT
 
Thank you for a very clear description. If your Xilinx board USB cable is not detected with product ID 000f, when executing 'lsusb', then you might have to copy all of the xusb*.hex files from the /Xilinx/bin/lin directory to /usr/share. This is clear if you look at the rules file. In my case, the product ID was 000d, and I needed the xusb_emb.hex file.
Fabiano
August 9, 2008   10:09 PM PDT
 
XILINX JTAG tools on Linux without proprietary kernel modules RELATED

Thanks for your precious guide. Now I can use Impact (ISE 9.2i) in OpenSuse 11.0 (X86_64)
Aleksandr
November 17, 2007   09:33 AM PST
 
I have 64-bit Gentoo Linux
I compiled libusb0driver.so
When I tried to run impact I see:

LD_PRELOAD=/home/starterkit/Xilinx92i/bin/lin/libusb-driver.so ./impact
ERROR: ld.so: object '/home/starterkit/Xilinx92i/bin/lin/libusb-driver.so' from LD_PRELOAD cannot be preloaded: ignored.
ERROR: ld.so: object '/home/starterkit/Xilinx92i/bin/lin/libusb-driver.so' from LD_PRELOAD cannot be preloaded: ignored.
ERROR: ld.so: object '/home/starterkit/Xilinx92i/bin/lin/libusb-driver.so' from LD_PRELOAD cannot be preloaded: ignored.

Release 9.2i - iMPACT J.36
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
ERROR: ld.so: object '/home/starterkit/Xilinx92i/bin/lin/libusb-driver.so' from LD_PRELOAD cannot be preloaded: ignored.

What can I do?
 

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