All Xilinx IP blocks are protected, meaning we don't have access to the RTL code and we can't probe internal nodes during a simulation. This makes debugging complicated. We can only observe input and output signals to the IP block and we have no idea what is going on inside the block.
The reset logic
The OPB_V20 design includes several sources for bus reset. A power-on reset circuit asserts the OPB_Rst for 16 clock cycles anytime the FPGA has completed configuration. External resets that occur during the 16 clock reset time are ignored. After the 16-clock reset has completed, external resets can be applied to the OPB_V20 reset signals. The external resets are: SYS_Rst (can be configured as high-true or low-true), WDT_Rst, and Debug_SYS_Rst. SYS_Rst is the main user reset for the OPB and can be connected to internal logic or an external signal or switch. WDT_Rst can be connected to the reset output of a Watchdog Timer to allow for OPB resets in the event of a watchdog time-out. Debug_SYS_Rst can be connected to the reset output of a debug peripheral, such as the JTAG UART, so that the debugger can remotely reset the OPB. SYS_Rst, WDT_Rst, and Debug_SYS_Rst are synchronized to the OPB_Clk in the OPB_V20, but the width of these signals is otherwise unaltered.
Reset signal polarity
What is the polarity of the reset signal. Here is the specification for the opb_v20 setup, taken from the ETC_system.mhs file.
BEGIN opb_v20 PARAMETER INSTANCE = mb_opb PARAMETER HW_VER = 1.10.c PARAMETER C_EXT_RESET_HIGH = 0 PORT SYS_Rst = sys_rst_s PORT OPB_Clk = sys_clk_s END
The PARAMETER C_EXT_RESET_HIGH = 0 specification means that the reset signal is active low.
The system reset SYS_rst goes to the opb_mb block and should propagate through this block and generate the inverted OPB_rst signal.
MicroBlaze reset
When a Reset (OPB_rst) or Debug_Rst occurs, MicroBlaze will flush the pipeline and start fetching instructions from the reset vector (address 0x0). Both external reset signals are active high, and should be asserted for a minimum of 16 cycles.
All output signals are defined from the opb_mb block and we have the reset signal to the MicroBlaze processor coming through. We are ready for more advanced simulations. First we have to study how the MicroBlaze processor operates. Here is the MicroBlaze Processor Reference Guide.
