The process of building a testbench from scratch is a tedious and error prone task. We will use the Topi Top Code Generator to create a skeleton for our testbench. This will save us time and headache. Here we go:
Start the Topi program: ==> topi &
Open the Design Setup window. Setup->Design and specify a name for our design.
Next open the Pin Table setup window and select the ASIC/FPGA Pin Definition format.
Open the Pin Table window and select Import from VHDL entity from the Edit menu. We will now import information about all signals used in the top entity that the testbench must access.
This is what the Pin Table looks like after the import has finished.
Some of the signals names are very long and contain information that we don't need. We will add shorter instance names. To do that we open the Add Instance Names window Edit->Add Instance Names and copy the selected signal names to the Instance Name column.
We can now edit the instance names in the Pin Table editor and the result looks like this:
Everything is now setup for generating a Verilog testbench: Generate->Verilog Testbench.
When we click the run button this testbench setup file is generated. The whole process took less than 30 minutes. Topi saved us several hours work. This file will be included in the main body testbench file.The testbench is now complete and we only need a simple testcase to start our first simulation. For more information about testbench design read part 7 of this story. TopNextPrevious
