• Cadence Incisive Unified Simulator (IUS58) will be used
• The Mongoose Simulation Environment will be used to define the simulation setup
  
• All IP blocks are or will be compiled and storied in a simulation database
• All wrapper files and the top entity files will be compiled and stored in the database
• The verilog testbench template will be generated by the Topi Top Code Generator
• We have to find a verilog or VHDL model for the external SDRAM
  

Part 13 (Compiling everything) for information on how to compile the EDK libraries. Here is a view of the simulation database:

This is the printout from the compilation.



The following line in the cds.lib file defines the name and the location of the compilation database.

define etc_v1_00_a  /home/svenand/root/projects/ETC/verification/database/ncsim/userlib/etc_v1_00_a

Compiling Verilog wrappers

The ETC_system_verilog_v1_00_a.def contains all the Verilog wrappers. In our case only the ETC wrapper.



When compiling Verilog code you almost every time get a message telling you that some modules are missing timescale directives. The easiest way to fix this problem is to have a separate timescale file only containing a timescale directive. Like this: timescale 1ns/10ps. I call this file timescale.v and put it as the first file in the Verilog compile script.

Compiling VHDL wrappers

The ETC_system_vhdl_v1_00_a.def contains all the VHDL wrappers and the top entity.

define top   /home/svenand/root/projects/ETC/verification/database/ncsim/top_design

Elaborating the design

We have now compiled the whole design and are ready to elaborate. Here is the elaboration script generated from Mongoose:

/* NCSIM elaboration control file generated from Mongoose 15.5       */
/* Generation date :  2007-04-22                                     */
/* Generation time :  04:57:52                                       */

-cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds_system.lib
-hdlvar /home/svenand/root/projects/ETC/verification/simSetup/ncsim/hdl.var
-logfile /home/svenand/root/projects/ETC/verification/log/ETC_system_vhdl_v1_00_a.elog
-messages
-notimingchecks
-access +rwc
ETC_SYSTEM

Here is the result from the elaboration.



Warning messages

During the elaboration phase you will probably see a lot of warnings displayed in the terminal window. For example:

ncelab: *W,CUDEFB: default binding occurred for component instance (:ETC_system(STRUCTURE):etc_0) with verilog module (top.etc_0_wrapper:module).

and

ncelab: *W,CUNOTB: component instance is not fully bound (:ETC_system(STRUCTURE):iobuf_47) [File:ETC_system.vhd, Line:2075]

To find out more about these warnings we can execute the following commands:

==> nchelp ncelab CUDEFB

nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
ncelab/CUDEFB =
    No explicit binding mechanism was found for the component instance
    in the form of a configuration specification or a component
    declaration. Default binding occurred with an entity having a
    visible entity declaration which had the same simple name as that
    of the instantiated component.

I do remember overhearing something about this particular message.  Default binding is a perfectly normal thing to
do, and is standard VHDL.  However, some customer was trying to use a methodology of requiring explicit binding for
everything.  To enforce this, they wanted a warning produced whenever default binding was used instead.  As a result,
everyone else has to put up with a bunch of warnings that they didn't care about.
I think we can ignore this warning. We will add this line to the elaboration script: -nowarn CUDEFB

1. Uses explicit binding indications
2. If there is no explicit binding indication, the elaborator tries to bind the component to in order:

• A design unit made visable with a USE clause given to the architecture instantiating the component.
• A design unit made visable with a USE clause given to the entity of the architecture instantiating the component.
• A design unit available in the library into whjich the component was compiled.
• A design unit in the work library

1. A design unit made visable with a LIBRARY clause given to the architecture instantiating the component (no corresponding USE clause).
2. A design unit made visable with a LIBRARY clause given to the entity of the architecture instantiating the component (no corresponding USE clause)
3. A design unit in a library defined in the cds.lib file. If a binding has not been found the elaborator opens the cds.lib file and searches all of the libraries that are defined.