The IP catalog tab shows all of the IPs that are available to use in an EDK project. To add the ETC IP:
Bring the IP catalog tab forward
Expand the Project Repository hierarchy
Drag and drop the ETC into the System Assembly View or double click on the ETC.
Expand the ETC instance
Highlite the slave OPB connection (SOPB)
Select the No Connection pull down menu and change it to mb_opb
Port connection
All OPB signals have already been connected to OPB bus. The remaining signals can be connected using the port view. We will make all signals external. Some input signals not used will be connected to ground and some unused output signals will be left unconnected.
Generate addresses
Select the Address filter to define addresses for the newly added ETC peripheral. The address can be assigned by entering the Base Address or the tool can assign an address. We will let the tool generate addresses:
Change the size of the memory blocks to 1K and for the register map to 4.
Click the Generate Addresses
A message in the console window will state that the address map has been generated successfully. The design is now ready to be implemented.
Mixed language design
All IP blocks from Xilinx are written in VHDL. The ETC IP is written in Verilog and therefor this design will be a mixed language design. The synthesis and simulation tools have no problems dealing with mixed language designs and hopefully this will not complicate our design job.
Set project options
Select Project->Project Options and click the HDL and Simulation tab. Because the majority of the design is in VHDL we will generate a VHDL top entity file. We will use NCSim for our simulations and we will allow mixed language behavioral files.
Generate the system netlist
We can now generate the system netlist. Click Hardware->Generate Netlist. The generation starts and returns with the following error message:
ERROR:MDT - INST:ETC_0 PORT:I_OPB_BE CONNECTOR:mb_opb_OPB_BE - /home/svenand/root/projects/ETC/xps/pcores/ETC_v1_00_a/data/ETC_v2_1_0.mpd line 43 - calculated index is out of signal VEC range of [0:3]
Let's open the ETC_v2_1_o.mpd file and figure out what the problem is. The OPB_BE signal is a four bit bus and not a one bit signal as I thought. If we add VEC [0:3] to the OPB_BE definition this problem will be fixed and we can rerun the netlist generation.
This is incredible. The whole netlist generation runs without any problems and it took less than 10 minutes on my MacBook using a virtual machine (Parallels Desktop) and Ubuntu Linux. Here is the log file and here are all the warnings. What happend during the netlist generation
When we start the netlist generation the following command is executed: platgen -p xc4vfx12ff668-10 -lang vhdl ETC_system.mhs
(Courtesy of Xilinx)
Hardware generation is accomplished with the Platform Generator (Platgen) tool. Platgen constructs the programmable system on a chip in the form of hardware netlists (HDL and implementation netlist files). Platgen creates a hardware platform using the Microprocessor Hardware Specification (MHS) file as input. In addition to netlist files in various formats such as NGC and EDIF, Platgen creates support files for downstream tools and top-level HDL wrappers to allow you to add other components to the automatically generated hardware platform. Read more about Platgen in the Embedded Systems Tools Guide (chapter 2). During the Platgen run the following directories have been created and filled with files.
hdl
implementation
synthesis
The HDL directory contains all the HDL verilog and VHDL wrapper files that instantiates the IP blocks used in the design. The VHDL IPs always have VHDL wrappers and the Verilog IPs have Verilog wrappers. The top module ETC_system.vhd is a VHDL entity because we specified a VHDL netlist to be generated.
The implementation directory holds all the NGC files. The NGC file is a netlist that contains logical design data and constraints. This file replaces both EDIF and Netlist Constraints (NCF) files.
The synthesis directory holds all synthesis scripts used when running the syntesis tool XST.
We are now ready to program the FPGA on the evaluation board and start debugging the design. But before we do that we will setup a simulation environment and simulate the whole design. I am an old ASIC designer. Always simulate before implement.
Generate simulation HDL files
We will try the Xilinx HDL simulation environment. To generate the simulation setup goto the Simulation menu and select Generate Simulation HDL Files. The following script will start: make -f ETC_system.make simmodel. When the script has finished a new directory called simulation has been created.
Using simulation, you don't have to wait for hardware to be complete before testing your software. The result: facilitated software development, which allows you meet more aggressive project deadlines.
Simulation provides insight into the internal workings of your system. Signals and register values are more accessible in a simulated system than they are once a design is in hardware.
Simulation also allows you complete control of your system. Conditions that may be difficult to create in a hardware setting are relatively easy to simulate.
Running a simulation in XPS
We will take these steps to start a simulation using NCSIM:
cd /home/svenand/root/projects/ETC/xps/simulation/behavioral
chmod 777 ETC_system.sh (make script executable)
chmod 777 ETC_system_setup.sh
Edit the ETC_system_setup.sh file and change -lib_binding to -relax
Start the simulation script: ./ETC_system_setup.sh
Read chapter 7 in the EDK Concepts, Tools, and Techniques guide to find out more about simulating our design. Before we can start our simulation we need to write a simple software application that will run in our system. We will come back to simulation when we have finished this task.
