New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

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New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Cobra Command Tool
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Thursday, April 12, 2007
FPGA design from scratch. Part 17
Adding the ETC IP

The IP catalog tab shows all of the IPs that are available to use in an EDK project. To add the ETC IP:
  • Bring the IP catalog tab forward
  • Expand the Project Repository hierarchy
  • Drag and drop the ETC into the System Assembly View or double click on the ETC.
  • Expand the ETC instance
  • Highlite the slave OPB connection (SOPB)
  • Select the No Connection pull down menu and change it to mb_opb




Port connection

All OPB signals have already been connected to OPB bus. The remaining signals can be connected using the port view. We will make all signals external. Some input signals not used will be connected to ground and some unused output signals will be left unconnected.




Generate addresses

Select the Address filter to define addresses for the newly added ETC peripheral. The address can be assigned by entering the Base Address or the tool can assign an address. We will let the tool generate addresses:
  • Change the size of the memory blocks to 1K and for the register map to 4.
  • Click the Generate Addresses


A message in the console window will state that the address map has been generated successfully. The design is now ready to be implemented.

Mixed language design

All IP blocks from Xilinx are written in VHDL. The ETC IP is written in Verilog and therefor this design will be a mixed language design. The synthesis and simulation tools have no problems dealing with mixed language designs and hopefully this will not complicate our design job.

Set project options


Select Project->Project Options and click the HDL and Simulation tab. Because the majority of the design is in VHDL we will generate a VHDL top entity file. We will use NCSim for our simulations and we will allow mixed language behavioral files.





Generate the system netlist

We can now generate the system netlist. Click Hardware->Generate Netlist. The generation starts and returns with the following error message:

ERROR:MDT - INST:ETC_0 PORT:I_OPB_BE CONNECTOR:mb_opb_OPB_BE -
   /home/svenand/root/projects/ETC/xps/pcores/ETC_v1_00_a/data/ETC_v2_1_0.mpd
   line 43 - calculated index is out of signal VEC range of [0:3]

Completion time: 1.00 seconds

ERROR:MDT - platgen failed with errors!

make:
*** [implementation/microblaze_0_wrapper.ngc] Error 2

Done!

Let's open the
ETC_v2_1_o.mpd file and figure out what the problem is. The OPB_BE signal is a four bit bus and not a one bit signal as I thought. If we add VEC [0:3] to the OPB_BE definition this problem will be fixed and we can rerun the netlist generation.

This is incredible. The whole netlist generation runs without any problems and it took less than 10 minutes on my MacBook using a virtual machine (Parallels Desktop) and Ubuntu Linux. Here is the
log file and here are all the warnings.

What happend during the netlist generation

When we start the netlist generation the following command is executed: platgen -p xc4vfx12ff668-10 -lang vhdl   ETC_system.mhs


                                                                                                 (Courtesy of Xilinx)

Hardware generation is accomplished with the Platform Generator (Platgen) tool. Platgen constructs the programmable system on a chip in the form of hardware netlists (HDL and implementation netlist files). Platgen creates a hardware platform using the Microprocessor Hardware Specification (MHS) file as input. In addition to netlist files in various formats such as NGC and EDIF, Platgen creates support files for downstream tools and top-level HDL wrappers to allow you to add other components to the automatically generated hardware platform. Read more about Platgen in the
Embedded Systems Tools Guide  (chapter 2).

During the Platgen run the following directories have been created and filled with files.
  • hdl
  • implementation
  • synthesis
The HDL directory contains all the HDL verilog and VHDL wrapper files that instantiates the IP blocks used in the design. The VHDL IPs always have VHDL wrappers and the Verilog IPs have Verilog wrappers. The top module ETC_system.vhd is a VHDL entity because we specified a VHDL netlist to be generated.



The implementation directory holds all the NGC files. The NGC file is a netlist that contains logical design data and constraints. This file replaces both EDIF and Netlist Constraints (NCF) files.




The synthesis directory holds all synthesis scripts used when running the syntesis tool XST.




We are now ready to program the FPGA on the evaluation board and start debugging the design. But before we do that we will setup a simulation environment and simulate the whole design. I am an old ASIC designer. Always simulate before implement.

Generate simulation HDL files

We will try the Xilinx HDL simulation environment. To generate the simulation setup goto the Simulation menu and select Generate Simulation HDL Files. The following script will start: make -f ETC_system.make simmodel. When the script has finished a new directory called simulation has been created.



Here is the
simgen log file.

Why simulate an embedded design
  • Using simulation, you don't have to wait for hardware to be complete before testing your software. The result: facilitated software development, which allows you meet more aggressive project deadlines.
  • Simulation provides insight into the internal workings of your system. Signals and register values are more accessible in a simulated system than they are once a design is in hardware.
  • Simulation also allows you complete control of your system. Conditions that may be difficult to create in a hardware setting are relatively easy to simulate.
Running a simulation in XPS

We will take these steps to start a simulation using NCSIM:
  1. cd /home/svenand/root/projects/ETC/xps/simulation/behavioral
  2. chmod 777 ETC_system.sh (make script executable)
  3. chmod 777 ETC_system_setup.sh
  4. Edit the ETC_system_setup.sh file and change -lib_binding to -relax
  5. Start the simulation script: ./ETC_system_setup.sh
Here are instructions from Xilinx on how to use NCSIM.

Read chapter 7 in the
EDK Concepts, Tools, and Techniques guide to find out more about simulating our design. Before we can start our simulation we need to write a simple software application that will run in our system. We will come back to simulation when we have finished this task.

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Posted at 18:59 by svenand

 

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