My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
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Any piece of IP you create must be compliant with the system that is in place. To ensure compliance, the following must occur:
The interface required by your IP must be determined. The bus to which your custom peripheral will attach must be identified. For example: a. Processor Local Bus (PLB). The PLB provides a high-speed interface between the processor and high-performance peripherals. b. On-chip Peripheral Bus (OPB). The OPB allows processor access to low-speed, low-performance system resources.
Functionality must be implemented and verified. Your custom functionality must be implemented and verified, with awareness that common functionality available from the EDK peripherals library can be reused. Your stand-alone core must be verified. Isolating the core ensures easier debug in the future.
The IP must be imported to EDK. Your peripheral must be copied to an EDK-appropriate directory, and the Platform Specification Format (PSF) interface files (MPD and PAO) must be created, so other EDK tools can recognize your peripheral.
Your peripheral must be added to the processor system created in XPS.
Create or import an user peripheral
One of the key advantages of building an embedded system in an FPGA is the ability to include customer IP and interface that IP to the processor. To start the Create and Import Peripheral Wizard select Hardware->Create or Import Peripheral.
Click the More Info button for more information. We will import an existing peripheral.
We will call our peripheral ETC (the name of the top module) and add a version to the name.
The peripheral is made up of Verilog files (.v).
We will use the ISE project file to define the Verilog source code.
Here are all the verilog source files.
The ETC peripheral will operate as an OPB slave (SOPB) and the OPB interface is already designed and verified. The On-chip Peripheral Bus(OPB) is an IBM standard and is also used in the Power PC processor.
The wizard tries to map the ETC interface names to the standard naming convention for OPB. All the names that don't match have to be manually inserted.
It seems like we are missing some of the optional OPB signals. I have to add these signals to the top module ETC.v. I will add the missing pins and also some parameter statements defining register and memory address ranges. Like this:
In this window we have to select the right parameters defining the address range for registers and memory banks.
Here we define the interrupt signal and the operation of the interrupt.
Congratulations! We have added our peripheral to the current XPS project. Good work.
Here are all files in the pcores directory.
XPS provides an interactive development environment that allows you to specify all aspects of your hardware platform. XPS maintains your hardware platform description in a high-level form, known as the Microprocessor Hardware Specification (MHS) file. The MHS, an editable text file, is the principal source file representing the hardware component of your embedded system. XPS synthesizes the MHS source file into Hardware Description Language (HDL) netlists ready for FPGA place and route.
The MHS File
The MHS file is integral to your design process. It contains all peripherals along with their parameters. The MHS file defines the configuration of the embedded processor system and includes information on the bus architecture, peripherals, processor, connectivity, and address space. For more detailed information on the MHS file, refer to the "Microprocessor Hardware Specification (MHS)" chapter of the Platform Specification Format Reference Manual, available at http://www.xilinx.com/ise/embedded/edk_docs.htm. XPS Project Files