Xilinx Platform Studio XPS Software Development Kit SDK Create a new project in XPS Generate a design report file
Part 16 Create or import an user peripheral The MHS file XPS project files Xilinx IP center
Part 17 Adding the ETC IP Generate the system netlist using platgen What happend during the netlist generation Generate simulation HDL files
Part 18 Putting together a system simulation environment The simulation database The cds.lib file Compiling the ETC IP Compiling the block RAM Compiling Verilog wrappers Compiling VHDL wrappers Elaborating the design Warning messages
Part 19 Generating a Verilog testbench Part 20 Running our first simulation Adding the DDR SDRAM Suppressing assert messages in IEEE packages Part 21 Debugging the simulation testbench The reset logic Part 22 Using the XPS software development kit (SDK) Software development flow GNU compiler collection (gcc) Running SDK Creating a new C appilcation project Part 23 Simulating program execution in the MicroBlaze processor Verification strategy Verification flow Writing a simple c program Loading the program Running an NCSIM simulation Simulation result Compile and build the program inside SDK Generate assembly code and hex code Make a NCSIM memory load file Running a simulation
Part 24 System simulations DDR SDRAM controller LED displays and push buttons OPB GPIO registers Embedded test controller Debugging the On-Chip Peripheral bus
Part 25 Implementing the hardware platform User constraints file Setting up our constraints file Specify pin constraints Specify timing constraints The implementation directory Start bitstrem generation Bitstream generation flow Scriptfile to run XFlow Bitstream generation result Configuration of the FPGA Using the platform cable USB ML403 evaluation board ML403 block diagram Installing cable drivers Xilinx JTAG tools on Linux without proprietary kernel modules Setting up the USB cable iMPACT FPGA configuration tool Starting iMPACT
Part 26 Using the iMPACT configuration tool Boundary Scan and JTAG configuration IEE standard 1149.1 (JTAG) The identification register Read IDCODE Read the FPGA status register Device configuration Using Xilinx Platform Studio
Part 27 Pin assignment closure process PACE Pin and Area Constraint Editor Running PACE Topi the Top Code Generator Topi setup Using Topi to modify the Xilinx user constraints file Xilinx Floorplanner Viewing pin placement Xilinx PlanAhead
Part 28 Power calculations XPower Low power consumption
Part 29 Hardware setup Software setup Download and execute a simple program Download the bitstream Get program size Running the program
Part 30 Running demonstration software applications ML403 Reference Systemson the CD
Part 31 Adding a 16x2 character LCD display Set address range Connecting ports The easy way to add a new block Configure the IP block The LCD driver LCD display timing 8-bit write operation Programming sequence Display setup More reading Signal wiring on the ML403 board Adding constraints Generate netlist Generate bitstream
Part 32 Writing the "Hello World" program SDK platform settings C program build C header files The GPIO API definitions C program examples Device configuartion in SDK Part 33 Simulating the LCD driver C program Program execution (Waveform plot) Generating the software libraries and BSPs GNU compiler tools Input files Output files Output from SDK build process Display program size
Part 34 Program disassembly MicroBlaze software reference guide System memory layout Reset sequence ELF file content Startup files First stage initialization files Second stage initialization files Part 35 Generate simulation HDL files Simgen Data2MEM memory tool ETC_system_sim.bmm ETC_system_init.vhd ETC_system_tb.vhd Modifying the testbench file Compiling the BRAM initialization file Compiling the testbench Simulating program execution Part 36 The LCD driver (once more) Editing the user constraints file Generate new bitstream Device configuration Application program Displaying "Hello World"
Part 37 Debugging our design Xilinx microprocessor debugger and GNU software debugging tools Xilinx microprocessor debugger (XMD) MicroBlaze processor target MicroBlaze MDM hardware setup Debug session Reading registers in MicroBlaze Load program Set breakpoint Remove breakpoint Display breakpoints Start program execution Single step Stop program execution Display program code Getting help Using XMD in Xilinx Platform Studio
Part 38 Writing software for our embedded system Writing a software device driver Software development overview Device driver programmer guide Platform specification format reference manual Microprocessor Driver Definition (MDD) Libraries and driver generation Device driver architecture xparameters.h Software driver source code Source code repository Software device drivers used SDK project directory Header source files
Part 39 Fixing our software driver etc_v2_1_0.tcl etc_v2_1_0.mdd Makefile xetc_g.c xetc.h xetc_l.h Writing an application program Print statements Printout from program Generate HDL simulation files Generating the BRAM initialization file Running a simulation
Part 40 Debugging our hardware design ChipScope Pro Trying out ChipScope Pro ChipScope installation
Part 41 Adding an interrupt controller Finding an interrupt controller OPB_INTC Register map Configuring the interrupt controller Making connections Software setup xparameters.h xintc_l.h Generate a software interrupt Generate a hardware interrupt MicroBlaze interrupt handling MicroBlaze interrupt timing Part 42 Adding a timer Connect the interrupt signal OPB Timer/Counter Register address map Library generation Application program Simulation results Part 43 Installing a Linux OS Why using a Linux OS Embedded Linux OS µClinux Finding a linux OS Choosing a Linux OS PetaLinux
Part 44 Adding an external memory controller Generate addresses Software platform settings OPB External Memory Controller
Part 45 A computer cache Enabling MicroBlaze caches Specify cacheable memory segment Instruction cache operation Data cache operation Xilinx cachelink XCL Adding the MCH_OPB_DDR_SDRAM controller Connect IXCL and DXCL Connecting ports ETC_system.mhs Part 46 Installing and running the Linux OS Disassembly of the Linux kernel Download the Linux kernel
Munis November 7, 2009 10:49 AM PST Absolutely brilliant stuff you have posted here! million thanks!
Max August 7, 2009 01:52 PM PDT Well Done!
Ethan June 25, 2009 06:53 PM PDT I have been working in FPGA design area for more than 5 years. Always made notes myselft recording own learning curve in the flood of documentations. Never had clear index for beginners to start with. Your work looks just as the ultimate brillant solution, will be extremely helpful for any stage learners.
Thank you very much!!!
Jon July 9, 2008 05:07 PM PDT Excellent work. This tutorial has really helped me get up and running. Why doesn't Xilinx documentation have something this straight-forward that explains their tools?
Laurent February 19, 2008 08:14 PM PST Great Work! Thanks! Laurent from Paris
Anup Raghavan August 31, 2007 08:02 AM PDT I bow to you Sven. I am very impressed with your tutorial and the presentation style. I can imagine the fun you would have had doing the project, but documenting it with step by step instructions is a work of art on its own. Hats off! Thank you for your contribution and knowledge sharing.
Anup
sushil August 31, 2007 02:21 AM PDT Hi Sven,
Over last two years I am struggling to learn FPGA's, I already have the kits etc with me but it was really hard to get started as I do not have background in H/W, dont even know VHDL/Verilog!!!
Your tutorial here is extensive, better coverage than any book I have looked at, and better still, it comes from your real life experience. I am impressed!
I want to thank you a million times, and hopefully this time my effort would take-off :)
Thanks again, I appreciate the hard work and time you have put in assembling this.
