New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Thursday, December 28, 2006
FPGA design from scratch. Table of content
Part 1

Introduction
Ordering the MicroBlaze development kit
Installing the Integrated Software Environment (ISE)
Running a board demo test

Part 2

Design object description

Part 3

Setting up the ISE design software
Running the
ISE design software

Part 4

Adding Verilog source code
Generating memories using Coregen
Synthesizing the design
Simulating the design (Introduction)


Part 5

Setting up the simulation environment using Mongoose

Part 6

The simulation process
Compiling macro libraries
Compiling the design
Compiling the testbench
Elaborating everything

Part 7

Testbench description

Part 8

Using HAL the HDL analysis and linting tool from Cadence

Part 9

Regression testing using Mongoose

Part 10

Synthesis using timing constraints (Introduction)

Part 11


The Field Programmable Gate Array (FPGA) description

Part 12

Adding synthesis constraints

Part 13

The MicroBlaze soft processor core
Compiling simulation libraries using compedklib


Part 14

Putting everything together
Installing ISE WebPack 9.1i
Installing EDK 9.1i


Part 15

Xilinx Platform Studio XPS
Software Development Kit SDK
Create a new project in XPS
Generate a design report file


Part 16

Create or import an user peripheral
The MHS file
XPS project files
Xilinx IP center


Part 17

Adding the ETC IP
Generate the system netlist using platgen
What happend during the netlist gener
ation
Generate simulation HDL files

Part 18

Putting together a system simulation environment
The simulation database
The cds.lib file
Compiling the ETC IP
Compiling the block RAM
Compiling Verilog wrappers
Compiling VHDL wrappers
Elaborating the design
Warning messages


Part 19

Generating a Verilog testbench

Part 20

Running our first simulation
Adding the DDR SDRAM
Suppressing assert messages in IEEE packages

Part 21

Debugging the simulation testbench
The reset logic

Part 22

Using the XPS software development kit (SDK)
Software development flow
GNU compiler collection (gcc)
Running SDK
Creating a new C appilcation project

Part 23

Simulating program execution in the MicroBlaze processor
Verification strategy
Verification flow
Writing a simple c program
Loading the program
Running an NCSIM simulation
Simulation result
Compile and build the program inside SDK
Generate assembly code and hex code
Make a NCSIM memory load file
Running a simulation


Part 24

System simulations
DDR SDRAM controller
LED displays and push buttons
OPB GPIO registers
Embedded test controller
Debugging the On-Chip Peripheral bus


Part 25

Implementing the hardware platform
User constraints file
Setting up our constraints file
Specify pin constraints
Specify timing constraints
The implementation directory
Start bitstrem generation
Bitstream generation flow
Scriptfile to run XFlow
Bitstream generation result
Configuration of the FPGA
Using the platform cable USB
ML403 evaluation board
ML403 block diagram
Installing cable drivers
Xilinx JTAG tools on Linux without proprietary kernel modules
Setting up the USB cable
iMPACT FPGA configuration tool
Starting iMPACT


Part 26

Using the iMPACT configuration tool
Boundary Scan and JTAG configuration
IEE standard 1149.1 (JTAG)
The identification register
Read IDCODE
Read the FPGA status register
Device configuration
Using Xilinx Platform Studio


Part 27

Pin assignment closure process
PACE Pin and Area Constraint Editor
Running PACE
Topi the Top Code Generator
Topi setup
Using Topi to modify the Xilinx user constraints file
Xilinx Floorplanner
Viewing pin placement
Xilinx PlanAhead


Part 28

Power calculations
XPower
Low power consumption


Part 29

Hardware setup
Software setup
Download and execute a simple program
Download the bitstream
Get program size
Running the program


Part 30

Running demonstration software applications
ML403 Reference Systemson the CD


Part 31

Adding a 16x2 character LCD display
Set address range
Connecting ports
The easy way to add a new block
Configure the IP block
The LCD driver
LCD display timing
8-bit write operation
Programming sequence
Display setup
More reading
Signal wiring on the ML403 board
Adding constraints
Generate netlist
Generate bitstream


Part 32

Writing the "Hello World" program
SDK platform settings
C program build
C header files
The GPIO API definitions
C program examples

Device configuartion in SDK

Part 33

Simulating the LCD driver
C program
Program execution (Waveform plot)
Generating the software libraries and BSPs
GNU compiler tools
Input files
Output files
Output from SDK build process
Display program size


Part 34

Program disassembly
MicroBlaze software reference guide
System memory layout
Reset sequence
ELF file content
Startup files
First stage initialization files
Second stage initialization files


Part 35

Generate simulation HDL files
Simgen
Data2MEM memory tool
ETC_system_sim.bmm
ETC_system_init.vhd
ETC_system_tb.vhd
Modifying the testbench file
Compiling the BRAM initialization file
Compiling the testbench
Simulating program execution

Part 36

The LCD driver (once more)
Editing the user constraints file
Generate new bitstream
Device configuration
Application program
Displaying "Hello World"

Part 37

Debugging our design
Xilinx microprocessor debugger and GNU software debugging tools
Xilinx microprocessor debugger (XMD)
MicroBlaze processor target
MicroBlaze MDM hardware setup
Debug session
Reading registers in MicroBlaze
Load program
Set breakpoint
Remove breakpoint
Display breakpoints
Start program execution
Single step
Stop program execution
Display program code
Getting help
Using XMD in Xilinx Platform Studio


Part 38

Writing software for our embedded system
Writing a software device driver
Software development overview
Device driver programmer guide
Platform specification format reference manual
Microprocessor Driver Definition (MDD)
Libraries and driver generation
Device driver architecture
xparameters.h
Software driver source code
Source code repository
Software device drivers used
SDK project directory
Header source files


Part 39

Fixing our software driver
etc_v2_1_0.tcl
etc_v2_1_0.mdd
Makefile
xetc_g.c
xetc.h
xetc_l.h
Writing an application program
Print statements
Printout from program
Generate HDL simulation files
Generating the BRAM initialization file
Running a simulation


Part 40

Debugging our hardware design
ChipScope Pro
Trying out ChipScope Pro
ChipScope installation


Part 41

Adding an interrupt controller
Finding an interrupt controller
OPB_INTC
Register map
Configuring the interrupt controller
Making connections
Software setup
xparameters.h
xintc_l.h
Generate a software interrupt
Generate a hardware interrupt
MicroBlaze interrupt handling
MicroBlaze interrupt timing

Part 42

Adding a timer
Connect the interrupt signal
OPB Timer/Counter
Register address map
Library generation
Application program
Simulation results


Part 43

Installing a Linux OS
Why using a Linux OS
Embedded Linux OS
µClinux
Finding a linux OS
Choosing a Linux OS
PetaLinux



Part 44

Adding an external memory controller
Generate addresses
Software platform settings
OPB External Memory Controller


Part 45

A computer cache
Enabling MicroBlaze caches
Specify cacheable memory segment
Instruction cache operation
Data cache operation
Xilinx cachelink XCL
Adding the MCH_OPB_DDR_SDRAM controller
Connect IXCL and DXCL
Connecting ports
ETC_system.mhs

Part 46

Installing and running the Linux OS
Disassembly of the Linux kernel
Download the Linux kernel

Part 51

Installing Design Suite 13.2


Part 52

ISE Design Navigator

Part 53


Xilinx Platform Studio

Part 54


Using the ISE Simulator

Part 55


Creating a MicroBlaze Peripheral Interface

Part 56


Adding a PLB interface

Part 57


Fixing a hyperterminal

Part 58


Using the Software Development Kit

Part 59


Running a simulation

Part 60


Looking for a new development board

Part 61


MicroBlaze Soft Processor


























Top




Posted at 07:38 by svenand

Ali
January 4, 2011   05:42 AM PST
 
Hi,
I'd like to say WOW !! SERIOUSLY THIS IS AWESOME !!!
I'm working on a project in university, using the MicroBlaze, and your articles are a great help.
Thanks for putting so much time and effort into writing this documentation.
Would you happen to have a book collecting all these articles ?
Wii Mod
November 23, 2010   03:21 AM PST
 
Absolutely brilliant stuff you have posted here! million thanks!
Munis
November 7, 2009   10:49 AM PST
 
Absolutely brilliant stuff you have posted here! million thanks!
Max
August 7, 2009   01:52 PM PDT
 
Well Done!
Ethan
June 25, 2009   06:53 PM PDT
 
I have been working in FPGA design area for more than 5 years. Always made notes myselft recording own learning curve in the flood of documentations. Never had clear index for beginners to start with. Your work looks just as the ultimate brillant solution, will be extremely helpful for any stage learners.
Thank you very much!!!
Jon
July 9, 2008   05:07 PM PDT
 
Excellent work. This tutorial has really helped me get up and running. Why doesn't Xilinx documentation have something this straight-forward that explains their tools?
Laurent
February 19, 2008   08:14 PM PST
 
Great Work! Thanks! Laurent from Paris
Anup Raghavan
August 31, 2007   08:02 AM PDT
 
I bow to you Sven. I am very impressed with your tutorial and the presentation style. I can imagine the fun you would have had doing the project, but documenting it with step by step instructions is a work of art on its own. Hats off! Thank you for your contribution and knowledge sharing.
Anup
sushil
August 31, 2007   02:21 AM PDT
 
Hi Sven,
Over last two years I am struggling to learn FPGA's, I already have the kits etc with me but it was really hard to get started as I do not have background in H/W, dont even know VHDL/Verilog!!!

Your tutorial here is extensive, better coverage than any book I have looked at, and better still, it comes from your real life experience. I am impressed!

I want to thank you a million times, and hopefully this time my effort would take-off :)

Thanks again, I appreciate the hard work and time you have put in assembling this.

-Sushil
 

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