My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
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We will use the MicroBlaze soft processor as the main controller in our system. The MicroBlaze™ soft processor is a 32-bit Harvard RISC architecture optimized for Xilinx FPGAs. The basic architecture consists of 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt. We can configure this basic design with more advanced features to allow us to balance the required performance of the target application against the logic area cost of the soft processor.
(Courtesy of Xilinx) Here is the reference guide to download. Installation of the Embedded Development Kit (EDK)
The Embedded Development Kit provides you with a complete tool chain for the creation of your Virtex™ and Spartan™ series embedded PowerPC™ 405 and MicroBlaze™ designs. You find all the documentation here.
To install the Linux version of EDK follow these steps.
Insert the Embedded Development Kit DVD. This DVD is part of the ML401 development kit.
Open a terminal window and type cd /media/cdrom0 or whatever the path is to the cdrom.
Execute the setup script ./setup. If everything goes fine the Xilinx Install Program window will be displayed.
If you get the following error message when running the setup script it probably means that the system doesn't allow you to execute programs on the DVD: bash: ./setup: /bin/sh: bad interpreter: Permission denied.
To fix this problem you have to edit the file /etc/fstab (static file system information) and add execute permission to the line defining the cdrom. Here is an example: /dev/hdb /media/cdrom0 udf,iso9660 user,noauto,exec 0 0
Fill in all information and have the EDK product ID available, found on the back of EDK Development Kit DVD.
The registration code will appear in the web browser and will also be sent to the email address you specified.
Read all license agreements carefully !!! and click the agree check boxes.
Insert the registration code when asked for.
Specify the destination directory where the EDK software will be installed.
Start the installation
When the installation has finished we will see the following file tree structure.
The files settings.csh and settings.sh contains setting of environment variables used by EDK. If you use a bash or sh shell add the line: source edk_install_dir/settings.sh to your shell startup file. If you use csh or tcsh add the line: source edk_install_dir/settings.csh to your shell startup file.
Now it is time to find the MicroBlaze VHDL source code. I wonder where it can be and in what format it is. Let's look in the hw directory.
All the IP vendors protect their intellectual property using different forms of encryption. The MicroBlaze VHDL source code is encrypted and can not be read, modified or understood. It can be compiled using the Cadence ncvhdl compiler and you don't need to specify any special flags for the compilation.
The UNISIM Library is a library of functional models used for behavioral and structural simulation. It includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools. The UNISIM library also includes components that are commonly instantiated, such as I/Os and memory cells. We can instantiate the UNISIM library components in our design (VHDL or Verilog) and simulate them during behavioral simulation. All asynchronous components in the UNISIM library have zero delay. All synchronous components have a unit delay to avoid race conditions. The clock-to-out delay for these is 100 ps.
The SIMPRIM Library is used for timing simulation. It includes all the Xilinx Primitives Library components used by Xilinx implementation tools.
The Xilinx CORE Generator™ is a graphical Intellectual Property (IP) design tool for creating high-level modules like FIR Filters, FIFOs, CAMs, and other advanced IP. We can customize and pre-optimize modules to take advantage of the inherent architectural features of Xilinx FPGA devices, such as block multipliers, SRLs, fast carry logic and onchip, single-port or dual-port RAM. The CORE Generator HDL library models are used for behavioral simulation. We can select the appropriate HDL model to integrate into our HDL design. The models do not use library components for global signals.
The EDK Library is used for behavioral simulation. It contains all the EDK IP components, precompiled for ModelSim SE and PE or NcSim. This library eliminates the need to recompile EDK components on a per-project basis, minimizing overall compile time. The EDK IP components library is provided for VHDL only and may be encrypted. The Xilinx CompEDKLib utility deploys compiled models for EDK IP components into a common location. Unencrypted EDK IP components can be compiled using CompEDKLib. Precompiled libraries are provided for encrypted components.
To find out how to compile all the libraries and all the IP blocks for the IUS simulator we first read the Embedded Systems Tools Guide. It tells us to use the Xilinx program compedklib to perform the compilation of all the libraries. We will use the program in GUI mode. Let's start. But before we start we will delete all old libraries we have compiled before. If not we may see a lot of compilation errors.
Select the simulator to use.
Select directories to store compiled libraries.
Select directory to store EDK libs
Compile ISE and EDK libraries
Here is the result.
Now when we have everything compiled it is time to start building the complete simulation environment.That is the subject for the next chapter in this story.