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Table of content

New Horizons
What's new
Starting a blog
Writing a blog
I got a job

SystemC
SystemC from scratch. Part 1
SystemC from scratch. Part 2
SystemC from scratch. Part 3

ASIC/FPGA Design
Table of content
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
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XCell Journals
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A processor benchmark
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Fixing a HyperTerminal in Mac OS X
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Dec 6, 2006
FPGA design from scratch. Part 12
Adding synthesis constraints

Constraints are essential to help you meet your design goals or obtain the best implementation of your circuit. Constraints are available in XST to control various aspects of the synthesis process itself, as well as placement and routing. Synthesis algorithms and heuristics have been tuned to automatically provide optimal results in most situations. In some cases, however, synthesis may fail to initially achieve optimal results; some of the available constraints allow you to explore different synthesis alternatives to meet your specific needs.

XST constraints can be specified in a file called the Xilinx Constraint File (XCF). The XCF must have an extension of .xcf.
To add a synthesis constraints file open the Synthesis Options window by right-clicking Synthesize - XST in the Proceses window and select Properties. Mark the Use Synthesis Constraints File box and fill in the name of the Synthesis Constraints File : /home/svenand/root/projects/ETC/synthesis/constraints/ETC_constraints.xcf



This
table shows all synthesis constraints available for XST.

Here is the constraints file I am using to make a safe implementation of the case statements in the ETC_CONFIG module.

BEGIN MODEL ETC_CONFIG
   NET jtc_tck_source       safe_implementation = yes;
   NET tdo_source           safe_implementation = yes;
   NET jtc_tms_source       safe_implementation = yes;
   NET jtc_trstz_source     safe_implementation = yes;
   NET jtc_tdi_source       safe_implementation = yes;
   NET mtc_tdo_source       safe_implementation = yes;
END;

When we rerun the synthesis we will see the following messages appear in the report file:

Analyzing module <ETC_CONFIG> in library <work>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tms_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tck_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_trstz_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <mtc_tdo_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <tdo_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tdi_source> in unit <ETC_CONFIG>.

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Posted at 03:56 pm by svenand

sunil
May 27, 2009   01:11 PM PDT
 
Can you let me know how to specify a clock constraint in xcf file?
 

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