New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

If you want to be updated on this weblog Enter your email here:

rss feed

Wednesday, December 06, 2006
FPGA design from scratch. Part 12
Adding synthesis constraints

Constraints are essential to help you meet your design goals or obtain the best implementation of your circuit. Constraints are available in XST to control various aspects of the synthesis process itself, as well as placement and routing. Synthesis algorithms and heuristics have been tuned to automatically provide optimal results in most situations. In some cases, however, synthesis may fail to initially achieve optimal results; some of the available constraints allow you to explore different synthesis alternatives to meet your specific needs.

XST constraints can be specified in a file called the Xilinx Constraint File (XCF). The XCF must have an extension of .xcf.
To add a synthesis constraints file open the Synthesis Options window by right-clicking Synthesize - XST in the Proceses window and select Properties. Mark the Use Synthesis Constraints File box and fill in the name of the Synthesis Constraints File : /home/svenand/root/projects/ETC/synthesis/constraints/ETC_constraints.xcf

table shows all synthesis constraints available for XST.

Here is the constraints file I am using to make a safe implementation of the case statements in the ETC_CONFIG module.

   NET jtc_tck_source       safe_implementation = yes;
   NET tdo_source           safe_implementation = yes;
   NET jtc_tms_source       safe_implementation = yes;
   NET jtc_trstz_source     safe_implementation = yes;
   NET jtc_tdi_source       safe_implementation = yes;
   NET mtc_tdo_source       safe_implementation = yes;

When we rerun the synthesis we will see the following messages appear in the report file:

Analyzing module <ETC_CONFIG> in library <work>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tms_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tck_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_trstz_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <mtc_tdo_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <tdo_source> in unit <ETC_CONFIG>.
    Set property "SAFE_IMPLEMENTATION = yes" for signal <jtc_tdi_source> in unit <ETC_CONFIG>.

Top  Next  Previous

Posted at 15:56 by svenand


Leave a Comment:


Homepage (optional)


Previous Entry Home Next Entry