Basic process technology types

• SRAM - based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS.
• Antifuse - One-time programmable. CMOS.
• EPROM - Erasable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
• EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS.
• Flash - Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
• Fuse - One-time programmable. Bipolar.

FPGA manufacturers and their specialties

As of late 2006, the FPGA market has mostly settled into a state where there are two major "general-purpose" FPGA manufacturers and a number of other players who differentiate themselves by offering unique capabilities.

• Xilinx and Altera are the current FPGA market leaders.
• Lattice Semiconductor provides both SRAM and non-volatile, flash-based FPGAs.
• Actel has antifuse and reprogrammable flash-based FPGAs, and also offers mixed signal flash-based FPGAs.
• Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx were. They focus on providing AVR Microcontrollers with FPGA fabric on the same die.

I have chosen to use a Xilinx FPGA in this story not because it is better or more powerful then the competitors, but it has the MicroBlaze soft processor core which is important to me. The evaluation board I purchased contains a Xilinx Virtex-4 FPGA device (XC4VFX12). Here is a good start to the Xilinx FPGA world.

the XC4VFX12 and see what's inside the chip.



                                                                                                                                                          (Courtesy of Xilinx)
Logic Cells

A logic cell is defined by Xilinx to be one 4 input

+ a flip flop + carry logic. The XC4FX12 has 12,312 logic cells. A logic cell looks like this:




Configurable Logic Blocks

• CLB is optimized for area and speed for compact high performance design.
• Four slices per CLB implement any combinatorial and sequential circuit.
• Each slice has 4-input look-up tables (LUT), flip-flops, multiplexors, arithmetic logic, carry logic, and dedicated internal routing.
• Dedicated AND/OR logic implements wide input functions.

Shift Register SRL16 block

• Configure any CLB LUT (Look-Up Table) to work as a fast, compact, 16-bit shift register.
• Cascade LUTs to build longer shift registers.
• Implement pipeline registers and buffers for video, wireless.

Distributed RAM

• Configure any LUT to work as a single-port or dual-port 16-bit RAM/ROM.
• Cascade LUTs to build larger memories.
• Applications include flexible memory sizes, FIFOs, and buffers.

Embedded Block RAM

• 36 blocks of cascadable, synchronous 18 Kbit block RAM.
• Configure any 18 Kbit block as a single/dual-port RAM.
• Supports multiple aspect ratios, data-width conversion, and parity.
• Applications include data caches, deep FIFOs, and buffers.
• The maximum size of a block RAM is 648 kbits
  

• Clock deskew. The DCM contains a delayed-locked loop to completely eliminate clock distribution delays.
• Frequency Synthesis. Separate outputs provide a doubled frequency. Another output provides a frequency that is a specified fraction of the input.
• Phase shifting. The DCM allows coarse and fine-grained phase-shifting.

                                                                    (Courtesy of Xilinx)
Ethernet MAC

The XC4VFX12 FPGA has built-in Ethernet connectivity with two Ethernet media access controller (MAC) blocks. The Xilinx unique tri-mode Ethernet MAC provides guaranteed performance and UNH-verified interoperability. This integrated functionality reduces total system cost by reducing design and verification effort, freeing approximately 1,800 logic cells per Ethernet MAC in the FPGA fabric.

Summary

The XC4VFX12FPGA device has 12,312 logic cells. We will use about 1200 logic cells for the design excluding the MicroBlaze soft processor core. The MicroBlaze will use between 800 to 2600 LUTs. For the block RAM we will use 64 kbits out of 648 kbits. There is plenty of room for future expansions.

More to read

If you want to know more about FPGA design look for a book at Amazon.com.

Training

Here are some companies providing training for Xilinix users. There are many more.

• Active Media
• BitSim Sweden
• BlackBox Consulting Australia
• Esperan
• Technically Speaking
• Xilinx