Thursday, December 07, 2006
FPGA design from scratch. Part 11
Before we continue our FPGA design journey we will make a short stop and take a closer look at the leading actor/actress in this story. The FPGA device itself.
The Field Programmable Gate Array
If you are not involved in electronic design this header makes no sense to you. Is it a computer game where you try to arrange an array of gates out in a corn field or what is it? Let's start by explaining the gate array part first. We will turn to the Wikipedia encyclopedia for an explanation as we have done so many times before in this story.
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICS). A gate array circuit is a prefabricated silicon chip circuit with no particular function in which transistors, standard NAND or NOR logic gates, and other active devices are placed at regular predefined positions and manufactured on a wafer, usually called master slice. Creation of a circuit with a specified function is accomplished by adding a final surface layer metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customised as desired. This layer is analogous to the copper layer of a single-sided printed circuit board PCB.
Instead of having to manufacture the gate array at an expensive silicon foundry we can make it programmable by the user (in the field) and we will come up with a field programmable gate array.
A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.
Basic process technology types
- SRAM - based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. CMOS.
- Antifuse - One-time programmable. CMOS.
- EPROM - Erasable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
- EEPROM - Electrically Erasable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS.
- Flash - Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
- Fuse - One-time programmable. Bipolar.
FPGA manufacturers and their specialties
As of late 2006, the FPGA market has mostly settled into a state where there are two major "general-purpose" FPGA manufacturers and a number of other players who differentiate themselves by offering unique capabilities.
- Xilinx and Altera are the current FPGA market leaders.
- Lattice Semiconductor provides both SRAM and non-volatile, flash-based FPGAs.
- Actel has antifuse and reprogrammable flash-based FPGAs, and also offers mixed signal flash-based FPGAs.
- Atmel provides fine-grain reconfigurable devices, as the Xilinx XC62xx were. They focus on providing AVR Microcontrollers with FPGA fabric on the same die.
I have chosen to use a Xilinx FPGA in this story not because it is better or more powerful then the competitors, but it has the MicroBlaze soft processor core which is important to me. The evaluation board I purchased contains a Xilinx Virtex-4 FPGA device (XC4VFX12). Here is a good start to the Xilinx FPGA world.The Virtex-4 FPGA familyThe Virtex-4 family of FPGAs was introduced 2004 and includes three platforms; Virtex-4 LX for logic, Virtex-4 SX for very high performance signal processing, and Virtex-4 FX for embedded processing and high-speed serial connectivity. Each version has a different mix of the special features and comes in a range of density to cover a variety of application sizes. Here is the data sheet
. (Courtesy of Xilinx)
These product tables show the different platforms and which features are included. To find out more about the Virtex-4 family read the user guide (pdf). Let's take a look at the XC4VFX12 and see what's inside the chip.
(Courtesy of Xilinx)
A logic cell is defined by Xilinx to be one 4 input LUT + a flip flop + carry logic. The XC4FX12 has 12,312 logic cells. A logic cell looks like this:
Configurable Logic Blocks
The Configurable Logic Block (CLB) is the basic logic unit in an FPGA. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers, or RAM.
(Courtesy of Xilinx)
- CLB is optimized for area and speed for compact high performance design.
- Four slices per CLB implement any combinatorial and sequential circuit.
- Each slice has 4-input look-up tables (LUT), flip-flops, multiplexors, arithmetic logic, carry logic, and dedicated internal routing.
- Dedicated AND/OR logic implements wide input functions.
There are several ways you can build a memory in the XC4VFX12.
Shift Register SRL16 block
- Configure any CLB LUT (Look-Up Table) to work as a fast, compact, 16-bit shift register.
- Cascade LUTs to build longer shift registers.
- Implement pipeline registers and buffers for video, wireless.
- Configure any LUT to work as a single-port or dual-port 16-bit RAM/ROM.
- Cascade LUTs to build larger memories.
- Applications include flexible memory sizes, FIFOs, and buffers.
Embedded Block RAM
- 36 blocks of cascadable, synchronous 18 Kbit block RAM.
- Configure any 18 Kbit block as a single/dual-port RAM.
- Supports multiple aspect ratios, data-width conversion, and parity.
- Applications include data caches, deep FIFOs, and buffers.
- The maximum size of a block RAM is 648 kbits
Digital Clock Managers
The Digital Clock Managers (DCM) provides a number of clock management features:
- Clock deskew. The DCM contains a delayed-locked loop to completely eliminate clock distribution delays.
- Frequency Synthesis. Separate outputs provide a doubled frequency. Another output provides a frequency that is a specified fraction of the input.
- Phase shifting. The DCM allows coarse and fine-grained phase-shifting.
The XtremeDSP slices contain a dedicated 18x18-bits 2's complement signed multiplier, adder logic, and a 48 bit accumulator. Each multiplier and accumulator can be used independently. XC4VFX12 has 32 XtremeDSPs.
PowerPC Processor Block
The XC4VFX12 FPGA has one PowerPC™ 405, 32-bit RISC processor core. This industry standard processor offer high performance and a broad range of third-party support. The new Auxiliary Processor Unit (APU) controller simplifies the integration of hardware accelerators and co-processors.
(Courtesy of Xilinx)Ethernet MACThe XC4VFX12 FPGA has built-in Ethernet connectivity with two Ethernet media access controller (MAC) blocks. The Xilinx unique tri-mode Ethernet MAC provides guaranteed performance and UNH-verified interoperability. This integrated functionality reduces total system cost by reducing design and verification effort, freeing approximately 1,800 logic cells per Ethernet MAC in the FPGA fabric.Top Next Previous
The XC4VFX12FPGA device has 12,312 logic cells. We will use about 1200 logic cells for the design excluding the MicroBlaze soft processor core. The MicroBlaze will use between 800 to 2600 LUTs. For the block RAM we will use 64 kbits out of 648 kbits. There is plenty of room for future expansions.
More to read
If you want to know more about FPGA design look for a book at Amazon.com.
Here are some companies providing training for Xilinix users. There are many more.