New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Sunday, December 10, 2006
FPGA design from scratch. Part 10
It took longer than expected to finalize the verification phase but I think we can regain this lost time when we start debugging the real design. Hopefully we will not have that many bugs left in the design. We are now ready for the final synthesis runs.

Synthesis with timing constraints

Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL) or behavioral) is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

The synthesis is part of the
design closure process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives. A constraint is a design target that must be met in order for the design to be considered successful. For example, a chip may be required to run at a specific frequency in order to interface with other components in a system. Other constraints can be the power consumption and the chip size.

Designing an embedded system design in an FPGA that meets all timing requirements, starts already in the planing phase and continues throughout the whole project. Here are some important steps in achieving design closure.
  1. Understanding the differences between ASIC and FPGA
  2. System analysis and design partitioning
  3. RTL design for FPGA
  4. Synthesizing using the "right" timing constraints.
  5. Floor planing critical parts of the design
  6. Place and route and pin placement
Here is an article from Altera describing the differences between ASIC and FPGA design. From Altera you can also download the ASIC to FPGA Design Methodology & Guidelines.

In our design the only constraints we have are timing constraints for input and output signals. The design will operate at a maximum clock frequence of 54 MHz .This will be easily met in the Virtex-4 FPGA family.

We will use the Xilinx synthesis tool
XST because it is part of the Integrated Software Environment (ISE) and it is free. Here is an interesting article form FPGA Journal about "free" synthesis tools, how good are they. Other synthesis tools we could have used can be found in this table:

 Tool  Vendor
 Synplify Pro  Synplicity
 Precision  Mentor

Before we start the synthesis run, let's take a look in the 
XST User Guide
and the FAQ.

XST is a Xilinx tool that synthesizes HDL designs to create Xilinx specific netlist files called NGC files. The NGC file is a netlist that contains both logical design data and constraints that takes the place of both EDIF
and NCF (Netlist Constraints File) files. This manual describes XST support for Xilinx devices, HDL languages and design constraints. The manual also explains how to use various design optimization and coding techniques when creating designs for use with XST. We can choose to run XST from the command line or from inside the Project Navigator. Let's start the Project Navigator and follow these instructions.

=> ise &

After the synthesis the ISE project directory looks like this:

The synthesis report file

The Synthesis Report file is called <ETC.syr>, let's take a
look at it. We can see that the synthesis was successful, that the timing looks good and that the device utilization is about 10%. We could have used a smaller FPGA.
Timing Summary:
Speed Grade: -12

Minimum period: 5.839ns (Maximum Frequency: 171.250MHz)
Minimum input arrival time before clock: 5.433ns
Maximum output required time after clock: 6.491ns
Maximum combinational path delay: 8.409ns

Device utilization summary:


Selected Device : 4vfx12ff668-12

Number of Slices: 601 out of 5472 10%
Number of Slice Flip Flops: 570 out of 10944 5%
Number of 4 input LUT
s: 1113 out of 10944 10%
Number of IOs: 129
Number of bonded IOBs: 109 out of 320 34%
Number of GCLKs: 2 out of 32 6%

What else can we find out from the synthesis report file

The memory blocks are black boxed:

WARNING:Xst:2211 - "../../design/ETC_DUAL_PORT_1024x32.v" line 327:
Instantiating black box module <ETC_DUAL_PORT_1024x32>.

WARNING:Xst:2211 - "../../design/ETC_DUAL_PORT_1024x32.v" line 339:
Instantiating black box module <ETC_DUAL_PORT_1024x32>.

Black box instantiation

A black box is any instantiated component that is not represented by HDL code, but rather by another netlist format. Synthesis tools will generally report some kind of warning when a black box (this is, an instantiated component with no associated VHDL code) is detected.

Examples of black boxes include:
- CORE Generator modules (in our case)
- Instantiated EDIF files
- Instantiated primitives

If you are instantiating a component that is represented by something other than VHDL code, no response to the warning message is needed. If your intent was not to instantiate a black box, check your component declaration and instantiation to ensure that the component is properly represented by VHDL code.

To avoid "black box" warning messages, add the following lines to your HDL code:


architecture <architecture_name>

attribute box_type : string;
attribute box_type of <component_name> : component is "black_box";



//synthesis attribute box_type <module_name> "black_box"

Unused register bits

Some registers have unused bits:
WARNING:Xst:646 - Signal <tdi_data_reg1<31:30>> is assigned but never used.
WARNING:Xst:646 - Signal <tdi_data_reg2<31:30>> is assigned but never used.
WARNING:Xst:646 - Signal <tdi_data_reg3<31:30>> is assigned but never used.
WARNING:Xst:646 - Signal <tdi_data_reg4<31:30>> is assigned but never used.
One-hot encoding not safe
INFO:Xst:2117 - HDL ADVISOR -Mux Selector <jtc_tck_source> of Case statement line 313 
was re-encoded using one-hot encoding.The case statement will be optimized
(default statement optimization),but this optimization may lead to design initialization problems.
To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <jtc_tck_source> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization

We will take a closer look at these warnings and info messages but before we do, we will generate a Post-Synthesis Simulation Model.

Post-synthesis simulation model

The Post-Synthesis Simulation Model will contain all the building blocks used in the FPGA, like LUTs, muxes and I/O buffers. It is functionally correct but it has no timing information and it should be simulated using the unisim library.
Double-click the <Generate Post-Synthesis Simulation Model> entry in the Processes window in the Project Navigator to start the generation.
The flat netlist file
will be found in the <ETC/netgen/synthesis> directory.
Before we can use it in our simulation we have to add the following instantiation <glbl   glbl();>  inside the module ETC.

We replace the ETC RTL design files with the ETC netlist file in our simulation setup and rerun our testcases and they all pass. The synthesis tool did its job.

Top  Next  Previous

Posted at 08:57 by svenand

March 15, 2011   03:01 PM PDT
hello sir,

i have a query regarding black box instantiation...when i integrate ise and edk, the instance for edk for the hdl is generated as below...

// Instantiate the module
(* BOX_TYPE = "user_black_box" *)
system instance_name (

but when i instantiate this in the top mosule the black box instantiation is giving some errors how do i instantiate this black box can u provide me the syntax????


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