New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



If you want to be updated on this weblog Enter your email here:



rss feed



 
Monday, December 11, 2006
FPGA design from scratch. Part 9
When we have a stable design it is time to start the regression testing. We have to put together a test suite containing all the testcases we would like to use for our functional simulation. When we run all these testcases we will produce a lot of test result log files. We need a system to handle the whole regression testing and the Mongoose Simulation Environment can help you.

Regression Testing in Mongoose

Mongoose uses test sequences written in the Mongoose
Script Language (MSL) to perform regression testing. A  test sequence is a collection of testcases that are executed in sequence. You can control when to start a new testcase and where to send it. It can run as a background job on your own host or it can be sent to a batch queue manager (LSF) and  run on a dedicated simulation host.
This flow diagram shows the process of generating a test sequence, running a test sequence, analyzing the result and display the result in a web browser and/or send an email or
SMS with a summary of all test results.



Here is an example of a test sequence file. You can mix unix commands and Mongoose script commands. Lines starting with UC: are a unix commands and lines starting with MC: are Mongoose commands. You can write this file by hand or you can use the Test Sequence Generator to automatically generate one from the testcases you selected.


//$$HEADER
/*************************************************************************/
// Module:        ETC_TEST
// Design:        ETC
// Written by:    Sven-Ake Andersson ZooCad Consulting
// Description:   Test sequence file used for regression runs 
/*************************************************************************/

UC:echo 'Start test sequence'
MC:DisplayTime
MC:ClearAllCounters
MC:ClearFileNameAddOns
MC:AddTestCountToFileName
MC:AddTagNameToFileName
MC:SaveTickerInfo
MC:StartTicker
MC:SetTestCounter 1
MC:SetTagName ETC
MC:SetReportFormatShort
MC:SelectLogFile On
MC:SetReleaseName today
// Start of test sequence
UC:echo 'Testcase running : AllInstructionsExternalExcl.tc'
1:AllInstructionsExternalExcl.tc
MC:WaitSeconds 20
MC:WaitForSimulationToFinish 100
UC:echo 'Testcase running : BypassExternalExcl.tc'
1:BypassExternalExcl.tc
MC:WaitSeconds 20
MC:WaitForSimulationToFinish 100
// Add more testcases here
// ..................
MC:GenerateErrorReport
MC:DisplayHtmlFile
// Stop routine

UC:echo 'End of test sequence'
MC:SendErrorCount
MC:SendSMS 0706420380
MC:SendEmail zoodesign@comhem.se
MC:DisplayTime
MC:EndOfTestSequence


This is the email and SMS message sender window.



After running our testcases we have all
simulation log files saved in the result/printout directory:



Let's use the Log File Analyzer/Test Report Generator to generate a condensed test report file.



The Test Report Generator will search all log files for important information and put it into the
report file. The two errors reported are from testcases testing a function not implemented and can be ignored. We are finally ready for implementing the design into the FPGA.

Here is the email sent from the Mongoose script:




Top
Next  Previous




Posted at 15:02 by svenand

 

Leave a Comment:

Name


Homepage (optional)


Comments




Previous Entry Home Next Entry