New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

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Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
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SSSK
Wild skating
Tour day
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A look at the equipment you need
Skate maintenance
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Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
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KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

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ChipHit
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Dilbert
d9 Tech Blog
EDA Cafe
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Eli's tech Blog
Embedded.com
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FPGA Blog
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FPGA developer
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Tuesday, December 12, 2006
FPGA design from scratch. Part 8

Before we start synthesizing the design, let's make sure we have a clean design that won't give us any problems. We will use the HDL Analysis and Lint (HAL) tool  from Cadence to check our design. There are other tools available like, Spyglass from Atrenta, Indigo RTL Analysis from Blue Perl Software and Leda from Synopsys. We will use HAL because it is an efficient tool and it is part of the Incisive HDL simulator toolbox.

Using HAL

The first thing we will do is to read the HAL user guide to find out more about the program.
To open the user guide execute the following command: xpdf /cadence_install_dir/doc/hal/hal.pdf &
I have problems using the Cadence documentation system cdsdoc. I much prefer to read the pdf files using a standard PDF viewer like xpdf. To read the HAL reference manual use the following command: xpdf /cadence_install_dir/doc/halref/halref.pdf &

Introduction

This text is taken from the HAL user guide: "Functional closure in the ever-shrinking design cycles is achievable only by catching issues as early and as rapidly as possible. Design verification engineers need detection of problems related to multiple phases of design cycle, while the design is still under development at the RTL level. Such early warnings are a key to avoiding the expensive design iterations, and meeting quality and time-to-market goals. HAL checks the design for:
  • Design consistency, reusability and portability
  • Semantic correctness
  • Synthesizability
  • Testability and more"
Beautiful words let's see how good it is in reality. The flow diagram shows the two ways you can use HAL. The snapshot-based flow and the source file-based flow. We will use the snapshot-based flow.


Here is the complete HAL flow:
  1. Compile the design blocks into a library (design)
  2. Elaborate the design and save the result in a snapshot file (ETC_snapshot)
  3. Start hal using the following command: hal  design.ETC_snapshot
  4. HAL will execute and the result will be stored in a log file: hal.log
  5. To analyze the result start ncbrowse using the following command: ncbrowse -sortby severity -sortby category -sortby tag hal.log
We can use Mongoose (see Zoo Design Platform) to run the HDL analysis using HAL. But before we do let's save the current setup using the Load/Save Setup window.



We will save the current setup in the file ETC_simulation.setup and then create a new setup called ETC_analysis.setup to be used during the HAL runs. When we want to return to the simulation setup we will load ETC_simulation.setup and everything in Mongoose will be restored. This way we can handle a new task in Mongoose without interfering with other tasks.

This time we will only elaborate the design files and exclude the testbench. Let's change the top entity to ETC and give a name to the snapshot file : ETC_snapshot.



Select IUS/Elaboration from the Tool menu and start the elaboration:

ncelab: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
    Elaborating the design hierarchy:
        Caching library 'design' ....... Done
        Caching library 'std' ....... Done
        Caching library 'synopsys' ....... Done
        Caching library 'ieee' ....... Done
        Caching library 'ambit' ....... Done
        Caching library 'vital_memory' ....... Done
        Caching library 'ncutils' ....... Done
        Caching library 'ncinternal' ....... Done
        Caching library 'ncmodels' ....... Done
        Caching library 'cds_assertions' ....... Done
        Caching library 'sdilib' ....... Done
        Caching library 'macrolib' ....... Done
    Building instance overlay tables: .................... Done
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                         Instances  Unique
        Modules:                10       8
        Registers:             340     211
        Scalar wires:          154       -
        Vectored wires:         33       -
        Always blocks:          94      60
        Initial blocks:          6       3
        Cont. assignments:      63      71
        Timing checks:          16       -
        Simulation timescale:  1ps
    Writing initial simulation snapshot: design.ETC_snapshot:module


Select HAL from the Tool menu and start the HAL run.



hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options:   design.ETC_snapshot:module.
hal: Snapshot:  design.ETC_snapshot:module.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Sat Jan 13 00:16:31 CET 2007.

Performing lint checks
....................
Performing synthesizability checks
.
Analysis summary :

 Errors   : (2)
 METAEQ (2)    

 Warnings : (2082)
  BADSYS (24)     BITUSD (6)      CDEFCV (7)      CNSTLT (152)  
  CONSTC (44)     CTLCHR (404)    DIRRNG (9)      FNAVPC (5)    
  IGNDLY (4)      IMPTYP (91)     INIMEM (5)      INPASN (2)    
  INTTOB (16)     LCVARN (206)    LEXPGM (1)      MAXLEN (193)  
  MEMSIZ (2)      METACO (2)      MPCMPE (9)      MULOPR (16)   
  NEQPRM (33)     NESTIF (1)      NETDCL (20)     NOBLKN (49)   
  NOSPEC (1)      NOTECH (1)      OBMEMI (8)      POIASG (60)   
  PRMNAM (1)      PRMSZM (6)      SEPLIN (274)    STYVAL (110)  
  SYNTXZ (26)     UCCONN (150)    UELASG (34)     UELOPR (24)   
  ULRELE (33)     UNCONN (13)     URAREG (19)     URDPRT (1)    
  URDWIR (4)      USEFTN (3)      USEPAR (10)     VERREP (3)    

 Notes    : (90)
  ALOWID (11)     DECLIN (4)      IDLENG (75)   

Analysis failed.


Oophs! 2 errors and 2082 warnings. That's a lot of errors and warnings. Let's open the NCBrowse tool to analyze what is going on. Use the command: ncbrowse -sortby severity -sortby category -sortby tag hal.log &. Why not add this command to a user defined button. See previous chapter for a description.



A look at the log file reveals that the Xilinx memory is a behavioral verilog model that generates the two errors and many of the warnings we see. We have to exclude the memory from the analysis by adding this code in the design_info file (see HAL User Guide):

bb_list

  {
     designunit = ETC_DUAL_PORT_1024x32;
     file = /home/svenand/root/projects/ETC/design/ETC_DUAL_PORT_1024x32.v;
    
  }
 
This code will blackbox the memory and everything inside the memory block. When we rerun hal with the design_info file included we get the following result:

hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options:   -cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds.lib -logfile /home/svenand/root/projects/ETC/verification/hal/log/hal.log -File hal/script/etc_hal.script.
hal: Snapshot:  design.ETC_snapshot.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Sun Jan 14 00:42:26 CET 2007.

Performing lint checks
...........
Performing synthesizability checks
.
Analysis summary :

 Warnings : (821)
  BITUSD (6)      CDEFCV (7)      CNSTLT (36)     CTLCHR (77)   
  DIRRNG (8)      IMPTYP (25)     LCVARN (182)    MAXLEN (103)  
  MPCMPE (1)      NESTIF (1)      NETDCL (20)     NOBLKN (12)   
  POIASG (25)     SEPLIN (127)    STYVAL (97)     UCCONN (93)   
  URDPRT (1)    

 Notes    : (73)
  ALOWID (11)     IDLENG (62)   

Analysis failed.


We have go through the remaining warnings and see which ones can be ignored and which ones we have to investigate further.

 Warning  Description  Comment  Ignored
 BITUSD Unused bits inside a always block
  No
 CDEFCV Redundant default clause used
  No
 CNSTLT Literal '3'b1' should be replaced with a constant
  Yes
 CTLCHR Control characters in the source code found (tabs)
  Yes
 DIRRNG Inconsistent ordering of bits [0:31]
 OPB bus swapped
Yes
 IMPTYP Implicit type conversion
  No
 LCVARN Uppercase characters used for names
 I prefer upper case
Yes
 MAXLEN  Lines too long (more than 80 charcters)
  Yes
 MPCMPE Complex expressions, should add parentheses
  No
 NESTIF A nested if, in which the same variable is used in if comparisons, has been detected
  No
 NETDCL Declarations made prior to non-declarative statements
I will move the parameter statements
No
 NOBLKN  Always blocks not labeled
  Yes
 POIASG Overflow not verified
Counters will always wrap-around
Yes
 SEPLIN Use a separate line for each HDL statement
  Yes
 STYVAL Numeric value used for identifier
  Yes
 UCCONN Lowercase characters used for identifier
  Yes
 URDPRT Unconnected port
  No

HAL setup window:




After disabling the warnings we decided to ignore, here is the final result. I will take a closer look at these warnings and make the changes needed to get the design to pass HDL analysis.
We are then ready for the final synthesis run.


hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options:   -cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds.lib -logfile /home/svenand/root/projects/ETC/verification/analysis/log/hal.log -File /home/svenand/root/projects/ETC/verification/analysis/script/etc_hal.script.
hal: Snapshot:  design.ETC_snapshot.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Mon Jan 15 10:06:44 CET 2007.

Performing lint checks
...
Performing synthesizability checks
.
Analysis summary :

 Warnings : (61)
  BITUSD (6)      CDEFCV (7)      IMPTYP (25)     MPCMPE (1)    
  NESTIF (1)      NETDCL (20)     URDPRT (1)    

 Notes    : (73)
  ALOWID (11)     IDLENG (62)   

Analysis failed.

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Posted at 14:52 by svenand

Name
November 6, 2011   01:12 AM PDT
 
excellent website. It is very informative. Thank you.
 

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