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Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
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and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

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New Horizons
What's new
Starting a blog
Writing a blog
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Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
Evaluation kits and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
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Installing Cobra Command Tool
A processor benchmark
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Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
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100 Power Tips for FPGA Designers

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Tuesday, December 12, 2006
FPGA design from scratch. Part 8

Before we start synthesizing the design, let's make sure we have a clean design that won't give us any problems. We will use the HDL Analysis and Lint (HAL) tool  from Cadence to check our design. There are other tools available like, Spyglass from Atrenta, Indigo RTL Analysis from Blue Perl Software and Leda from Synopsys. We will use HAL because it is an efficient tool and it is part of the Incisive HDL simulator toolbox.

Using HAL

The first thing we will do is to read the HAL user guide to find out more about the program.
To open the user guide execute the following command: xpdf /cadence_install_dir/doc/hal/hal.pdf &
I have problems using the Cadence documentation system cdsdoc. I much prefer to read the pdf files using a standard PDF viewer like xpdf. To read the HAL reference manual use the following command: xpdf /cadence_install_dir/doc/halref/halref.pdf &

Introduction

This text is taken from the HAL user guide: "Functional closure in the ever-shrinking design cycles is achievable only by catching issues as early and as rapidly as possible. Design verification engineers need detection of problems related to multiple phases of design cycle, while the design is still under development at the RTL level. Such early warnings are a key to avoiding the expensive design iterations, and meeting quality and time-to-market goals. HAL checks the design for:
  • Design consistency, reusability and portability
  • Semantic correctness
  • Synthesizability
  • Testability and more"
Beautiful words let's see how good it is in reality. The flow diagram shows the two ways you can use HAL. The snapshot-based flow and the source file-based flow. We will use the snapshot-based flow.


Here is the complete HAL flow:
  1. Compile the design blocks into a library (design)
  2. Elaborate the design and save the result in a snapshot file (ETC_snapshot)
  3. Start hal using the following command: hal  design.ETC_snapshot
  4. HAL will execute and the result will be stored in a log file: hal.log
  5. To analyze the result start ncbrowse using the following command: ncbrowse -sortby severity -sortby category -sortby tag hal.log
We can use Mongoose (see Zoo Design Platform) to run the HDL analysis using HAL. But before we do let's save the current setup using the Load/Save Setup window.



We will save the current setup in the file ETC_simulation.setup and then create a new setup called ETC_analysis.setup to be used during the HAL runs. When we want to return to the simulation setup we will load ETC_simulation.setup and everything in Mongoose will be restored. This way we can handle a new task in Mongoose without interfering with other tasks.

This time we will only elaborate the design files and exclude the testbench. Let's change the top entity to ETC and give a name to the snapshot file : ETC_snapshot.



Select IUS/Elaboration from the Tool menu and start the elaboration:

ncelab: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
    Elaborating the design hierarchy:
        Caching library 'design' ....... Done
        Caching library 'std' ....... Done
        Caching library 'synopsys' ....... Done
        Caching library 'ieee' ....... Done
        Caching library 'ambit' ....... Done
        Caching library 'vital_memory' ....... Done
        Caching library 'ncutils' ....... Done
        Caching library 'ncinternal' ....... Done
        Caching library 'ncmodels' ....... Done
        Caching library 'cds_assertions' ....... Done
        Caching library 'sdilib' ....... Done
        Caching library 'macrolib' ....... Done
    Building instance overlay tables: .................... Done
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                         Instances  Unique
        Modules:                10       8
        Registers:             340     211
        Scalar wires:          154       -
        Vectored wires:         33       -
        Always blocks:          94      60
        Initial blocks:          6       3
        Cont. assignments:      63      71
        Timing checks:          16       -
        Simulation timescale:  1ps
    Writing initial simulation snapshot: design.ETC_snapshot:module


Select HAL from the Tool menu and start the HAL run.



hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options:   design.ETC_snapshot:module.
hal: Snapshot:  design.ETC_snapshot:module.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Sat Jan 13 00:16:31 CET 2007.

Performing lint checks
....................
Performing synthesizability checks
.
Analysis summary :

 Errors   : (2)
 METAEQ (2)    

 Warnings : (2082)
  BADSYS (24)     BITUSD (6)      CDEFCV (7)      CNSTLT (152)  
  CONSTC (44)     CTLCHR (404)    DIRRNG (9)      FNAVPC (5)    
  IGNDLY (4)      IMPTYP (91)     INIMEM (5)      INPASN (2)    
  INTTOB (16)     LCVARN (206)    LEXPGM (1)      MAXLEN (193)  
  MEMSIZ (2)      METACO (2)      MPCMPE (9)      MULOPR (16)   
  NEQPRM (33)     NESTIF (1)      NETDCL (20)     NOBLKN (49)   
  NOSPEC (1)      NOTECH (1)      OBMEMI (8)      POIASG (60)   
  PRMNAM (1)      PRMSZM (6)      SEPLIN (274)    STYVAL (110)  
  SYNTXZ (26)     UCCONN (150)    UELASG (34)     UELOPR (24)   
  ULRELE (33)     UNCONN (13)     URAREG (19)     URDPRT (1)    
  URDWIR (4)      USEFTN (3)      USEPAR (10)     VERREP (3)    

 Notes    : (90)
  ALOWID (11)     DECLIN (4)      IDLENG (75)   

Analysis failed.


Oophs! 2 errors and 2082 warnings. That's a lot of errors and warnings. Let's open the NCBrowse tool to analyze what is going on. Use the command: ncbrowse -sortby severity -sortby category -sortby tag hal.log &. Why not add this command to a user defined button. See previous chapter for a description.



A look at the log file reveals that the Xilinx memory is a behavioral verilog model that generates the two errors and many of the warnings we see. We have to exclude the memory from the analysis by adding this code in the design_info file (see HAL User Guide):

bb_list

  {
     designunit = ETC_DUAL_PORT_1024x32;
     file = /home/svenand/root/projects/ETC/design/ETC_DUAL_PORT_1024x32.v;
    
  }
 
This code will blackbox the memory and everything inside the memory block. When we rerun hal with the design_info file included we get the following result:

hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options:   -cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds.lib -logfile /home/svenand/root/projects/ETC/verification/hal/log/hal.log -File hal/script/etc_hal.script.
hal: Snapshot:  design.ETC_snapshot.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Sun Jan 14 00:42:26 CET 2007.

Performing lint checks
...........
Performing synthesizability checks
.
Analysis summary :

 Warnings : (821)
  BITUSD (6)      CDEFCV (7)      CNSTLT (36)     CTLCHR (77)   
  DIRRNG (8)      IMPTYP (25)     LCVARN (182)    MAXLEN (103)  
  MPCMPE (1)      NESTIF (1)      NETDCL (20)     NOBLKN (12)   
  POIASG (25)     SEPLIN (127)    STYVAL (97)     UCCONN (93)   
  URDPRT (1)    

 Notes    : (73)
  ALOWID (11)     IDLENG (62)   

Analysis failed.


We have go through the remaining warnings and see which ones can be ignored and which ones we have to investigate further.

 Warning  Description  Comment  Ignored
 BITUSD Unused bits inside a always block
  No
 CDEFCV Redundant default clause used
  No
 CNSTLT Literal '3'b1' should be replaced with a constant
  Yes
 CTLCHR Control characters in the source code found (tabs)
  Yes
 DIRRNG Inconsistent ordering of bits [0:31]
 OPB bus swapped
Yes
 IMPTYP Implicit type conversion
  No
 LCVARN Uppercase characters used for names
 I prefer upper case
Yes
 MAXLEN  Lines too long (more than 80 charcters)
  Yes
 MPCMPE Complex expressions, should add parentheses
  No
 NESTIF A nested if, in which the same variable is used in if comparisons, has been detected
  No
 NETDCL Declarations made prior to non-declarative statements
I will move the parameter statements
No
 NOBLKN  Always blocks not labeled
  Yes
 POIASG Overflow not verified
Counters will always wrap-around
Yes
 SEPLIN Use a separate line for each HDL statement
  Yes
 STYVAL Numeric value used for identifier
  Yes
 UCCONN Lowercase characters used for identifier
  Yes
 URDPRT Unconnected port
  No

HAL setup window:




After disabling the warnings we decided to ignore, here is the final result. I will take a closer look at these warnings and make the changes needed to get the design to pass HDL analysis.
We are then ready for the final synthesis run.


hal: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
Incisive HDL analysis
hal: Options:   -cdslib /home/svenand/root/projects/ETC/verification/simSetup/ncsim/cds.lib -logfile /home/svenand/root/projects/ETC/verification/analysis/log/hal.log -File /home/svenand/root/projects/ETC/verification/analysis/script/etc_hal.script.
hal: Snapshot:  design.ETC_snapshot.
hal: Workspace: /home/svenand/root/projects/ETC/verification.
hal: Date: Mon Jan 15 10:06:44 CET 2007.

Performing lint checks
...
Performing synthesizability checks
.
Analysis summary :

 Warnings : (61)
  BITUSD (6)      CDEFCV (7)      IMPTYP (25)     MPCMPE (1)    
  NESTIF (1)      NETDCL (20)     URDPRT (1)    

 Notes    : (73)
  ALOWID (11)     IDLENG (62)   

Analysis failed.

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Posted at 14:52 by svenand

Name
November 6, 2011   01:12 AM PDT
 
excellent website. It is very informative. Thank you.
 

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