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Table of content

New Horizons
What's new
Starting a blog
Writing a blog
I got a job

SystemC
SystemC from scratch. Part 1
SystemC from scratch. Part 2
SystemC from scratch. Part 3

ASIC/FPGA Design
Table of content
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Links
Acronyms and abbreviations
XCell Journals
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Ubuntu Linux on a MacBook
Customizing Ubuntu Linux 1
Customizing Ubuntu Linux 2
Upgrading to Ubuntu 7.04
Install Ubuntu 7.04 with VMware
Making the virtual machine run faster
Ubuntu Links
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Wireless freedom
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts
Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state


Example Files
Verilog Testbench Body
Verilog Testcase
Verilog Setup
Simulation Result File
Simulation Report File




Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice


Favorites
Adventures in ASIC
ChipHit
Computer History Museum
Community of Sweden
DeepChip
Design & Reuse
Dilbert
EDA Cafe
EDA DesignLine
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA Journal
FPGA World
MacApper
Mac geekery
Mac 2 Ubuntu
Get Perpendicular
Programmable Logic DesignLine
History of Linux
OpenCores
ORSoC
Simplehelp
SOCcentral
World of ASIC



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Sep 7, 2006
Verilog Testcase

//$$HEADER
/*************************************************************************/
/*                                                                       */
/*                H E A D E R   I N F O R M A T I O N                    */
/*                                                                       */
/*************************************************************************/

// Module:        ETC_TEST
// Design:        ETC
// Written by:    Sven-Ake Andersson
// Description:   Testcase file for functional testing  


//$$UPDATE
/*************************************************************************/
/*                                                                       */
/*                U P D A T E   I N F O R M A T I O N                    */
/*                                                                       */
/*************************************************************************/

// Date        Version    Description
//------------------------------------------------------------------------
// 060322    1.0    First version
// 060719    1.1    New method for generating the testprogram
// 060823    1.11   Added expected data
// 060828    1.12   Modified for OPB interface


//$$CURRENT VERSION
/*************************************************************************/
/*                                                                       */
/*                   C U R R E N T   V E R S I O N                       */
/*                                                                       */
/*************************************************************************/

initial
 begin
    TestCaseIdentity  = 10'ha;      // Identifies the testcase
    TestCaseVersion   = 12'h112;    // Identifies the testcase version
 end
    
//$$TEST DESCRIPTION
/*************************************************************************/
/*                                                                       */
/*                 T E S T   D E S C R I P T I O N                       */
/*                                                                       */
/*************************************************************************/

// JTAG instruction tested : BYPASS
// Scan data through the bypass register and observe the TDO out data
// which will be one TCK clock cycle delayed.



//$$PARAMETERS
/*************************************************************************/
/*                                                                       */
/*                       P A R A M E T E R S                             */
/*                                                                       */
/*************************************************************************/

parameter   MAXIMUM_NUMBER_OF_TCK_CYCLES        =  24'd1000;


/*************************************************************************/
/*                                                                       */
/*                D E F I N E   T E S T   P R O G R A M                  */
/*                                                                       */
/*************************************************************************/


task CompileTestProgram;

begin

  SetLoadModuleIdentity(DesignIdentity,TestCaseIdentity,TestCaseVersion);
  SetTdoRecordingMode(SKIP_TDO_SHIFTIR);
  TestResetKeepingTrstzLow (10);
  LoadInstruction(INSTRUCTION_LENGTH,BYPASS);
  ReadWriteDataRegister(BypassRegLen+20,{{BypassRegLen{1'b0}},20'b1110011101});
  SetExpectedData(BypassRegLen+20,{20'b1110011101,{BypassRegLen{1'bx}}});
  EndOfTestProgram;


end

endtask



/*************************************************************************/
/*                                                                       */
/*                  S T A R T    T H E   S I M U L A T I O N             */
/*                                                                       */
/*************************************************************************/

initial
begin

/*************************************************************************/
/*                    D I S P L A Y   H E A D E R                        */
/*************************************************************************/

  HeaderDisplay(AllFiles);


/*************************************************************************/
/*                 C O M P I L E   T E S T  P R O G R A M                */
/*************************************************************************/

  CompileTestProgram;
  CompilationCheck;
  if (CompilationError) begin
     $fdisplay(AllFiles,"Errors found during compilation of test program");
     $fdisplay(AllFiles,"Simulation stopped ");
     $finish(2);
   end

  
/*************************************************************************/
/*                S A V E   L O A D   M O D U L E                        */
/*************************************************************************/

  SaveLoadModule;

/*************************************************************************/
/*               D I S P L A Y   T E S T  P R O G R A M                  */
/*************************************************************************/

  DisplayTestProgramRam(TestProgramSize);


/*************************************************************************/
/*                 S E T   I N P U T   C O N D I T I O N S               */
/*************************************************************************/

  SetAllInpinsLow;            // Define all other inputs
  CE1               = 1;      // Default value
  SetAllInpinsFixed;          // Define all fixed inputs 
  SetAllDiffInputsLow;        // Define all differential inputs
  ForceAllIopinsTristated;    // Force all iopins from outside with "z"

/*************************************************************************/
/*                         R E S E T   E T C                             */
/*************************************************************************/

  ResetSystem(10,5);


/*************************************************************************/
/*                   L O A D   T E S T  P R O G R A M                    */
/*************************************************************************/

   LoadTestProgram(TestProgramSize);


/*************************************************************************/
/*             W R I T E   C O N T R O L   R E G I S T E R               */
/*************************************************************************/

  WriteTransfer(ControlRegister,{ENABLE_INTERRUPT,DISABLE_LOOP_MODE,
                                 SKIP_TDO_SHIFTIR,DISABLE_SINGLE_STEP,
                                 ENABLE_TCK,CLOCK_RATE_DIV_BY_8,
                                 ExternalTestDBCexcl});

  TestClockCycles(10);
 

/*************************************************************************/
/*                    S T A R T   T H E   T E S T                        */
/*************************************************************************/

  WriteTransfer(ExecuteRegister,START_ETC); 

/*************************************************************************/
/*         W A I T   F O R  I N T E R R U P T  ( E N D  O F  T E S T )   */
/*************************************************************************/

  WaitForInterrupt(MAXIMUM_NUMBER_OF_TCK_CYCLES);
  TestClockCycles(20);


/*************************************************************************/
/*                    S T O P   T H E   T E S T                          */
/*************************************************************************/

  WriteTransfer(ExecuteRegister,STOP_ETC); 
  TestClockCycles(10);


/*************************************************************************/
/*                      D I S A B L E   T C K                            */
/*************************************************************************/

  WriteTransfer(ControlRegister,{DISABLE_TCK,CLOCK_RATE_DIV_BY_8,
                                 ExternalTestDBCexcl});

  SystemClockCycles(100);


/*************************************************************************/
/*        F I N D   N U M B E R   O F   T D O   B I T S  S T O R E D     */
/*************************************************************************/

  ReadStatusRegisterBits(BusyBit,PauseBit,FinishBit,LoadedTask,PauseShiftDr,
                         RecAddress,Reserved,TdoBitCount);


/*************************************************************************/
/*              T D O   D A T A   C O M P A R I S O N                    */
/*************************************************************************/

  TdoDataComparison(ExpectedDataSize); 



/*************************************************************************/
/*                 D I S P L A Y   T E S T   R E S U L T                 */
/*************************************************************************/

  ResultDisplay(AllFiles);


/*************************************************************************/
/*                F I N I S H   T H E   S I M U L A T I O N              */
/*************************************************************************/

  $finish(2);

end

endmodule

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
 
Posted at 10:40 am by svenand

 

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