//$$HEADER
/*************************************************************************/
/* */
/* H E A D E R I N F O R M A T I O N */
/* */
/*************************************************************************/
// Module: ETC_TEST
// Design: ETC
// Written by: Sven-Ake Andersson
// Description: Testbench body file for functional testing of the
// embedded test controller (ETC)
//$$UPDATE
/*************************************************************************/
/* */
/* U P D A T E I N F O R M A T I O N */
/* */
/*************************************************************************/
// Date Version Change
//------------------------------------------------------------------------
// 070102 1.0 First version
// 070108 1.1 Changed names of include setup files
//$$DESCRIPTION
/*************************************************************************/
/* */
/* T E S T B E N C H D E S C R I P T I O N */
/* */
/*************************************************************************/
//$$DEFINE
/*************************************************************************/
/* */
/* D E F I N E D I R E C T I V E S */
/* */
/*************************************************************************/
//$$TIMESCALE
/*************************************************************************/
/* */
/* T I M E S C A L E D I R E C T I V E */
/* */
/*************************************************************************/
`timescale 1ns / 10ps
//$$MODULE
/*************************************************************************/
/* */
/* M O D U L E S T A R T */
/* */
/*************************************************************************/
module ETC_TEST();
//$$VERSION
/*************************************************************************/
/* */
/* V E R S I O N D E F I N I T I O N S */
/* */
/*************************************************************************/
parameter TestbenchVersion = 1.1;
//$$PARAMETER
/*************************************************************************/
/* */
/* U S E R D E F I N E D P A R A M E T E R S */
/* */
/*************************************************************************/
parameter MaxNumberPins = 1000; // Defines array sizes
parameter MaxNumberOfTdiBits = 4095; // Maximum number of TDI/TDO data bits
// for one task
//$$TIMING
/*************************************************************************/
/* */
/* F U N C T I O N A L */
/* T I M I N G S E T U P */
/* */
/*************************************************************************/
parameter I_CLK_ClockStart = 0;
parameter I_CLK_ClockWidth = 10;
parameter I_CLK_ClockPeriod = 20;
//$$PROGRAM DEFINED
/*************************************************************************/
/* */
/* P R O G R A M D E F I N E D P A R A M E T E R S */
/* */
/*************************************************************************/
// Set maximum values for counters and memory sizes
parameter PROGRAM_SIZE_MAX = 1024; // Maximum size of testprogram ram
parameter WAIT_CYCLES_MAX = 67108863;
parameter TRTZ_LOW_CYCLES_MAX = 4095;
parameter TMS_HIGH_CYCLES_MAX = 4095;
parameter CLOCK_RATE_DIV_BY_4 = 3'b000;
parameter CLOCK_RATE_DIV_BY_8 = 3'b001;
parameter CLOCK_RATE_DIV_BY_16 = 3'b010;
parameter CLOCK_RATE_DIV_BY_32 = 3'b011;
parameter CLOCK_RATE_DIV_BY_64 = 3'b100;
parameter ENABLE_TCK = 1'b1;
parameter DISABLE_TCK = 1'b0;
parameter ENABLE_SINGLE_STEP = 1'b1;
parameter DISABLE_SINGLE_STEP = 1'b0;
parameter ENABLE_INTERRUPT = 1'b1;
parameter DISABLE_INTERRUPT = 1'b0;
parameter NO_SHIFT_DR = 12'b0;
parameter NO_SHIFT_IR = 12'b0;
parameter SAVE_ALL_TDO = 2'b00;
parameter SKIP_TDO_SHIFTIR = 2'b01;
parameter SKIP_TDO_SHIFTDR = 2'b10;
parameter SKIP_TDO_ALL = 2'b11;
parameter ENABLE_LOOP_MODE = 1'b1;
parameter DISABLE_LOOP_MODE = 1'b0;
parameter NOT_USED = 2'b0;
parameter STOP_ETC = 32'h0;
parameter START_ETC = 32'h1;
parameter RESET_ETC = 32'h8;
//$$ETC ADDRESSES USED
/*************************************************************************/
/* */
/* E T C A D D R E S S M A P */
/* */
/*************************************************************************/
parameter ControlRegister = 32'h00000200; // write
parameter StatusRegister = 32'h00000204; // read
parameter ExecuteRegister = 32'h00000208; // write
parameter DebugRegister = 32'h0000020c; // read
parameter TestProgramMemory = 32'h00000000; // write
parameter TestResultMemory = 32'h00000100; // read
//$$CONFIG REGISTER SETUP
/*************************************************************************/
/* */
/* C O N F I G R E G I S T E R S E T U P */
/* */
/*************************************************************************/
parameter BoardTest = 4'b0000; // Connect external JTAG tester
parameter InternalTest = 4'b0001; // ETC connects to JTC internally
parameter ExternalTestDBCincl = 4'b0010; // ETC connects externally to the board
parameter ExternalTestDBCexcl = 4'b0011; // ETC connects externally to the board
parameter SystemTestDBCincl = 4'b0100; // ETC connects externally to the system
parameter SystemTestDBCexcl = 4'b0101; // ETC connects externally to the system
//$$ETC INSTRUCTION CODES
/*************************************************************************/
/* */
/* M T C I N S T R U C T I O N C O D E S */
/* */
/*************************************************************************/
parameter NoOperationOpCode = 4'b0000;
parameter TestResetTrstzLowOpCode = 4'b0001;
parameter TestResetTmsHighOpCode = 4'b0010;
parameter LoadInstructionOpCode = 4'b0011;
parameter LoadDataOpCode = 4'b0100;
parameter LoadInstructionAndDataOpCode = 4'b0101;
parameter LoadDataAndInstructionOpCode = 4'b0110;
parameter LoadDataPauseOpCode = 4'b0111;
parameter LoadDataContinueOpCode = 4'b1000;
parameter LoadDataContinuePauseOpCode = 4'b1001;
parameter WaitInRunTestIdleOpCode = 4'b1010;
parameter PauseInRunTestIdleOpCode = 4'b1011;
parameter EndOfTestOpCode = 4'b1100;
//$$TAP CONTROLLER
/*************************************************************************/
/* */
/* T A P C O N T R O L L E R C O N S T A N T S */
/* */
/*************************************************************************/
parameter ASIC_IDCODE = 32'h14012049;
parameter BoundaryScanRegLen = 51;
parameter MbistEnableRegLen = 40;
parameter MbistResultRegLen = 1;
parameter IdentificationRegLen = 32;
parameter BypassRegLen = 1;
//$$TAP_STATES
/*************************************************************************/
/* */
/* T A P C O N T R O L L E R S T A T E S */
/* */
/*************************************************************************/
parameter TEST_LOGIC_RESET = 4'b1111; // F
parameter RUN_TEST_IDLE = 4'b0100; // 4
parameter SELECT_DR_SCAN = 4'b1100; // C
parameter SELECT_IR_SCAN = 4'b0111; // 7
parameter CAPTURE_IR = 4'b0110; // 6
parameter SHIFT_IR = 4'b1001; // 9
parameter EXIT1_IR = 4'b0010; // 2
parameter PAUSE_IR = 4'b0011; // 3
parameter EXIT2_IR = 4'b0000; // 0
parameter UPDATE_IR = 4'b0101; // 5
parameter CAPTURE_DR = 4'b1110; // E
parameter SHIFT_DR = 4'b0001; // 1
parameter EXIT1_DR = 4'b1010; // A
parameter PAUSE_DR = 4'b1011; // B
parameter EXIT2_DR = 4'b1000; // 8
parameter UPDATE_DR = 4'b1101; // D
//$$JTAG INSTRUCTION
/*************************************************************************/
/* */
/* J T A G I N S T R U C T I O N S */
/* */
/*************************************************************************/
// INSTRUCTION OPCODES
parameter INSTRUCTION_LENGTH = 4;
parameter EXTEST = 4'b0000;
parameter IDCODE = 4'b0010;
parameter SAMPLE = 4'b0011;
parameter CLAMP = 4'b0100;
parameter HIGHZ = 4'b0101;
parameter MBIST_ENABLE = 4'b0110;
parameter MBIST_RESULT = 4'b0111;
parameter FAULT_INJECT = 4'b1000;
parameter EXTEST_PULSE = 4'b1001;
parameter EXTEST_TRAIN = 4'b1010;
parameter BYPASS = 4'b1111;
//$$INTEGER DEFINITIONS
/*************************************************************************/
/* */
/* I N T E G E R D E F I N I T I O N S */
/* */
/*************************************************************************/
integer i,j,jj;
integer cycles;
integer Address;
integer TestProgramSize;
integer ExpectedDataSize;
integer LoadModuleSize;
integer HeaderSize;
integer ExpectedDataAddress;
integer ExpectedDataBit;
integer NumberOfTdoDataWords;
integer CompilationError; // Set when error found during compilation
integer ShiftDataLen;
integer ShiftInstructionLen;
integer DataLenAdjust;
integer DataFinished;
integer FuncErrors; // Number of functional errors
integer EndOfTestIncluded; // Set when EndOfTest task included
integer TckClockCount;
integer SystemClockCount;
//$$REAL DEFINITIONS
/*************************************************************************/
/* */
/* R E A L D E F I N I T I O N S */
/* */
/*************************************************************************/
//$$REGISTER DEFINITIONS
/*************************************************************************/
/* */
/* R E G I S T E R D E F I N I T I O N S */
/* */
/*************************************************************************/
// Setup register
reg [31:0] TestProgram [0:1023]; // Store test program for ETC test
reg [31:0] ExpectedData [0:1023]; // Store expected data from ETC test
reg [31:0] MaskData [0:1023]; // Store mask data from ETC test
reg [31:0] TdoSavedData; // Store data when reading result memory
reg [31:0] InstructionCode;
reg [31:0] TdiDataWord;
reg [29:0] TdiDataTemp;
reg [29:0] TdiDataFix;
//$$DEVICE PINS
/*************************************************************************/
/* */
/* D E V I C E P I N S */
/* */
/*************************************************************************/
// Found in setup include file
//$$PROGRAM REGISTERS
/*************************************************************************/
/* */
/* R E G I S T E R U S E D D U R I N G S I M U L A T I O N */
/* */
/*************************************************************************/
// These register declarations must not be changed
reg [MaxNumberPins:1] COMPARE_VALUE;
reg [MaxNumberPins:1] MASK_VALUE;
reg [MaxNumberPins:1] RESULT_VALUE;
// Log file pointers
reg [31:0] AllFiles;
reg [31:0] Report;
reg [31:0] LoadModule;
reg [8*30:1] TaskName; // Store executing task name
reg [ 9 : 0] DesignIdentity;
reg [ 9 : 0] TestCaseIdentity;
reg [11 : 0] TestCaseVersion;
reg [31 : 0] LoadModuleIdentity;
reg [31 : 0] TdoRecordingMode;
reg BusyBit;
reg PauseBit;
reg FinishBit;
reg [3:0] LoadedTask;
reg [2:0] ErrorCode;
reg PauseShiftDr;
reg [5:0] RecAddress;
reg [4:0] Reserved;
reg [15:0] TdoBitCount;
reg [15:0] ExpectedTdoBits; // Count expected TDO data bits during
// test program compilatio
reg TimeStamp;
//$$PROBES
/*************************************************************************/
/* */
/* P R O B E S I N T O T H E D E S I G N */
/* */
/*************************************************************************/
wire [3:0] tapstate = {
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y4 .D ,
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y3 .D ,
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y2 .D ,
ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/TAP_CONTROLLER/TCB_Y1 .D };
wire shiftdr = ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_SHIFTDR_STATE;
wire shiftir = ETC_TEST.ETC_TOP.ASIC_INSTANCE.JTAG_MODULE/JTAG_SHIFTIR ;
`ifdef INTERNAL_TEST
wire TCK = ETC_TEST.ETC_TOP.ETC_INSTANCE.JTC_TCK;
`endif
`ifdef EXTERNAL_TEST
wire TCK = ETC_TEST.ETC_TOP.ETC_INSTANCE.JTC_TCK;
`endif
`ifdef SYSTEM_TEST
wire TCK = ETC_TEST.ETC_TOP.ETC_INSTANCE.JTC_TCK;
`endif
`ifdef BOARD_TEST
wire TCK = ETC_TEST.ETC_DBC3_TOP.BOARD_TESTER.ETC_TCKO;
`endif
//$$INCLUDE FILES
/*************************************************************************/
/* */
/* I N C L U D E F I L E S */
/* */
/*************************************************************************/
`ifdef INTERNAL_TEST
`include "ETC_InternalTestbench.setup"
`endif
`ifdef EXTERNAL_TEST
`include "ETC_ExternalTestbench.setup"
`endif
`ifdef SYSTEM_TEST
`include "ETC_SystemTestbench.setup"
`endif
`ifdef BOARD_TEST
`include "ETC_BoardtestTestbench.setup"
`endif
`include "ETC_SystemTasks.v"
`ifdef BOARD_TEST
`include "ETC_BoardtestTasks.v"
`endif
//$$INITIALIZATION
/*************************************************************************/
/* */
/* I N I T I A L I Z A T I O N R O U T I N E S */
/* */
/*************************************************************************/
initial
begin
Address = 0;
ExpectedDataAddress = 0;
ExpectedDataSize = 0;
TestProgramSize = 0;
ExpectedDataBit = 0;
NumberOfTdoDataWords = 0;
CompilationError = 0;
FuncErrors = 0;
MASK_VALUE = 0;
COMPARE_VALUE = 0;
EndOfTestIncluded = 0;
TckClockCount = 0;
SystemClockCount = 0;
ExpectedTdoBits = 0;
TimeStamp = 1'b0;
LoadModuleIdentity = 32'h0;
TdoRecordingMode = 32'h0;
$timeformat(-9, 0, " ns",10); // 1ns precision
DesignIdentity = 9'h171; // Identifies the design
end
/*************************************************************************/
/* */
/* O P E N O U T P U T F I L E S */
/* */
/*************************************************************************/
initial
begin
`ifdef MONGOOSE_START
Report = $fopen({"result/",`TESTCASE_STRING,".res"});
if (Report == 0) $finish;
LoadModule = $fopen({"result/",`TESTCASE_STRING,".lm"});
if (LoadModule == 0) $finish;
`endif
AllFiles = (Report | 1);
end
//$$COUNT CLOCKS
/*************************************************************************/
/* */
/* C O U N T C L O C K S */
/* */
/*************************************************************************/
always
begin
@(posedge TCK) TckClockCount = TckClockCount + 1;
end
always
begin
@(posedge I_CLK) SystemClockCount = SystemClockCount + 1;
end
//$$TEST OUTPUT SIGNALS
/*************************************************************************/
/* */
/* T E S T O U T P U T S I G N A L S */
/* */
/*************************************************************************/
always
begin
@(posedge TCK) begin
`ifdef INTERNAL_TEST
if (ETC_ENB != 1'b0 && FuncErrors == 0) begin
$fdisplay(AllFiles,"ETC_ENB signal not equal 0");
FuncErrors = FuncErrors + 1; end
`endif
`ifdef BOARD_TEST
if (ETC_ENB != 1'b0 && FuncErrors == 0) begin
$fdisplay(AllFiles,"ETC_ENB signal not equal 0");
FuncErrors = FuncErrors + 1; end
`endif
end
end
//$$CLOCKS
/*************************************************************************/
/* */
/* G E N E R A T E C L O C K S */
/* */
/*************************************************************************/
// Generate system clock
always
begin
#I_CLK_ClockStart I_CLK = 1;
#I_CLK_ClockWidth I_CLK = 0;
#(I_CLK_ClockPeriod-I_CLK_ClockStart-I_CLK_ClockWidth);
end
//$$END OF FILE
/*************************************************************************/
/* */
/* E N D O F T E S T B E N C H B O D Y */
/* */
/*************************************************************************/
// Endmodule is found in testcase file
-------------------------------------------------------------------------------------------
Posted at 09:13 am by
svenand
