Yieppie! I got a 45 days evaluation license from Cadence. Time to start the simulator. But before we do let's take a look at the testbench.
Testbench design
A clean and well-structured testbench is probably the best investment you can do in an ASIC/FPGA design project. Before the verification phases is finished the testbench has been changed hundreds of times. A lot of time will be saved if you find everything quickly in the testbench. There are many ways to setup a verification testbench and it can be more or less complicated. It can include co-simulation with software using c or c++ code, it can include Specman or Vera code and it can be written in SystemVerilog or SystemC. In this example I will describe a typical Verilog testbench without any extras.
Here is a block diagram showing the Verilog testbench I use in this project. It consists of a Verilog testbench body and a Verilog testcase. The Verilog testbench body will include a number of support files during compilation, using the include statement. During compilation the body file and all the include files together with the testcase will will be compiled into one complete testbench. In a ASIC/FPGA project there can be several hundreds of testcases used. Not having to include the testbench body in every testcase will save a lot of disk space. Let's take a look at the different blocks.
Verilog Testbench Body
The body file contains all the common setup that are used by all testcases. This is what's in the body file:
Header information
Update and revision information
Testbench description
Timescale directive
Module definition
Version
Parameter definitions
Timing setup
Integer definitions
Register definitions
Probes into the design
Include statements to include external files
Initialization routine
Open output files
Common counters
Clock generation
Verilog Testcase
The testcase is made up of a number of simulation tasks that will perform different actions on the device under simulation (DUS). The testcase has the endmodule statement as the last line.
Task Files
I use tasks as much as possible. Tasks make the testcase easier to read and understand. When an error is found in a testcase you only have to fix one task instead of having to change all testcases. All tasks are collected in one or more task files.
Setup Files
The Embedded Test Controller can operate in 5 different modes. For every mode of operation there is a separate setup. These setups are stored in different files and the rigth setup file is included during compilation using an `ìfdef statement. The setup files are generated by the Topi Top Code Generator. Read more about Topi in Zoo Design Platform. Mongoose Setup
Mongoose supports this testbench setup in several ways. First you specify the testbench body file in the Design Specification window.
To specify where to look for include files you use the compile command -incdir. You can specify up to four include directories in the Verilog Simulation Setup window.
We put all our testbench files here:
Now when we have a better understanding of the testbench let's start the simulation. Start Mongoose and select Testcase (Verilog) from the Object menu.
Select one of the testcases and click the start button. Mongoose is setup to run a three step process, compiling, elaborating and simulating in one pass. You can choose to run compilation, elaboration and simulation as separate steps if you prefer.
Debugging the design
There are many ways to debug the design and the testbench. The best debugging tool I know about is the Simvision waveform viewer, which is included in the Incisive HDL simulator. When debugging the design, I enable the generation of a waveform dump, run the full simulation or as long as I need, then load the dump file into Simvision and start tracing the problem. To setup a waveform dump in Mongoose use the Waveform Dump window. The ### specification in the file name will automatically be replaced by the testcase name. You enable the generation of a dump file by setting the Dump flag to sst/wlf.
Debugging tips
For a huge design the dump file can be several gigabytes if not limited. There are several ways to limit the size of the dump file.
Set the scope depth to only dump down to a certain hierarchical level. Default is 0 (= all levels).
Only dump certain parts of the design by entering one or two scope names.
Set the dump file size to the maximum size you can handle.
Simulation result When the simulation has finished we open Simvision using the command: simvision <dump_file> The first window displayed is the Design Browser. Select the signals you would like to look at and click the Waveform display button.
Here is a waveform plot of the working design.
We will probably open simvision many times during the verification phase. Let's define a user button to open it.
Mongoose User Defined Buttons
Open the User Buttons window in the Setup menu. Choose a name for the first button (SImvision) and enter the command executed when clicking the button. We will define the following command: simvision $PLOT_FIILE &. <$PLOT_FILE> reference the latest dump file generated. Click the update button and the user defined button will appear in the terminal window. In the same way you can define three more buttons.
This is what the terminal window looks like.
We are done with the design
Congratulations! We have I working solution. We have run all the testcases and they pass. Now is time to figure out how to get this design into an FPGA. That is the subject of the next chapter in this story.
