New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

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You are welcome to contact me
and ask questions or make comments
about my blog.

View Sven Andersson's profile on LinkedIn

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New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Cobra Command Tool
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Wednesday, December 13, 2006
FPGA design from scratch. Part 7
Yieppie! I got a 45 days evaluation license from Cadence. Time to start the simulator. But before we do let's take a look at the testbench.

Testbench design

A clean and well-structured testbench is probably the best investment you can do in an ASIC/FPGA design project. Before the verification phases is finished the testbench has been changed hundreds of times. A lot of time will be saved if you find everything quickly in the testbench. There are many ways to setup a verification testbench and it can be more or less complicated. It can include co-simulation with software using
c or c++ code, it can include Specman or Vera code and it can be written in SystemVerilog or SystemC. In this example I will describe a typical Verilog testbench without any extras.





Here is a block diagram showing the Verilog testbench I use in this project. It consists of a
Verilog testbench body and a Verilog testcase. The Verilog testbench body will include a number of support files during compilation, using the include statement. During compilation the body file and all the include files together with the testcase will will be compiled into one complete testbench. In a ASIC/FPGA project there can be several hundreds of testcases used. Not having to include the testbench body in every testcase will save a lot of disk space.
Let's take a look at the different blocks.

Verilog Testbench Body

The body file contains all the common setup that are used by all testcases. This is what's in the body file:
  • Header information
  • Update and revision information
  • Testbench description
  • Timescale directive
  • Module definition
  • Version
  • Parameter definitions
  • Timing setup
  • Integer definitions
  • Register definitions
  • Probes into the design
  • Include statements to include external files
  • Initialization routine
  • Open output files
  • Common counters
  • Clock generation
Verilog Testcase

The testcase is made up of a number of simulation tasks that will perform different actions on the device under simulation (DUS). The testcase has the endmodule statement as the last line.

Task Files

I use tasks as much as possible. Tasks make the testcase easier to read and understand. When an error is found in a testcase you only have to fix one task instead of having to change all testcases. All tasks are collected in one or more task files.

Setup Files

The Embedded Test Controller can operate in 5 different modes. For every mode of operation there is a separate setup. These setups are stored in different files and the rigth setup file is included during compilation using an `fdef statement. The setup files are generated by the Topi Top Code Generator. Read more about Topi in
Zoo Design Platform.

Mongoose Setup

Mongoose supports this testbench setup in several ways. First you specify the testbench body file in the Design Specification window.



To specify where to look for include files you use the compile command -incdir. You can specify up to four include directories in the Verilog Simulation Setup window.



We put all our testbench files here:



Now when we have a better understanding of the testbench let's start the simulation. Start Mongoose and select Testcase (Verilog) from the Object menu.



Select one of the testcases and click the start button. Mongoose is setup to run a three step process, compiling, elaborating and simulating in one pass. You can choose to run compilation, elaboration and simulation as separate steps if you prefer.

Debugging the design

There are many ways to debug the design and the testbench. The best debugging tool I know about is the Simvision waveform viewer, which is included in the Incisive HDL simulator. When debugging the design, I enable the generation of a waveform dump, run the full simulation or as long as I need, then load the dump file into Simvision and start tracing the problem. To setup a waveform dump in Mongoose use the Waveform Dump window. The ### specification in the file name will automatically be replaced by the testcase name. You enable the generation of a dump file by setting the Dump flag to sst/wlf.




Debugging tips

For a huge design the dump file can be several gigabytes if not limited. There are several ways to limit the size of the dump file.
  • Set the scope depth to only dump down to a certain hierarchical level. Default is 0 (= all levels).
  • Only dump certain parts of the design by entering one or two scope names.
  • Set the dump file size to the maximum size you can handle.
Simulation result

When the simulation has finished we open Simvision using the command: simvision <dump_file> The first window displayed is the Design Browser. Select the signals you would like to look at and click the Waveform display button.



Here is a waveform plot of the working design.



We will probably open simvision many times during the verification phase. Let's define a user button to open it.

Mongoose User Defined Buttons

Open the User Buttons window in the Setup menu. Choose a name for the first button (SImvision) and enter the command executed when clicking the button. We will define the following command: simvision $PLOT_FIILE &. <$PLOT_FILE> reference the latest dump file generated. Click the update button and the user defined button will appear in the terminal window. In the same way you can define three more buttons.



This is what the terminal window looks like.




We are done with the design

Congratulations! We have I working solution. We have run all the testcases and they pass. Now is time to figure out how to get this design into an FPGA. That is the subject of the next chapter in this story.

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Posted at 07:41 by svenand

 

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