New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.

View Sven Andersson's profile on LinkedIn

Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Cobra Command Tool
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Thursday, December 14, 2006
FPGA design from scratch. Part 6
Now when we have the simulation environment in place it is time to start looking at the simulation process using the Cadence Incisive HDL simulator.

The simulation process

It was easier before when we were using Verilog-XL. Just write one input script file including all design files, all macro library files and all testbench files and start Verilog using that file. The simulation kicked-off and when it finished there was a logfile to read. When using the Incisive HDL simulator it is a little bit more complicated. The simulation process is now a three step process including the following steps:
  1. Compilation of all design files, macro library files and testbench files.
  2. Elaboration of the whole design and saving the result in a snapshot.
  3. Simulation of the snapshot.
In the compilation phase all source files will be compiled in to one or more libraries and stored as binary data. It is a good idea to use several libraries and compile the macro library files into one library, the design files into another library and the testbench into yet another library. In this way it is easy to modify the testbench without affecting the rest of the compiled data. In Mongoose we will use this scheme. All files are compiled as induvidual files and there is no control of interconnects between modules.

In the elaboration phase all the libraries are read and elaborated, which means that all depencies are checked. Missing modules, missing connection and unconnected inputs and outputs will be reported. During the elaboration a new database will be built containing the whole design and the testbench connected together. This database can be saved in a snapshot file or it will reside in the testbench library database.

In the simulation phase the snapshot file will be read and the simulation will start executing the simulation flow described in the testbench. Data will be written to a logfile and if enabled there will be a waveform file generated.

Here is a flow diagram showing the simulation process in Mongoose.


This is what the default Incisive HDL simulator setup looks like in Mongoose



The mapping of library names to physical file locations are done in the cds.lib file which must be referenced in the ncvlog compile script. When starting a compilation in Mongoose the mapping shown above will be written to the cds.lib file. The file will look like this:

softinclude $CDS_INST_DIR/tools/inca/files/cds.lib
define macrolib         /home/svenand/root/projects/ETC/verification/database/ncsim/macrolib
define design            /home/svenand/root/projects/ETC/verification/database/ncsim/design
define testbench      /home/svenand/root/projects/ETC/verification/database/ncsim/testbench

Before we can start compiling the source code we need to setup definition files containing all files we are going to compile. Let's start with the macro library files from Xilinx. If you browse through the Xilinx installation you will find the macro libraries here:



We will use the script generator built in to Mongoose to generate the definition files. The Unisims library (having unit delays) and the CoreLib library will be used for our functional simulations.



Now we are ready to compile the macro libraries. Select Macro Library Def from the Object menu. Select one of the definition files and click the start button (the Mongoose).



The compilation will run in the terminal window:




In the same way we compile the design files and the testbench files. The database directory will contain the following files after the compilation phase is finished. The design-info file is added by the Mongoose and includes information about the source files compiled. When Clearcase revision handling is used this file also includes the config spec.



Congratulations, we have all our source code compiled. Time to start elaboration. Just one more thing we have to do before we start, enter the name of the top module (the testbench). We do that in the NCSIM setup window. In our case it is ETC_TEST.



Select IUS/Elaboration and start the elaboration phase. This is what to output looks like:

/home/svenand/root/projects/ETC/verification/.mongoose-batch0
ncelab: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
    Elaborating the design hierarchy:
        Caching library 'testbench' ....... Done
        Caching library 'std' ....... Done
        Caching library 'synopsys' ....... Done
        Caching library 'ieee' ....... Done
        Caching library 'ambit' ....... Done
        Caching library 'vital_memory' ....... Done
        Caching library 'ncutils' ....... Done
        Caching library 'ncinternal' ....... Done
        Caching library 'ncmodels' ....... Done
        Caching library 'cds_assertions' ....... Done
        Caching library 'sdilib' ....... Done
        Caching library 'macrolib' ....... Done
        Caching library 'design' ....... Done
 
    Building instance overlay tables: .................... Done
    Loading native compiled code:     .................... Done
    Building instance specific data structures.
    Design hierarchy summary:
                                            Instances  Unique
        Modules:                        4348      87
        UDPs:                              2208       6
        Primitives:                     2710       9
        Timing outputs:           2220      35
        Registers:                     1014     462
        Scalar wires:                2995       -
        Vectored wires:               37       -
        Always blocks:                 98      64
        Initial blocks:                    10       7
        Cont. assignments:         50     194
        Pseudo assignments:       5       5
        Timing checks:            7984     811
        Simulation timescale:   1ps
    Writing initial simulation snapshot: testbench.ETC_TEST:module

We are ready to start the simulation. We only need a IUS license file from Cadence.

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Posted at 08:29 by svenand

 

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