Now when we have the simulation environment in place it is time to start looking at the simulation process using the Cadence Incisive HDL simulator.
The simulation process It was easier before when we were using Verilog-XL. Just write one input script file including all design files, all macro library files and all testbench files and start Verilog using that file. The simulation kicked-off and when it finished there was a logfile to read. When using the Incisive HDL simulator it is a little bit more complicated. The simulation process is now a three step process including the following steps:
Compilation of all design files, macro library files and testbench files.
Elaboration of the whole design and saving the result in a snapshot.
Simulation of the snapshot.
In the compilation phase all source files will be compiled in to one or more libraries and stored as binary data. It is a good idea to use several libraries and compile the macro library files into one library, the design files into another library and the testbench into yet another library. In this way it is easy to modify the testbench without affecting the rest of the compiled data. In Mongoose we will use this scheme. All files are compiled as induvidual files and there is no control of interconnects between modules.
In the elaboration phase all the libraries are read and elaborated, which means that all depencies are checked. Missing modules, missing connection and unconnected inputs and outputs will be reported. During the elaboration a new database will be built containing the whole design and the testbench connected together. This database can be saved in a snapshot file or it will reside in the testbench library database.
In the simulation phase the snapshot file will be read and the simulation will start executing the simulation flow described in the testbench. Data will be written to a logfile and if enabled there will be a waveform file generated.
Here is a flow diagram showing the simulation process in Mongoose.
This is what the default Incisive HDL simulator setup looks like in Mongoose
The mapping of library names to physical file locations are done in the cds.lib file which must be referenced in the ncvlog compile script. When starting a compilation in Mongoose the mapping shown above will be written to the cds.lib file. The file will look like this:
softinclude $CDS_INST_DIR/tools/inca/files/cds.lib define macrolib /home/svenand/root/projects/ETC/verification/database/ncsim/macrolib define design /home/svenand/root/projects/ETC/verification/database/ncsim/design define testbench /home/svenand/root/projects/ETC/verification/database/ncsim/testbench Before we can start compiling the source code we need to setup definition files containing all files we are going to compile. Let's start with the macro library files from Xilinx. If you browse through the Xilinx installation you will find the macro libraries here:
We will use the script generator built in to Mongoose to generate the definition files. The Unisims library (having unit delays) and the CoreLib library will be used for our functional simulations.
Now we are ready to compile the macro libraries. Select Macro Library Def from the Object menu. Select one of the definition files and click the start button (the Mongoose).
The compilation will run in the terminal window:
In the same way we compile the design files and the testbench files. The database directory will contain the following files after the compilation phase is finished. The design-info file is added by the Mongoose and includes information about the source files compiled. When Clearcase revision handling is used this file also includes the config spec.
Congratulations, we have all our source code compiled. Time to start elaboration. Just one more thing we have to do before we start, enter the name of the top module (the testbench). We do that in the NCSIM setup window. In our case it is ETC_TEST.
Select IUS/Elaboration and start the elaboration phase. This is what to output looks like:
