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We need to clarify which external package pins that should be used to connect the LEDS output from the PWM_controller in the PL to the physical LEDs on the PCB. In order to pick up all the signal names, the design needs to be synthesized before the I/O planning layout can be opened.
Synthesis is the process of transforming an RTL-specified design into a gate-level representation. Vivado Integrated Design Environment (IDE) synthesis is timing-driven and optimized for memory usage and performance. Support for SystemVerilog as well as mixed VHDL and Verilog languages is included. The tool supports Xilinx Design Constraints (XDC), which is based on the industry-standard Synopsys Design Constraints (SDC). For more information read the document: Vivado Design Suite User Guide Synthesis (UG901).
1. In the Flow Navigator pane, select Synthesis->Run Synthesis. This will take a few minutes to complete. Ignore and close any warnings.
If the synthesis runs without errors this window will pop up.
2. Select Open Synthesis Design and click OK. Here is the result after synthesis.
3. To start the pin placement change from Default Layout to I/O planning layout in the top toolbar.
4. Expand All Ports in the I/O Planning pane at the bottom. Scroll down and select bus LEDS.
5. To find out which pins are connected to the LEDs we can read the ZedBoard Hardware Guide. We find the information in chapter 2.7.2 User LEDs.
6. Change the I/O standard to LVCMOS33 (3.3V) and add the pin locations in the Site column.
7. Save the settings in a constraints file by clicking CTRL-S.
8. A pop-up window appears. Type the file name PL_pins and click OK.
9. Returning to Default Layout we can see the file in the Design Sources pane. This is what the file PL_pins.xdc looks like.
Here is what the Linux file structure looks like for the LED_Controller project.
The Vivado Design Suite offers a variety of design flows, and supports an array of design sources. However, to get to a bitstream that can be downloaded into an FPGA, the design must pass through implementation. This is a series of steps that takes the logical netlist and maps it into the physical array of the target Xilinx device.
The Vivado implementation process includes logical as well as physical transformations of the design, and consists of the following sub-processes:
Opt Design: Optimize the logical design to make it easier to fit into the target Xilinx FPGA.
Power Opt Design: Optionally optimize elements of the design to reduce power demands of the implemented FPGA.
Place Design: Place the design onto the target Xilinx device.
Phys Opt Design: Optionally optimize the timing of the design by replicating drivers of high-fanout nets to distribute the loads.
Route Design: Route the design onto the target Xilinx device.
Write Bitstream: Generate a bitstream for Xilinx device configuration.
Saving the constraint file caused the synthesis to go out-of-date.
1. To avoid re-running the synthesis we can force the design up-to-date by selecting the run in Design Runs tab, right click and select "Force Up-to-Date".
2. In the Flow Navigator pane, select Run Implementation. This will take a few minutes to complete.
3. If the implementation returns without errors this window pops up.
4. Let's open the implemented design and have a look at the result.
5. From the Flow Navigator we can look a number of reports.
6. Here is the utilization report. We can see that we use only a small fraction of the resources available.
7. In the Flow Navigator pane, select Generate Bitstream. This will take a few minutes to complete.
8. When the bitstream generation has finished this window pops up.
9. Click OK to view the result.
Export hardware for SDK
We now have a design that can be used to configure the ZedBoard. But first we have to export the design to Vivado SDK where we will write the c-program that will run in the ARM processing system. Before we start the export we have to make sure that:
The block diagram is displayed in Vivado. Expand system_wrapper in the Source panel and double-click system_i - system (system.bd) to open the Block Diagram.
SDK is not running
The implemented design is open (when exporting the bitstream)
10. To open the implemented design, click Open Implemented Design in the Flow Navigator.
11. In the Vivado top menu select: File->Export->Export Hardware for SDK
12. This time we will export the hardware design and include the bitstream. Click OK.
13. Click Yes to overwrite the old design. This completes the hardware design in lab 2. In the next session we will create a custom C application to interact with this new PL peripheral. Here is what was exported.
svenand July 19, 2014 04:46 PM PDT Hi Pedro,
Thanks for helping out. I'm having vacation and have no access to the ZedBoard.
Pedro July 16, 2014 01:18 PM PDT
Hello Nadine and Huse
You cant choose B14 because B14 is only for PS. You cannot connect B14 to PL in Microzed.
If you want you can connect an LED on the bottom of your board, just check the available pins on the PL part and then select it.
You might want to take a look at the board schematic and see witch pin suits you best.
If you have any other questions you can email me at: email@example.com
Nadine July 12, 2014 03:36 PM PDT
I'm getting the same kind of error for Microzed board:
llegal to place instance LED_OBUF_inst on site B14. The location site type does not match the instance type. Instance LED_OBUF_inst belongs to a shape with reference instance LED_OBUF_inst. Shape elements have relative placement respect to each other.The invalid location might results from a constraint on any of the instance in the shape.
Is it possible to prevent Vivado from placing fixed port in B14 location ?
Huse June 25, 2014 06:11 PM PDT
Do you think it is possible to adapt this to the microzed board? i have modified the code so there is only one led, and then tried to place it in B14 (where the microzed's LED is at. But i get the next error: " Illegal to place instance LEDS_OBUF_inst on site B14. The location site type does not match the instance type. Instance LEDS_OBUF_inst belongs to a shape with reference instance LEDS_OBUF_inst. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape."
Do you have any idea why this could be?