New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

If you want to be updated on this weblog Enter your email here:

rss feed

Wednesday, February 26, 2014
Zynq design from scratch. Part 17.
Create a new custom HDL module

Since we have added the AXI GPIO in the design we need to regenerate the HDL files that are required for synthesis, implementation, and simulation. Expand Design Sources and system_wrapper in the Source pane, righg-click system ( and select Generate Output Files.

We will copy the wrapper file because we are going to modify it later on.

We will copy and overwrite the old file.

Here is the new wrapper file showing the system instance. Leave the file open we will use it soon.

Create a pulse-width modulation module

Next we need to create a new HDL module that will control the LED brightness. We will use pulse-width modulation (PWM) technique. This module will need a free running counter and a comparator that determines the duty cycle of the output signal. Most LCD monitors refresh rate is 50-60 Hz. From the PS we output a 50 MHz clock. Dividing that clock by one million will give a 50 Hz refresh rate. The corresponding duty cycle will then control the brightness. If we don't have time to write this code ourselves we can download a Verilog HDL file called PWM_Controller.v

Add sources

After downloading PWM_Controller.v w ehave to add it to our design. In the Flow Navigator pane select Project Manager->Add Sources.

Select Add or Create Design Sources and click Next.

Find and select the PWM_Controller.v file and click OK.

Mark Copyt sources into project and click Finish.

The Verilog HDL file PWM_Controller.v has been added to the Design Sources.

Modifying the wrapper file

We will make the following changes to the system_wrapper.v file:

Remove unused outputs FCLK_CLK0 and led_dutycycle_tri_0. We don't have bring out these signals to output pins. We will remove them from the module header and the output declaration.

2. Add a LED 8 bit output in the module header and in the output declaration.

3. Add an instantiation of the PWM_Controller.v and connect all the signals.

Here is the modified system_wrapper.v file. Save the file by clicking CTRL-S

Top   Previous   Next

Posted at 15:50 by svenand


Leave a Comment:


Homepage (optional)


Previous Entry Home Next Entry