New Horizons









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My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
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learn more about this fantastic field.
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Zynq Design From Scratch
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

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Installing Cobra Command Tool
A processor benchmark

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Porting a Unix program to Mac OS X
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Saturday, February 15, 2014
Zynq design from scratch. Part 11.
Build the hardware platform and export to SDK

A basic ARM hardware platform is now configured. The configuration includes clock and DDR controller settings. It also enabled and maps a UART peripheral. Now we will build the hardware platform and export to the Software Development Kit (SDK) so that an application can be developed.


1. Since we have added an IP in the design we need to generate the HDL files that are required for implementation, simulation and synthesis. In this first design we only use PS and there is nothing designed in the PL but we still need to do this step in order to hook up the design to the top level. Expand <Design Sources> in the Sources pane, right click system(system.bd) and select <Generate Output Products>. This window pops-up. Click Generate to start the generation.







2. Even though the whole design is made in IP integrator we still need a top level HDL in order to  identify the top of the design. The only thing needed is a top level HDL wrapper that instantiates the Block Design and it can be created automatically by right-clicking system(system.bd) and selecting <Create HDL Wrapper).

3. Click OK to let Vivado generate the system_wrapper.v top-level module for the design.






4.
Notice that the embedded system (system.bd) is now a sub-module of system_wrapper.





5. We now have a design that can be used to configure the ZedBoard. But first we have to export the design to Vivado SDK where we will write the c-program that will run in the ARM processing system. In Vivado menu select File->Export->Export Hardware for SDK...





6. The Vivado design tool exports the Hardware Platform Specification for our design (system.xml) to SDK. In addition to system.xml, there are four more files exported to SDK. They are ps7_init.c, ps7_init.h, ps7_init.tcl, and ps7_init.html. The system.xml file opens by default when SDK launches. The address map of our system read from this file is shown in the SDK window.

The ps7_init.c and ps7_init.h files contain the initialization code for the Zynq processing system and initialization settings for DDR, clocks, plls and MIOs. SDK uses these settings when initializing the processing system so that the applications can be run on top of the processing system.





Here are some of the files generated during the hardware design session. No it is time to start writing some software. We will start with the simplest program called "Hello World".




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Posted at 09:41 by svenand

 

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