New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Friday, December 15, 2006
FPGA design from scratch. Part 5
I have decided to use the Cadence Incisive HDL simulator for my functional verification. I will setup my own simulation environment using a tool called Mongoose. Mongoose is a graphical user interface (GUI) program, designed  for setting up and running a simulation testbench. It can be used as an interactive tool or used for running regression testing in batch mode.
I started to develop the Mongoose program more than 10 years ago and have been using it in all my ASIC verification work. It can be setup to utilize any Verilog or VHDL simulator and it can also integrate
Specman for automatic generation of functional tests. In this chapter I will describe how to setup and use the Cadence Insisive HDL simulator in the Mongoose Simulation Environment. Read more about Mongoose in the Zoo Design Platform presentation.

Setting up the simulation environment

Before starting Mongoose we have create a working directory. The working directory is the directory from where we start all our simulations:
mkdir /home/svenand/root/projects/ETC/verification
We don't want to remember this long file name so we will define an environment variable instead:
/home/svenand/root/projects/ETC/verification (csh and tcsh)
Add this statement to your .cshrc file
ETC_VERIFICATION=/home/svenand/root/projects/ETC/verification (sh and bash)
Add this statement  to your .bashrc file
Go to the working directory: cd $ETC_VERIFICATION
and start the Mongoose program: mongoose &

Open the terminal window by clicking the button.

Next thing to do is to create the file structure needed to support all activities during the simulation phase. Select Create Environment from the Setup menu and fill in the information:
  • Design name : ETC
  • Environment Variable Name : ETC_VERIFICATION
  • Working Directory : $ETC_VERIFICATION
  • Language : Verilog
  • Simulator : NC-SIM (Incisive HDL Simulator)
  • Simulation Setup : Functional
  • Script File : $ETC_VERIFICATION/CreateEnvironment

Click the Setup Script button to generate and run the environment setup script. When finished click the Mongoose Setup button to save the whole Mongoose setup in the file .mongoose-setup stored in the working directory. The next time you start Mongoose the setup file will be read and your are back to where you were the last time.

Too see what the file structure looks like open the File Tree Browser and click the Set Root button to display the first level of files. Double-click on a directory to see the next level of files.

This table explains the usage of the different directories. This is only a recommendation, you can change almost everything if you like to.

 Directory  Description
 bookmark Stores the directory bookmark file
 command Stores saved commands
 database Stores the compiled simulation libraries
 debug Stores debug commands for interactive debugging
 design Stores the verilog or VHDL design files
 designDefine Stores design definition files (behaviour, RTL, netlist)
 help Stores help information
 input Stores TCL input files to the simulator
 key Stores the key file from the simulation
Stores macro library definition files
Stores log files
Stores the macro library files
Stores all the script files generated from Mongoose
Stores Simvision waveform viewer plot files
Stores different result files from the simulation
Stores auxilary script files
Stores sdf setup files
Stores Mongoose setup files
Stores simulator setup files (cds.lib, hdl.var)
Stores Verilog task files
Stores Verilog testbench file
Stores Verilog testcase files

To display the current directories setup open Setup->Environment.

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Posted at 07:42 by svenand


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