My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company
You are welcome to contact me
and ask questions or make comments
about my blog.
When I start a GUI program for the first time this is the feeling I get.
The same thing with Vivado, I have no idea which buttons to push or which handles to pull. For that reason Xilinx together with Avnet have developed a number one-day training classes called "Xilinx SpeedWay Design Workshops".
Xilinx SpeedWay Design Workshops
Avnet Electronics Marketing introduces a new global series of Xilinx® SpeedWay Design Workshops™ for designers of electronic applications based on the Xilinx Zynq®-7000 All Programmable (AP) SoC Architecture. Taught by Avnet technical experts, these single day workshops combine informative presentations with hands-on labs supported by the ZedBoard™ and MicroZed™ development platforms. The training is recommended equally for engineers who want to gain hands-on experience with the tools and techniques that can be used to implement the Zynq-7000 AP SoC family.
Here are some other tutorials you may want to study:
The Vivado® Design Suite offers multiple ways to accomplish the tasks involved in Xilinx® FPGA design and verification. In addition to the traditional register transfer level (RTL)-to-bitstream FPGA design flow, the Vivado Design Suite provides new system-level integration flows that focus on intellectual property (IP)-centric design. Various IP can be instantiated, configured, and interactively connected into IP subsystem block designs within the Vivado IP integrator environment. Custom IP and IP block designs can be configured and packaged and made available from the Vivado IP catalog. Design analysis and verification is enabled at each stage of the flow. Design analysis features include logic simulation, I/O and clock planning, power an alysis, constraint definition and timing analysis, design rule checks (DRC), visualization of design logic, analysis and modification of implementation results, and programming and debugging.
The entire solution is integrated within a graphical user interface (GUI) known as the Vivado Integrated Design Environment (IDE). The Vivado IDE provides an interface to assemble, implement, and validate the design and the IP. In addition, all flows can be run using Tcl commands. Tcl commands can be scripted or entered interactively using the Vivado Design Suite Tcl shell or using the Tcl Console in the Vivado IDE. You can use Tcl scripts to run the entire design flow, including design analysis, or to run only parts of the flow.
For more information read the document: Vivado Design User Guide: Design Flows Overview (UG892).
Getting a head start
In December 2013 I attended a SpeedWay Design Workshop here in Stockholm held by Avnet. The workshop was called "Introduction to Zynq" and took us through a complete Zynq-7000 design including software development, using the ZedBoard. For all of you who don't have the possibility to go to one of these workshops here is your chance to get the same information from my blog. Let's get started!