New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Thursday, February 13, 2014
Zynq design from scratch. Part 9.
Using Vivado

When I start a GUI program for the first time this is the feeling I get.


The same thing with Vivado, I have no idea which buttons to push or which handles to pull. For that reason Xilinx together with Avnet have developed a number one-day training classes  called "Xilinx SpeedWay Design Workshops".

Xilinx SpeedWay Design Workshops




Avnet Electronics Marketing introduces a new global series of Xilinx® SpeedWay Design Workshops™ for designers of electronic applications based on the Xilinx Zynq®-7000 All Programmable (AP) SoC Architecture. Taught by Avnet technical experts, these single day workshops combine informative presentations with hands-on labs supported by the ZedBoard™ and MicroZed™ development platforms. The training is recommended equally for engineers who want to gain hands-on experience with the tools and techniques that can be used to implement the Zynq-7000 AP SoC family.

Other tutorials

Here are some other tutorials you may want to study:

Training


Introduction

The Vivado® Design Suite offers multiple ways to accomplish the tasks involved in Xilinx® FPGA design and verification. In addition to the traditional register transfer level (RTL)-to-bitstream FPGA design flow, the Vivado Design Suite provides new system-level integration flows that focus on intellectual property (IP)-centric design. Various IP can be instantiated, configured, and interactively connected into IP subsystem block designs within the Vivado IP integrator environment. Custom IP and IP block designs can be configured and packaged and made available from the Vivado IP catalog. Design analysis and verification is enabled at each stage of the flow. Design analysis features include logic simulation, I/O and clock planning, power an alysis, constraint definition and timing analysis, design rule checks (DRC), visualization of design logic, analysis and modification of implementation results, and programming and debugging.

The entire solution is integrated within a graphical user interface (GUI) known as the Vivado Integrated Design Environment (IDE). The Vivado IDE provides an interface to assemble, implement, and validate the design and the IP. In addition, all flows can be run using Tcl commands. Tcl commands can be scripted or entered interactively using the Vivado Design Suite Tcl shell or using the Tcl Console in the Vivado IDE. You can use Tcl scripts to run the entire design flow, including design analysis, or to run only parts of the flow.


Design flow




For more information read the document: 
Vivado Design User Guide: Design Flows Overview (UG892).


Getting a head start

In December 2013 I attended a SpeedWay Design Workshop here in Stockholm held by Avnet. The workshop was called  "Introduction to Zynq" and took us through a complete Zynq-7000 design including software development, using the ZedBoard. For all of you who don't have the possibility to go to one of these workshops here is your chance to get the same information from my blog. Let's get started!

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Posted at 11:11 by svenand

 

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