New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2
Using Vivado 2014.2
Upgrading to Ubuntu 14.04
Using Petalinux 2014.2
Booting from SD card and SPI flash
Booting Petalinux 2014.2 from SD card
Booting Petalinux 2014.2 from SPI flash

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Saturday, December 16, 2006
FPGA design from scratch. Part 4
Add existing code.

In the processes window double-click the Add Existing Source process. In the file browser window find the design directory and mark all files you would like to include. Repeat until all files have been added.

Check syntax

Mark the top file in the source window. In the process window expand the process Synthesis -XST.  Double-click the Check Syntax process to start the syntax check. The result will be displayed in the console window. Correct all syntax errors and when finished continue to the next step.

Generating memory blocks

In our design we need two memories. One memory to store the test program and one memory to record the test result. The memories must be dual-port memories and their size should be 1024x32. We use the same model for both memories. We will use the
Xilinx Core Generator program to generate the memory model. Let's start the program: coregen &

Click the Create new project link and follow the instructions. Don't forget to select VHDL or Verilog in the Project Options window. In the function window, open Memories and Storage->Dual Port Block. Click Customize. Specify all the options you need and click Generate to start the memory block generation. When finished there will be a number of files stored in the destination directory. See File Tree Browser display.

The file <etc_dual_port_1024x32_readme.txt> explains the usage of the different files.

 File Name
 File Usage
etc_dual_port_1024x32.edn  Electronic Data Netlist (EDN) file containing the information required to implement the module in a Xilinx FPGA.
 etc_dual_port_1024x32.v Verilog wrapper file provided to suppport functional simulation.
 etc_dual_port_1024x32.veo VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design.
 etc_dual_port_1024x32.xco CORE Generator input file containing the parameters used to regenerate a core.

We will use the file <etc_dual_port_1024x32.v> in our functional simulations. When we synthesize the design this file will be black boxed. The EDN file <etc_dual_port_1024x32.edn> will be used during the build process to generate the final FPGA design.

Synthesizing the design

Now when the whole design is completed I will do a quick
synthesis run to find out if there are any design errors left. I will use the Xilinx synthesis tool XST.
  1. Select the top module in the source window
  2. Double click the Synthesize - XST tab in the process window.
  3. Wait for the synthesis to finish.
  4. Read the errors and warnings in the console window
  5. Fix the errors and rerun the synthesis.
  6. When it runs clean you can find out the device utilization from project status report.
  7. To see the synthesized netlist double-click View RTL Schematic (see screenshot).

Simulating the design

To verify that the design is functionally correct we will use
functional verification by the means of logic simulation.  The following standards are supported in the Xilinx simulation flow:

 Description  Version
 VHDL Language  IEEE-STD-1076-1993
 VITAL Modeling Standard
 Verilog Language  IEEE-STD-1364-2001
 Standard Delay Format  OVI 3.0
 Std_logic Data Type

Xilinx supports the following simulators:

 Simulator  OSCost
Xilinx ISE Simulator LiteWindows
Xilinx ISE Simulator WindowsLow
Mentor ModelSim XE-III Starter WindowsFree
Mentor ModelSim XE-IIIWindows
Mentor ModelSim PE (Personal Edition)
Mentor ModelSim LE (Linux Edition)
Mentor ModelSim SE (Special Edition)
Windows, Linux, Unix
Cadence Incisive HDL Simulator
Windows, Linux, Unix
Synopsys VCS-MX Linux,Unix

The limits for the ISE Simulator Lite are similar to the MXE-III Starter, 10,000 lines of debuggable code. Beyond this limit, the processing begins to slow down, but does not stop. The usefulness of this software is going to depend on coding style and type of simulation (either functional or timing) that is desired.

From this table you can see that there are no free simulators for Linux. It seems I have to go back to Windows or I will ask Cadence for a new evaluation license.

Here is the Xilinx simulation flow. Xilinx supports functional and timing simulations of HDL designs at five points in the HDL design flow:
  • Register Transfer Level (RTL)
  • Post-Synthesis (Pre-NGDBuild) Gate-Level
  • Post-HGDBuild (Pre-Map) Gate-Level
  • Post-Map Partial Timing (Block Delays)
  • Timing Simulations Post-Place and Route

                                                                                                   (Courtesy of Xilinx)

Next  Previous

Posted at 17:02 by svenand

September 20, 2011   07:57 AM PDT
I am part retired and had to pick up and fix a design. I found the Xilinx documentation extensive but missing basic checklists to get started. Examples:
How to provide a clock input to test
Undefined outputs probably mean undefined inputs
Minimum sources to build a circuit and get a program file out
Minimum sources to run Isim
If this check this and this etc
September 19, 2007   10:45 PM PDT
You have to ask Cadence for an evaluation license.

September 18, 2007   08:31 PM PDT
From where can we get an evaluation copy of Cadence Incisive HDL Simulator?
September 4, 2007   10:38 PM PDT
Yes. All the Zoo programs will be downloadable from my company web page: soon to be released.

Chuck Benz
September 4, 2007   06:02 PM PDT
1. I've had some success simulating Xilinx FPGA projects in the icarus free verilog simulator, including a microBlaze system. Icarus doesn't support smartmodels and the PPC core, of course. There's some info on my web page.

2. Are you releasing any of your Zoo tools, open source or otherwise? Forgive me if I missed links somewhere, but I didn't see any in my quick read.

3. On nice development board I like to endorse is Enterapoint's Raggedstone (and also their MiniCAN) - fairly cheap PCI Spartan3 boards.


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