My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company
You are welcome to contact me
and ask questions or make comments
about my blog.
Add existing code. In the processes window double-click the Add Existing Source process. In the file browser window find the design directory and mark all files you would like to include. Repeat until all files have been added.
Mark the top file in the source window. In the process window expand the process Synthesis -XST. Double-click the Check Syntax process to start the syntax check. The result will be displayed in the console window. Correct all syntax errors and when finished continue to the next step.
Generating memory blocks
In our design we need two memories. One memory to store the test program and one memory to record the test result. The memories must be dual-port memories and their size should be 1024x32. We use the same model for both memories. We will use the Xilinx Core Generator program to generate the memory model. Let's start the program: coregen &
Click the Create new project link and follow the instructions. Don't forget to select VHDL or Verilog in the Project Options window. In the function window, open Memories and Storage->Dual Port Block. Click Customize. Specify all the options you need and click Generate to start the memory block generation. When finished there will be a number of files stored in the destination directory. See File Tree Browser display.
The file <etc_dual_port_1024x32_readme.txt> explains the usage of the different files.
Electronic Data Netlist (EDN) file containing the information required to implement the module in a Xilinx FPGA.
Verilog wrapper file provided to suppport functional simulation.
VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design.
CORE Generator input file containing the parameters used to regenerate a core.
We will use the file <etc_dual_port_1024x32.v> in our functional simulations. When we synthesize the design this file will be black boxed. The EDN file <etc_dual_port_1024x32.edn> will be used during the build process to generate the final FPGA design. Synthesizing the design
Now when the whole design is completed I will do a quick synthesis run to find out if there are any design errors left. I will use the Xilinx synthesis tool XST.
Select the top module in the source window
Double click the Synthesize - XST tab in the process window.
Wait for the synthesis to finish.
Read the errors and warnings in the console window
Fix the errors and rerun the synthesis.
When it runs clean you can find out the device utilization from project status report.
To see the synthesized netlist double-click View RTL Schematic (see screenshot).
The limits for the ISE Simulator Lite are similar to the MXE-III Starter, 10,000 lines of debuggable code. Beyond this limit, the processing begins to slow down, but does not stop. The usefulness of this software is going to depend on coding style and type of simulation (either functional or timing) that is desired. From this table you can see that there are no free simulators for Linux. It seems I have to go back to Windows or I will ask Cadence for a new evaluation license.
Here is the Xilinx simulation flow. Xilinx supports functional and timing simulations of HDL designs at five points in the HDL design flow:
I am part retired and had to pick up and fix a design. I found the Xilinx documentation extensive but missing basic checklists to get started. Examples:
How to provide a clock input to test
Undefined outputs probably mean undefined inputs
Minimum sources to build a circuit and get a program file out
Minimum sources to run Isim
If this check this and this etc
svenand September 19, 2007 10:45 PM PDT You have to ask Cadence for an evaluation license.
primepie September 18, 2007 08:31 PM PDT
From where can we get an evaluation copy of Cadence Incisive HDL Simulator?
svenand September 4, 2007 10:38 PM PDT Yes. All the Zoo programs will be downloadable from my company web page: www.zoocad.com soon to be released.
1. I've had some success simulating Xilinx FPGA projects in the icarus free verilog simulator, including a microBlaze system. Icarus doesn't support smartmodels and the PPC core, of course. There's some info on my web page.
2. Are you releasing any of your Zoo tools, open source or otherwise? Forgive me if I missed links somewhere, but I didn't see any in my quick read.
3. On nice development board I like to endorse is Enterapoint's Raggedstone (and also their MiniCAN) - fairly cheap PCI Spartan3 boards.