New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

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and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Saturday, December 16, 2006
FPGA design from scratch. Part 4
Add existing code.

In the processes window double-click the Add Existing Source process. In the file browser window find the design directory and mark all files you would like to include. Repeat until all files have been added.

Check syntax

Mark the top file in the source window. In the process window expand the process Synthesis -XST.  Double-click the Check Syntax process to start the syntax check. The result will be displayed in the console window. Correct all syntax errors and when finished continue to the next step.

Generating memory blocks

In our design we need two memories. One memory to store the test program and one memory to record the test result. The memories must be dual-port memories and their size should be 1024x32. We use the same model for both memories. We will use the
Xilinx Core Generator program to generate the memory model. Let's start the program: coregen &



Click the Create new project link and follow the instructions. Don't forget to select VHDL or Verilog in the Project Options window. In the function window, open Memories and Storage->Dual Port Block. Click Customize. Specify all the options you need and click Generate to start the memory block generation. When finished there will be a number of files stored in the destination directory. See File Tree Browser display.




The file <etc_dual_port_1024x32_readme.txt> explains the usage of the different files.


 File Name
 File Usage
etc_dual_port_1024x32.edn  Electronic Data Netlist (EDN) file containing the information required to implement the module in a Xilinx FPGA.
 etc_dual_port_1024x32.v Verilog wrapper file provided to suppport functional simulation.
 etc_dual_port_1024x32.veo VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design.
 etc_dual_port_1024x32.xco CORE Generator input file containing the parameters used to regenerate a core.

We will use the file <etc_dual_port_1024x32.v> in our functional simulations. When we synthesize the design this file will be black boxed. The EDN file <etc_dual_port_1024x32.edn> will be used during the build process to generate the final FPGA design.

Synthesizing the design

Now when the whole design is completed I will do a quick
synthesis run to find out if there are any design errors left. I will use the Xilinx synthesis tool XST.
  1. Select the top module in the source window
  2. Double click the Synthesize - XST tab in the process window.
  3. Wait for the synthesis to finish.
  4. Read the errors and warnings in the console window
  5. Fix the errors and rerun the synthesis.
  6. When it runs clean you can find out the device utilization from project status report.
  7. To see the synthesized netlist double-click View RTL Schematic (see screenshot).



Simulating the design


To verify that the design is functionally correct we will use
functional verification by the means of logic simulation.  The following standards are supported in the Xilinx simulation flow:


 Description  Version
 VHDL Language  IEEE-STD-1076-1993
 VITAL Modeling Standard
 IEEE-STD-1076.4-2000
 Verilog Language  IEEE-STD-1364-2001
 Standard Delay Format  OVI 3.0
 Std_logic Data Type
 IEEE-STD-1164-93

Xilinx supports the following simulators:

 Simulator  OSCost
Xilinx ISE Simulator LiteWindows
Free
Xilinx ISE Simulator WindowsLow
Mentor ModelSim XE-III Starter WindowsFree
Mentor ModelSim XE-IIIWindows
Low
Mentor ModelSim PE (Personal Edition)
Windows
Medium
Mentor ModelSim LE (Linux Edition)
Linux
Medium
Mentor ModelSim SE (Special Edition)
Windows, Linux, Unix
High
Cadence Incisive HDL Simulator
Windows, Linux, Unix
High
Synopsys VCS-MX Linux,Unix
High

The limits for the ISE Simulator Lite are similar to the MXE-III Starter, 10,000 lines of debuggable code. Beyond this limit, the processing begins to slow down, but does not stop. The usefulness of this software is going to depend on coding style and type of simulation (either functional or timing) that is desired.

From this table you can see that there are no free simulators for Linux. It seems I have to go back to Windows or I will ask Cadence for a new evaluation license.

Here is the Xilinx simulation flow. Xilinx supports functional and timing simulations of HDL designs at five points in the HDL design flow:
  • Register Transfer Level (RTL)
  • Post-Synthesis (Pre-NGDBuild) Gate-Level
  • Post-HGDBuild (Pre-Map) Gate-Level
  • Post-Map Partial Timing (Block Delays)
  • Timing Simulations Post-Place and Route



                                                                                                   (Courtesy of Xilinx)

Top 
Next  Previous


Posted at 17:02 by svenand

James
September 20, 2011   07:57 AM PDT
 
I am part retired and had to pick up and fix a design. I found the Xilinx documentation extensive but missing basic checklists to get started. Examples:
How to provide a clock input to test
Undefined outputs probably mean undefined inputs
Minimum sources to build a circuit and get a program file out
Minimum sources to run Isim
If this check this and this etc
svenand
September 19, 2007   10:45 PM PDT
 
You have to ask Cadence for an evaluation license.

Sven
primepie
September 18, 2007   08:31 PM PDT
 
From where can we get an evaluation copy of Cadence Incisive HDL Simulator?
svenand
September 4, 2007   10:38 PM PDT
 
Yes. All the Zoo programs will be downloadable from my company web page: www.zoocad.com soon to be released.

Sven
Chuck Benz
September 4, 2007   06:02 PM PDT
 
1. I've had some success simulating Xilinx FPGA projects in the icarus free verilog simulator, including a microBlaze system. Icarus doesn't support smartmodels and the PPC core, of course. There's some info on my web page.

2. Are you releasing any of your Zoo tools, open source or otherwise? Forgive me if I missed links somewhere, but I didn't see any in my quick read.

3. On nice development board I like to endorse is Enterapoint's Raggedstone (and also their MiniCAN) - fairly cheap PCI Spartan3 boards.

\chuck
 

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