FPGA design from scratch. Part 93
The OpenRISC 1200
OpenRISC OR1200 is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL). For more information see OpenRisc 1200 Specification document.
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