New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and work
for Realtime Embedded AB.

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Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
FPGA design from scratch. Part 92
FPGA design from scratch. Part 93
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 50
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Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
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Friday, December 30, 2011
FPGA design from scratch. Part 90
Using Pmods

Pmods are small I/O interface boards that offer an ideal way to extend the capabilities of the Spartan-6 LX9 MicroBoard. Pmods communicate with system boards using 6 and 12-pin connectors. Pmods include sensors, I/O, data acquisition & conversion, connectors, external memory, and more.

Overview

The Spartan-6 LX9 MicroBoard has two connectors which allow expansion to Pmod Peripheral modules.



For more information on Pmods see: www.em.avnet.com/adipmods.

The Pmods can be ordered from Digilent. Here are some examples:


The Digilent Pmod 3-axis accelerometer

I just received the PmodACL board which I ordered from Silica before Christmas. A late Christmas present. We will connect this module to the Spartan-6 LX9 MicroBoard and build a new embedded system to make use of all the nice possibilities this board offers.


The Digilent Pmod-ACL features an Analog Devices ADXL345 Accelerometer. The ADXL345 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) measurement at up to ±16 g. Digital output data is formatted as 16-bit two's complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface.

The ADXL345 is well suited for mobile device applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (4 mg/LSB) enables measurement of inclination changes less than 1.0°.


The tutorial


This tutorial demonstrates how to interface an Avnet Spartan-6 LX9 MicroBoard to a Digilent PmodACL using the Xilinx EDK. It includes a custom designed peripheral core that provides a simple interface for software to access streaming acceleration data in all 3 dimensions as well as tap and free fall detection. We will follow the document: "Spartan-6 LX9 MicroBoard On-Ramp Tutorial, Utilizing Analog Device's Accelerometer Pmod AXI Version" from Avnet that can be downloaded from their support page.


The hardware platform

Here is a picture showing the system we are going to build. We will start with an existing project and make a copy of it as a starting point for our new project.




Copying an EDK project

We copy the LX9_AXI design (see part 65) to a new project called LX9_AXI_ACL. The following files are copied from the LX9_AXI project and renamed to LX9_AXI_ACL_system.mhs, LX9_AXI_ACL_system.xmp and LX9_AXI_ACL_system.ucf

We also have to copy the file etc/download.cmd used by iMPACT.




Edit the project file LX9_AXI_ACL_system.xmp and change the MHS and UCF file names.




Xilinx Platform Studio XPS

Start XPS and load the new project.




We will remove the following IPs:

  • SPI_FLASH
  • axi_pwm_0
  • axi_timer
  • microblaze_0_intc


Adding the ADI peripheral core

The custom AXI-based IP core is written in Verilog and is a subset of the MicroBlaze project. This core is controlled by software running on the MicroBlaze processor as well as interrupts from the accelerometer. The processor can program any of the internal accelerometer's configuration registers as well as read any of its data registers through this IP core. The IP core continuously updates position data based on interrupts received from the accelerometer.

A state machine inside cf_adxl345.v handles all of the transactions from the processor. It sits in an idle state waiting for stimulus from the processor or accelerometer. The processor can initiate reads and writes through a command register at address 0x00. Meanwhile, the state machine also responds to interrupts from the accelerometer indicating new data is available. The BW_RATE Register (0x2C) dictates the refresh rate of the accelerometer. 




The IP core is included in the file "Avnet_SP6LX9_MicroBoard_ADI_ACL_AXI_Pmod_13_2_01.zip" that can be downloaded from the Avnet support site. When unpacked it locks like this:




Adding the IP core

  1. Copy the directory cf_adxl345_core_v1_00_a to our own pcores directory.
  2. From the Project menu select <Rescan User Repositories>
  3. The IP core will show up in the User section of the IP catalog



Add the IP core to our system.




Rename the IP core to ADXL345. here is the result.




Connect all ports to external pins.




Here is the final result : LX9_AXI_ACL_system.mhs

Edit the constraints file: LX9_AXI_ACL_system.ucf




The LX9 MicroBoard


Connect the Pmod board to the connector J4.




We are ready to write the software to control our accelerometer. See next part.


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Posted at 04:15 pm by svenand

 

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