New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Bicycling
Stockholm by bike

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Friday, December 30, 2011
FPGA design from scratch. Part 90
Using Pmods

Pmods are small I/O interface boards that offer an ideal way to extend the capabilities of the Spartan-6 LX9 MicroBoard. Pmods communicate with system boards using 6 and 12-pin connectors. Pmods include sensors, I/O, data acquisition & conversion, connectors, external memory, and more.

Overview

The Spartan-6 LX9 MicroBoard has two connectors which allow expansion to Pmod Peripheral modules.



For more information on Pmods see: www.em.avnet.com/adipmods.

The Pmods can be ordered from Digilent. Here are some examples:


The Digilent Pmod 3-axis accelerometer

I just received the PmodACL board which I ordered from Silica before Christmas. A late Christmas present. We will connect this module to the Spartan-6 LX9 MicroBoard and build a new embedded system to make use of all the nice possibilities this board offers.


The Digilent Pmod-ACL features an Analog Devices ADXL345 Accelerometer. The ADXL345 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) measurement at up to ±16 g. Digital output data is formatted as 16-bit two's complement and is accessible through either a SPI (3- or 4-wire) or I2C digital interface.

The ADXL345 is well suited for mobile device applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (4 mg/LSB) enables measurement of inclination changes less than 1.0°.


The tutorial


This tutorial demonstrates how to interface an Avnet Spartan-6 LX9 MicroBoard to a Digilent PmodACL using the Xilinx EDK. It includes a custom designed peripheral core that provides a simple interface for software to access streaming acceleration data in all 3 dimensions as well as tap and free fall detection. We will follow the document: "Spartan-6 LX9 MicroBoard On-Ramp Tutorial, Utilizing Analog Device's Accelerometer Pmod AXI Version" from Avnet that can be downloaded from their support page.


The hardware platform

Here is a picture showing the system we are going to build. We will start with an existing project and make a copy of it as a starting point for our new project.




Copying an EDK project

We copy the LX9_AXI design (see part 65) to a new project called LX9_AXI_ACL. The following files are copied from the LX9_AXI project and renamed to LX9_AXI_ACL_system.mhs, LX9_AXI_ACL_system.xmp and LX9_AXI_ACL_system.ucf

We also have to copy the file etc/download.cmd used by iMPACT.




Edit the project file LX9_AXI_ACL_system.xmp and change the MHS and UCF file names.




Xilinx Platform Studio XPS

Start XPS and load the new project.




We will remove the following IPs:

  • SPI_FLASH
  • axi_pwm_0
  • axi_timer
  • microblaze_0_intc


Adding the ADI peripheral core

The custom AXI-based IP core is written in Verilog and is a subset of the MicroBlaze project. This core is controlled by software running on the MicroBlaze processor as well as interrupts from the accelerometer. The processor can program any of the internal accelerometer's configuration registers as well as read any of its data registers through this IP core. The IP core continuously updates position data based on interrupts received from the accelerometer.

A state machine inside cf_adxl345.v handles all of the transactions from the processor. It sits in an idle state waiting for stimulus from the processor or accelerometer. The processor can initiate reads and writes through a command register at address 0x00. Meanwhile, the state machine also responds to interrupts from the accelerometer indicating new data is available. The BW_RATE Register (0x2C) dictates the refresh rate of the accelerometer. 




The IP core is included in the file "Avnet_SP6LX9_MicroBoard_ADI_ACL_AXI_Pmod_13_2_01.zip" that can be downloaded from the Avnet support site. When unpacked it locks like this:




Adding the IP core

  1. Copy the directory cf_adxl345_core_v1_00_a to our own pcores directory.
  2. From the Project menu select <Rescan User Repositories>
  3. The IP core will show up in the User section of the IP catalog



Add the IP core to our system.




Rename the IP core to ADXL345. here is the result.




Connect all ports to external pins.




Here is the final result : LX9_AXI_ACL_system.mhs

Edit the constraints file: LX9_AXI_ACL_system.ucf




The LX9 MicroBoard


Connect the Pmod board to the connector J4.




We are ready to write the software to control our accelerometer. See next part.


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