The PlanAhead tool is a design and analysis product that provides an intuitive environment for the entire FPGA design and implementation process. To allow a seamless design experience for Xilinx FPGA designers, the PlanAhead tool is integrated with:
- Xilinx ISE® Design Suite software tools for synthesis and implementation
- Xilinx® Synthesis Technology (XST) tool
- CORE GeneratorTM tool
- ChipScopeTM Pro debugging tool
- ISE Simulator (ISim) tool
- XPower Analyzer tool
- FPGA Editor tool
- iMPACT device programming tool
According to Xilinx the long term plan is to promote PlanAhead to be the primary design entry GUI and it will eventually replace Project Navigator. Let's find out how good it is. We will jump in the cold water and start PlanAhead.
--> source /opt/Xilinx/13.3/ISE_DS/settings64.sh
--> planAhead &
Here is the welcome window.
Create a new project
We click the Create New Project Link to start a new project.
We have to give a name and location to our new project.
We will take the synthesized netlists from our last project.
Here are all the netlist files. Don't forget to change the top design (LX9_LXN_system.ngc)
Here are all the constraint files that will be added.
Specify our target FPGA.
Here is a summary of our new project.
PlanAhead up and running.
Adding BMM file
Block Memory Map file. A BMM file is a text file that has syntactic descriptions of how individual block RAMs constitute a contiguous logical data space. Data2MEM uses BMM files to direct the translation of data into the proper initialization form. Since a BMM file is a text file, it is directly editable.
Implement the design
The first attempt to run the implementation failed with the error message "No more space in device". The first thing we will do is to set the environment variable XIL_PAR_ENABLE_LEGALIZER
Next we have to modify the settings to improve the mapping of LUTs. Let's open the settings window.
Running the build program
Here is command to run the ngbuild:
Running the map program
This is what the mapping command looks like after changing the settings. Let's see if this works.
The implementation passed
Here are some of the results displayed in PlanAhead.
Select <Generate Bitstream> from the Program and Debug menu and add the first-stage bootloader ELF file.
Start bitstream generation.
Configure the Spartan-6 FPGA
We will start iMPACT to configure the FPGA. Select iMPACT from the Program and Debug menu.
iMPACT will start automatically and connect to the board and find the FPGA. Select the FPGA and double-click Program.
The device is programmed successfully. If iMPACT quits during startup try to delete the file impactdefaultproj.ipf.
PlanAhead is full of new features which will take some time to master. Xilinx has released a number of training videos helping us to better understand the possibilities.
PlanAhead seems like a good replacement for ISE Project Navigator. There is still a few things to fix and cleanup but I am ready to move from ISE to PlanAhead for the rest of this project.
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