New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Bicycling
Stockholm by bike

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



If you want to be updated on this weblog Enter your email here:



rss feed



 
Saturday, December 10, 2011
FPGA design from scratch. Part 85

Building our System-on-Chip design

We have now finished our embedded processor design and we have Linux running in our system. But this system isn't very useful without some extra logic performing some smart functions. It is time to start building our System-on-Chip (SOC) design. The Spartan-6 on the LX9 MicroBoard is already fully populated and there is not room for much more logic, but we will go through the principal design steps and maybe find a larger FPGA.

Returning to the ISE Project Navigator

I said in the beginning of this tutorial that we were going to skip ISE  Project Navigator altogether. That was before I had any idea on how far this tutorial was going to take us. To build our complete SOC we nead ISE Project Navigator or PlanAhed. We will start by using ISE. Here is a Xilinx tutorial that will give us a head start.

Create a new project in ISE

We will create a new project called LX9_LXN_TOP. We could have continued to build our SOC design using the project LX9_LXN and imported it to ISE directly. But as soon as we import a project from XPS this project will be locked and shouldn't be changed anymore inside XPS. Instead we will take a snapshot of our XPS embedded processor system and copy it to our new project LX9_LXN_TOP. The following files were copied from the LX9_LXN project:

  • LX9_LXN_system.xmp
  • LX9_LXN_system.mhs
  • LX9_LXN_system.ucf (renamed to LX9_LXN_system_top.ucf)


Renaming the constraints file

We will edit the LX9_LXN_system.xmp file and rename the constraint file LX9_LXN_system.ucf  to LX9_LXN_system_top.ucf. These constraints will be applied to our new top design.




Starting ISE

We are ready to start the ISE Project Navigator.

--> source /opt/Xilinx/13.3/ISE_DS/settings64.sh

--> ise &


ISE Design Suite Info Center

When we start ISE the following window pops up. This is the ISE Design Suite InfoCenter where we will find information on how to setup and run a project in ISE. We will return here when we run into problems.




And the next thing to happen is ISE starting up.




We start by creating a new project.




We select the Avnet Spartan-6 LX9 MicroBoard.




Here is the summary of our new project.




Importing our XPS design

From the Project menu select <Add Source>. By importing the LX9_LXN_system.xmp file all information about our XPS design will be retrieved.




Click OK to add the XPS design.



Our project is ready to be used.



Generating top HDL source file

There are two ways to build or top HDL design file.

  1. Instantiate the embedded XPS design in our top level HDL design file already available.
  2. Use the command <Generate Top HDL Source> in the process window.

As we don't have a top level design file we will use the <Generate Top HDL Source> command.




Adding the constraints file

  1. Select the LX9_LXN_TOP entry from the Hierachy Window. 
  2. Select  <Add Source> in the Project menu.
  3. Choose the file LX9_LXN_system_top.ucf




When this command has finished the design hierarchy looks like this:



Editing the constraints file

As we haven't changed anything in the top design we can use the old constraints file. When we start adding more IO-pins to our design we have add them to this file.




Synthesis the design

To set the process properties right-click the Synthesize - XST entry and select Process Properties.





The three settings windows allow us to change a number of synthesis options.


Run synthesis

To start the synthesis double-click the <Synthesize-XST> entry in the Process window.



Synthesis results

Here are the synthesis results from ISE Project Navigator (estimated values).



Implementing the design

The implementation phase includes the following steps:

  1. Translate
  2. Map 
  3. Place & Route

Translation

During translation, the NGDBuild program performs the following functions:

  • Performs timing specification and logical design rule checks.
  • Converts input design netlists and writes results to a single merged NGD netlist. The merged netlist describes the logic in the design as well as any location and timing constraints.
  • Adds constraints from the User Constraints File (UCF) to the merged netlist.


Mapping

The design is mapped into CLBs and IOBs. Map performs the following functions:

  • Allocates CLB (Configurable Logic Blocks) and IOB (Input Output Blocks) resources for all basic logic elements in the design.
  • Processes all location and timing constraints, performs target device optimizations, and runs a design rule check on the resulting mapped netlist.

Placing and routing the design

After the mapped design is evaluated, the design can be placed and routed. One of two place-and-route algorithms is performed during the Place and Route (PAR) process:

  • Timing-Driven PAR. PAR is run with the timing constraints specified in the input netlist, the constraints file, or both.
  • Non-Timing-Driven PAR. PAR is run, ignoring all timing constraints.


Double-click the Implement Design to start design implemenattion.



Synthesis results

Here are the final results after design implementation.




Generate Programming File

Double-click the <Generate Programming File> entry to start generating the final bitstream file (download.bit) found in the implementation directory.


Some hints

If you can't fit the design in the Spartan-6 FPGA, try the following tricks.

  • Use the latest version of ISE Project Navigator (13.3)
  • Set the environment variable  XIL_PAR_ENABLE_LEGALIZER=1
  • Modify the default settings for the different process steps (next thing to happen)

That was all for today.


Top Previous  Next




Posted at 09:21 by

 

Leave a Comment:

Name


Homepage (optional)


Comments




Previous Entry Home Next Entry