Building our System-on-Chip design
We have now finished our embedded processor design and we have Linux running in our system. But this system isn't very useful without some extra logic performing some smart functions. It is time to start building our System-on-Chip (SOC) design. The Spartan-6 on the LX9 MicroBoard is already fully populated and there is not room for much more logic, but we will go through the principal design steps and maybe find a larger FPGA.
Returning to the ISE Project Navigator
I said in the beginning of this tutorial that we were going to skip ISE Project Navigator altogether. That was before I had any idea on how far this tutorial was going to take us. To build our complete SOC we nead ISE Project Navigator or PlanAhed. We will start by using ISE. Here is a Xilinx tutorial that will give us a head start.
Create a new project in ISE
We will create a new project called LX9_LXN_TOP. We could have continued to build our SOC design using the project LX9_LXN and imported it to ISE directly. But as soon as we import a project from XPS this project will be locked and shouldn't be changed anymore inside XPS. Instead we will take a snapshot of our XPS embedded processor system and copy it to our new project LX9_LXN_TOP. The following files were copied from the LX9_LXN project:
- LX9_LXN_system.ucf (renamed to LX9_LXN_system_top.ucf)
Renaming the constraints file
We will edit the LX9_LXN_system.xmp file and rename the constraint file LX9_LXN_system.ucf to LX9_LXN_system_top.ucf. These constraints will be applied to our new top design.
We are ready to start the ISE Project Navigator.
--> source /opt/Xilinx/13.3/ISE_DS/settings64.sh
--> ise &
ISE Design Suite Info Center
When we start ISE the following window pops up. This is the ISE Design Suite InfoCenter where we will find information on how to setup and run a project in ISE. We will return here when we run into problems.
And the next thing to happen is ISE starting up.
We start by creating a new project.
We select the Avnet Spartan-6 LX9 MicroBoard.
Here is the summary of our new project.
Importing our XPS design
From the Project menu select <Add Source>. By importing the LX9_LXN_system.xmp file all information about our XPS design will be retrieved.
Click OK to add the XPS design.
Our project is ready to be used.
Generating top HDL source file
There are two ways to build or top HDL design file.
- Instantiate the embedded XPS design in our top level HDL design file already available.
- Use the command <Generate Top HDL Source> in the process window.
As we don't have a top level design file we will use the <Generate Top HDL Source> command.
Adding the constraints file
- Select the LX9_LXN_TOP entry from the Hierachy Window.
- Select <Add Source> in the Project menu.
- Choose the file LX9_LXN_system_top.ucf
When this command has finished the design hierarchy looks like this:
Editing the constraints file
As we haven't changed anything in the top design we can use the old constraints file. When we start adding more IO-pins to our design we have add them to this file.
Synthesis the design
To set the process properties right-click the Synthesize - XST entry and select Process Properties.
The three settings windows allow us to change a number of synthesis options.
To start the synthesis double-click the <Synthesize-XST> entry in the Process window.
Here are the synthesis results from ISE Project Navigator (estimated values).
Implementing the design
The implementation phase includes the following steps:
- Place & Route
During translation, the NGDBuild program performs the following functions:
- Performs timing specification and logical design rule checks.
- Converts input design netlists and writes results to a single merged NGD netlist. The merged netlist describes the logic in the design as well as any location and timing constraints.
- Adds constraints from the User Constraints File (UCF) to the merged netlist.
The design is mapped into CLBs and IOBs. Map performs the following functions:
- Allocates CLB (Configurable Logic Blocks) and IOB (Input Output Blocks) resources for all basic logic elements in the design.
- Processes all location and timing constraints, performs target device optimizations, and runs a design rule check on the resulting mapped netlist.
Placing and routing the design
After the mapped design is evaluated, the design can be placed and routed. One of two place-and-route algorithms is performed during the Place and Route (PAR) process:
- Timing-Driven PAR. PAR is run with the timing constraints specified in the input netlist, the constraints file, or both.
- Non-Timing-Driven PAR. PAR is run, ignoring all timing constraints.
Double-click the Implement Design to start design implemenattion.
Here are the final results after design implementation.
Generate Programming File
Double-click the <Generate Programming File> entry to start generating the final bitstream file (download.bit) found in the implementation directory.
If you can't fit the design in the Spartan-6 FPGA, try the following tricks.
- Use the latest version of ISE Project Navigator (13.3)
- Set the environment variable XIL_PAR_ENABLE_LEGALIZER=1
- Modify the default settings for the different process steps (next thing to happen)
That was all for today.
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