New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard
Lab2. Booting from SD card and SPI flash
Lab2. PetaLinux board bringup
Lab2. Writing userspace IO device driver
Lab2. Hardware debugging
MicroZed quick start
Installing Vivado 2014.1
Lab3. Adding push buttons to our Zynq system
Lab3. Adding an interrupt service routine
Installing Ubuntu 14.04
Installing Vivado and Petalinux 2014.2
Using Vivado 2014.2
Upgrading to Ubuntu 14.04
Using Petalinux 2014.2
Booting from SD card and SPI flash
Booting Petalinux 2014.2 from SD card
Booting Petalinux 2014.2 from SPI flash

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Monday, December 18, 2006
FPGA design from scratch. Part 3
Now it's time to get to know the Integrated Software Environment (ISE) design software from Xilinx. The first thing I would like to do is to generate the two memories needed. They have to be two-port memories, one port for writing and one port for reading. The size of the memories should be 1024x32 bits. Better start by finding the documentation from Xilinx. This is what the Xlinx design flow looks like.

                                                                                                      (Courtesy of Xilinx)

Let's begin by reading the "ISE Quick Start Tutorial". This is probably the best way to get started. Go to the pdf download page and download and unpack the file qst.zip. The tutorial contains the following sections:
  • Getting Started
  • Create a New Project
  • Create an HDL source
  • Design Simulation
  • Create Timing Constraints
  • Implement Design and Verify Constraints
  • Reimplement Design and Verify Pin Locations
  • Download Design to the Spartan-3 Demo Board
You can also download an ISE In-depth tutorial.

I will go through the whole design flow and let you know what I experience. The best way to have a question answered is to create a technical support case using the
Xilinx WebCase. Let's get going. The first thing to do is to create a new project.
  1. For Windows double click the ISE desktop icon . For Linux type <ise &> in a terminal.
  2. Select File->New Project
  3. Enter project name (ETC) and the directory path for the new project
  4. Click next
  5. Fill in all the device properties and software to use
  6. Click next
  7. I will add all the source code afterwards.
  8. Click finish.
Using Parallels Desktop

Xilinx ISE running in Windows XP




Xilinx ISE running in Ubuntu Linux.




Using VMware Fusion

I have switched to VMware Fusion. For more information read
How to install Ubuntu 7.04 using VMware Fusion in Mac OS X.



Windows versus Linux

From now on I will use the Linux version whenever I can. I don't like the blue color.

Top 
Next  Previous


Posted at 11:50 by svenand

ahlam
June 4, 2010   01:48 PM PDT
 
Dear Sir:
I'm Lecture in Computer Eng. my department have Spartan3-E XC3S500 , my work is JPEG core ,, I complete my VHDL core but I need to added color converter stage but
my FPGA is not enogh,,,I think ,,,I can use Microblaze to over come my problem,,, I start to wlork on EDK 10.1 as will as ISE 10.1 and bulit Xps file (wirte Simple C++ program
for try only ,,,to read BRAM content and display it using RS-232 but it take alot of space eleven BRAM and three embdded multiplier while I not use it , I dont know why ...can you help me to coennect my VHDL code with C++ code (color converter using Microblaze soft processor).I use OPB Bus.

alot of thanks to read my letter
Chiew
December 2, 2008   10:19 AM PST
 
Dear Mr.Svenand,

How about altera and Lattice FPGA?
I am quiet interesting on Lattice ECP2M FPGA with SERDES function and in a lower price.
Can you also do the FPGA design using Lattice FPGA?

svenand
October 7, 2007   07:13 AM PDT
 
I haven't used ISE WebPACK 7.1i. I started with ISE 8.1i and today I use ISE 9.1i. I think it is a good idea to keep updating the XIlinx software.
DeltaCodeL
September 24, 2007   08:22 PM PDT
 
I mean for implementation/Synthesize on Xilinx Virtex-4 XC4VLX25 Evaluation board from AVNET. Thanks for answers.

regards,
D
DeltaCodeL
September 24, 2007   08:21 PM PDT
 
Dear Mr. Svenand,

Do you have any experience on using xilinkcorelib on ISE Webpack 7.1i? I found some hard problem with it.
Surely waiting your useful advise.

regards,
D
 

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