This tutorial will show how to build and install a Linux OS on our MicroBlaze processor system. We will take a look at some of the Linux distributions available to us and choose the one we think is the best for our purpose. For more information about Linux in Xilinx products see Xilinx Wiki. 

Here are some candidates:

• PetaLinux from PetaLogix
  
• Free Linux distribution from Michal Simek
• Xilinx MicroBlaze Linux
• Linux for MicroBlaze mini-distro from Xillybus

Choosing PetaLinux

After taking a closer look at all the candidates I have decide to go for PetaLinux. PetaLogix has a long experience in using the MicroBlaze processor and has build many Linux distributions for this processor. PetaLinux is not a free distribution, but after talking to John Williams, the founder of PetaLogix he promised me a free evalution license for trying the PetaLinux SDK.

While we are waiting for the license, here are some documents we can study to get a better understanding of the process to build and install a Linux OS.

Building the hardware platform

We will follow the Ting Cao's blog and his advises on how to make the design fit in the Spartan-6 FPGA on the LX MicroBoard. Let's go through the whole design flow once more.

We will start a new project and use the BSB wizard to build our system.

->xps &

We select the Avnet Spartan-6 LX9 MicroBoard and let the reference clock run at 66MHz.  We will optimize for area, our biggest concern.

• Set processor frequency to 66MHz
  
• Set local memory size to 8KB
• Set cache sizes to 8KB
• Remove CDCE913_I2C and DIP_Switches_4bits peripherals
• Add axi_timer peripheral
• Enable interrupts for all peripherals
• Change the baud rate to 115200 for the uart
  

Here is the generated hardware platform and here is the corresponding mhs file.

Configuring the MicroBlaze soft processor

Right-click the micro_blaze0 entry and select Configure IP. For more information about MicroBlaze see part 60.

Select <Linux with MMU> and the click the Advanced button. Here are the settings for the General tab.

Here are the settings for the Exceptions tab.

Here are the settings for the Cache tab.

• Instruction cache size : 8KB
  
• Data cache size: 8KB
  
• Base Address: 0x8000_0000
  
• High Address: 0x83ff_ffff
  

Here are the settings for the MMU tab.

Here are the settings for the Debug tab.

Here are the settings for the PVR tab.

Interconnect Settings for BUSIF tab.

The Buses tab. This finalizes the MicroBlaze configuration.

Configure the debug_module

Right-click the debug_module entry and select Configure IP. We will disable the JTAG UART bus interface to save area.

Synthesize the design

In XPS select Hardware->Generate Netlist to synthesize the design. Here is the result from the syntesis (estimated values).

Place and route the design

In XPS select Hardware->Generate Bitstream to place and route the design and find out if it will fit in the Spartan-6 FPGA. Here is the result. It will fit.

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