Embedded ChipScope Debugging
This tutorial demonstrates how to debug and investigate AXI transactions in the embedded system using ChipScope Pro. The tutorial will show:
- How to add a ChipScope AXI Bus Monitor to our embedded processor
- Generate a FPGA Bitstream with embedded ChipScope core and SDK software application.
- How to view and interpret AXI Bus transactions using ChipScope Analyzer.
ChipScope Pro Tools Overview
As the density of FPGA devices increases, so does the impracticality of attaching test equipment probes to these devices under test. The ChipScope Pro tools integrate key logic analyzer and other test and measurement hardware components with the target design inside the supported Xilinx FPGA devices. The tools communicate with these components and provide the designer with a robust logic analyzer solution.
The ChipScope Pro Serial I/O Toolkit provides features and capabilities specific to the exploration and debug of designs that use the high-speed serial transceiver I/O capability of Xilinx FPGAs. The IBERT (internal bit error ratio tester) core and related software provides access to the high-speed serial transceivers and perform bit error ratio analysis on channels composed of these transceivers. The IBERT core supports the high-speed serial transceivers found in the Xilinx KintexTM-7, Virtex®-5, Virtex-6, and Spartan®-6 FPGA devices listed in the ISE Design Suite Product Table. For more information see the ChipScope Documents page.
Adding the ChipScope AXI Monitor Core
The AXI Monitor is a wrapper for the ChipScope Integrated Locig Analyzer (ILA) core. This monitor creates a specific ILA for monitoring AXI signals by creating trigger groups designed to be useful for debugging of the AXI bus.
In XPS open the Debug Configuration Wizard by selecting <Debug->Debug Configuration>.
Select <Monitor Hardware Signals> the click <Add ChipScope Peripheral>.
Click OK to exit. In the next window we will select which AXI interfaces we want to debug. We will probe the interface between MicroBlaze and the AXI interconnect block (microblaze_0.M_AXI_DP).
Click OK to finish the debug setup. Here is the result.
Go to Project -> Export Hardware Design to SDK and select Export Only. A new netlist and bitstream will be generated. Oops what happened. This error message tells us that the new design didn't fit in the FPGA.
Making the design smaller
We will delete the SPI_FLASH interface which we don't need right now. But before we do that we are going to keep a copy of the original design which can be reused later on. Copy file LX9_AXI_system.mhs to LX9_AXI_system_orig.mhs
We must remove some of the pins not connected anymore.
This time the bitstream generation runs without problem.
Configure the FPGA in SDK
We configure the FPGA and start the application program to make sure everything still works. We can see that LEDs intensity changes when we set the DIP switches to new values.
Analyzing the design with ChipScope Pro Analyzer
Use the command analyzer to start ChipScope.
--> analyzer &
Connecting ChipScope Pro Analyzer to target
Select Diligent USB JTAG Cable from the JTAG Chain menu. This window will pop up.
Click OK to connect. The device XC6SL9 is found and the JTAG chain is connected.
Here is the console printout.
Adding AXI signal names
We need to add the CDC file to attach names to the ChipScope signals. From the FIle menu choose Import and click Select New File. Navigate to ChipScope AXI Monitor IP directory and find the cdc file.
The Signals display window will show all signals available.
Capture waveform data
The program is running and we are ready to trigger and sample waveform data. Double_click Trigger Setup and Waveform entries to display the windows (if not already displayed).
Click the Trigger Anything (T!) button to fill the waveform window with data.
Here is the result.
Setting a trigger
This time we will trigger the waveform data capture when certain conditions occur. Open the Trigger Setup. Configure the Trigger as follows.
- In the M0:ARADDR row, change the radix to hex
- Set the value to 4002_0000
- Expand M7:RDATAACONTROL, change MON_AXI_RVALID to 1
- Set position to 512 (in the middle of the waveform window display)
- Double-click the Trigger Condition Equation, enable M0 amd M7. Click OK
This what the trigger setup looks like.
Click the Trigger button . The trigger should be centered on a valid read transacation (RVALID = 1) from address 0x4002_0000. The value in MON_AXI_RDATA should represent the status of the DIP switches on the board.
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