New Horizons









Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.



Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System
Introduction

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Introduction
Table of contents
Leon3
MicroBlaze
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Introduction
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Introduction
Table of contents
Index
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

CAD
A hardware designer's best friend
Zoo Design Platform

Linux
Installing Cobra Command Tool
A processor benchmark

Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Bicycling
Stockholm by bike

Running
The New York City Marathon

Skiing/Skating
Kittelfjall Lappland

Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Tuesday, September 27, 2011
FPGA design from scratch. Part 70
Embedded system simulation

This tutorial is divided into the following steps:
  1. Setting up the simulation environment
  2. Adding a test bench file
  3. Selecting an ELF file
  4. Generate simulation HDL files
  5. Modify the test bench file
  6. Using ISim to simulate the system
The test application will reside in block memory to provide a cycle accurate simulation. We will be using the design from the last tutorial. For more information see XPS on-line help.

Behavioral simulation
Behavioral simulation employs a high level of abstraction to model the design. A behavioral design might, for example, contain high-level operations, such as a four-bit addition operator (this is not an adder, as in a structural design), without containing specifics on how the design will be implemented. Synthesis tools then take these behavioral designs and infer the actual gate structures and connections to be used, generating a netlist description.
Behavioral simulation is performed using a pre-synthesis Hardware Description Language (HDL) description of the design. Of the three simulation methods (behavioral, structural, and timing), behavioral simulation runs the fastest but provides the least design information.
Behavioral simulation allows you to verify syntax and functionality without timing information. During design development, most verification is accomplished through behavioral simulation. Errors identified early in the design cycle are inexpensive to fix compared to functional errors identified during silicon debug. After the required functionality is achieved, structural and timing simulation methods can be implemented to obtain more detailed verification data.


Setting up the simulation environment

We have already been using ISim in a stand-alone mode and in the ISE Project Navigator (see
part 54) . This time we will run the ISim simulator inside XPS. To check the simulator settings open the Preference window under the Edit menu. Make sure the selected simulator is ISim.




Adding a testbench

A simulation testbench template file will be added when we run <Generate HDL Simulation Files>. To enable the test bench generation, open the Project Options window found in the Project menu and select Design Flow. Mark <Generate test bench template> check box, select Verilog as test bench language and Behavioral simulation models.




Select an ELF file

The simulation can take advantage of code running from BRAMs, providing a cycle accurate MicroBlaze simulation. We will be able to see and trace MicroBlaze execution. ISim will use the software application selected to initialize the BRAMs in XPS. We will use the Tutorial_Test application from the last tutorial in SDK.

We need to modify the application in SDK since writing to the UART would take too long in the simulation. Open the file main.c in SDK and comment out the print statement. When saved the file will be compiled.




Find the ELF file and add it to the Sim Executable in Project Files.




Generate behavioral simulation models

From the Simulation menu select <Generate Simulation HDL Files> to execute the following command:


The generated files will be stored in the simulation directory:




Modifying the test bench file

We will make the following changed to the auto-generated test bench file LX9_AXI_system_tb.v



................



Running a simulation

Select <Simulation->Launch HDL Simulator> to start the simulation. This command will be executed.



  1. Wait for ISim to open
  2. Find the signals we would like to look at.
  3. Right-click and select Add To Waveform Window to add these signals to the waveform display.
  4. From the Simulation menu select <Run All> to run the simulation until it finishes.




The complete test displayed in the waveform window.




Changing the time precision

ISim has full support for changing thr time precision of a simulation. The following command line switches are available for the ISim's compiler/elaborator executable fuse.

--timescale arg                Specify the default timescale for Verilog modules
--overrid_timeunit            Override timeunit for all Verilog modules, with the specified time unit in the --timescale option
--override_timeprecision Override time precision for all Verilog modules, with the specified time precision in the --timescale option
--timeprecsion_vhdl arg   Specify time precision for VHDL designs

To change the time precision we have to modify the fuse run script file: LX9_AXI_system_fuse.sh. Here is an example:




This will change the time precision for Verilog modules from the default value 100fs to 1ps.


Looking at MicroBlaze program execution

To view the disassembly of the C program code in SDK, expand the Tutorial_Test/Debug project. Double-click on the Tutorial_Test.elf executable file. Scroll down to view the disassembly code.




Select microblaze_0 to view all the MicroBlaze objects. There are a lot of valuable signals which can be observed during simulation.
Here are some.



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