New Horizons







Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company

Contact

You are welcome to contact me
and ask questions or make comments
about my blog.

View Sven Andersson's profile on LinkedIn

Content

New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
www.zynqfromscratch.com
Started February 2014
Introduction
Changes and updates
Zynq-7000 All Programmable SoC
ZedBoard and other boards
Computer platform and VirtualBox
Installing Ubuntu
Fixing Ubuntu
Installing Vivado
Starting Vivado
Using Vivado
Lab 1. Create a Zynq project
Lab 1. Build a hardware platform
Lab 1. Create a software application
Lab 1. Connect to ZedBoard
Lab 1. Run a software application
Lab 1. Benchmarking ARM Cortex-A9
Lab 2. Adding a GPIO peripheral
Lab 2. Create a custom HDL module
Lab 2. Connect package pins and implement
Lab 2. Create a software application and configure the PL
Lab 2. Debugging a software application
Running Linux from SD card
Installing PetaLinux
Booting PetaLinux
Connect to ZedBoad via ethernet
Rebuilding the PetaLinux kernel image
Running a DHCP server on the host
Running a TFTP server on the host
PetaLinux boot via U-boot
PetaLinux application development
Fixing the host computer
Running NFS servers
VirtualBox seamless mode
Mounting guest file system using sshfs
PetaLinux. Setting up a web server
PetaLinux. Using cgi scripts
PetaLinux. Web enabled application
Convert from VirtualBox to VMware
Running Linaro Ubuntu on ZedBoard
Running Android on ZedBoard

Chipotle Verification System
Introduction

Four soft-core processors
Started January 2012

Xilinx FPGA Design
New start August 2011
Problems, fixes and solutions
FPGA design from scratch. Part 51
FPGA design from scratch. Part 52
FPGA design from scratch. Part 53
FPGA design from scratch. Part 54
FPGA design from scratch. Part 55
FPGA design from scratch. Part 56
FPGA design from scratch. Part 57
FPGA design from scratch. Part 58
FPGA design from scratch. Part 59
FPGA design from scratch. Part 60
Using the Spartan-6 LX9 MicroBoard
Table of contents
FPGA design from scratch. Part 61
FPGA design from scratch. Part 62
FPGA design from scratch. Part 63
FPGA design from scratch. Part 64
FPGA design from scratch. Part 65
FPGA design from scratch. Part 66
FPGA design from scratch. Part 67
FPGA design from scratch. Part 68
FPGA design from scratch. Part 69
FPGA design from scratch. Part 70
FPGA design from scratch. Part 71
FPGA design from scratch. Part 72
FPGA design from scratch. Part 73
FPGA design from scratch. Part 74
FPGA design from scratch. Part 75
FPGA design from scratch. Part 76
FPGA design from scratch. Part 77
FPGA design from scratch. Part 78
FPGA design from scratch. Part 79
FPGA design from scratch. Part 80
FPGA design from scratch. Part 81
FPGA design from scratch. Part 82
FPGA design from scratch. Part 83
FPGA design from scratch. Part 84
FPGA design from scratch. Part 85
FPGA design from scratch. Part 86
FPGA design from scratch. Part 87
FPGA design from scratch. Part 88
FPGA design from scratch. Part 89
FPGA design from scratch. Part 90
FPGA design from scratch. Part 91
Started December 2006
Table of contents
Index
FPGA design from scratch. Part 1
FPGA design from scratch. Part 2
FPGA design from scratch. Part 3
FPGA design from scratch. Part 4
FPGA design from scratch. Part 5
FPGA design from scratch. Part 6
FPGA design from scratch. Part 7
FPGA design from scratch. Part 8
FPGA design from scratch. Part 9
FPGA design from scratch. Part 10
FPGA design from scratch. Part 11
FPGA design from scratch. Part 12
FPGA design from scratch. Part 13
FPGA design from scratch. Part 14
FPGA design from scratch. Part 15
FPGA design from scratch. Part 16
FPGA design from scratch. Part 17
FPGA design from scratch. Part 18
FPGA design from scratch. Part 19
FPGA design from scratch. Part 20
FPGA design from scratch. Part 21
FPGA design from scratch. Part 22
FPGA design from scratch. Part 23
FPGA design from scratch. Part 24
FPGA design from scratch. Part 25
FPGA design from scratch. Part 26
FPGA design from scratch. Part 27
FPGA design from scratch. Part 28
FPGA design from scratch. Part 29
FPGA design from scratch. Part 30
FPGA design from scratch. Part 31
FPGA design from scratch. Part 32
FPGA design from scratch. Part 33
FPGA design from scratch. Part 34
FPGA design from scratch. Part 35
FPGA design from scratch. Part 36
FPGA design from scratch. Part 37
FPGA design from scratch. Part 38
FPGA design from scratch. Part 39
FPGA design from scratch. Part 40
FPGA design from scratch. Part 41
FPGA design from scratch. Part 42
FPGA design from scratch. Part 43
FPGA design from scratch. Part 44
FPGA design from scratch. Part 45
FPGA design from scratch. Part 46
FPGA design from scratch. Part 47
FPGA design from scratch. Part 48
FPGA design from scratch. Part 49
FPGA design from scratch. Part 50
Acronyms and abbreviations
Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5
CAD
A hardware designer's best friend
Zoo Design Platform
Linux
Installing Cobra Command Tool
A processor benchmark
Mac
Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true
Running
The New York City Marathon
Skiing/Skating
Kittelfjäll Lappland
Tour skating in Sweden and around the world
Top
Introduction
SSSK
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Calendar
Links
Books, photos, films and videos
Weather forecasts

Travel
38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
Kittelfjäll Lapland
Landsort Art Walk
Skating on thin ice

Books
100 Power Tips for FPGA Designers

Favorites
Adventures in ASIC
ChipHit
Computer History Museum
DeepChip
Design & Reuse
Dilbert
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
Embedded.com
EmbeddedRelated.com
FPGA Arcade
FPGA Blog
FPGA Central
FPGA CPU News
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
OpenCores
Simplehelp
SOCcentral
World of ASIC



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Monday, December 25, 2006
FPGA design from scratch. Part 2
The design object

Now when we have the
infrastructure in place it is time to define a design object. The picture shows a simple block diagram of the hardware design I plan to implement in a FPGA.



The design is an embedded test controller (ETC) that will run a JTAG test program stored in the test program memory. The test result will be stored in the test result memory and when the test has finished the result can be read and compared to the expected data. If the test passes a green led will be turned on and if the test fails a red led will light up.  Here is a short discription of all the steps to run a test:
  1. The MicroBlaze reads the test program from the program memory and writes it to the test program memory.
  2. The MicroBlaze writes to the control register to setup the ETC
  3. The MicroBlaze  writes to the control register to start the  test.
  4. The test generator executes the test program and generates test data that will be sent through the test configurator to the test object.
  5. The test object sends data back that will be recorded by the test recorder and stored in the test result memory.
  6. When the test is finished an interrrupt is sent to the MicroBlaze.
  7. The MicroBlaze will write to the control register to stop the test.
  8. The MicroBlaze will read the test result memory and compare the data to the expected data stored in the program memory.
  9. If the recorded data matches the expected data the test has passed.

Memory map

Register/Memory Name
Size Access Address
Test Program RAM
1024x32 Write  
Test Result RAM
1024x32 Read  
Control 32 Read/Write Baseaddr+0x0
Status 32 Read Baseaddr+0x4
Execute 32 Read/Write Baseaddr+0x8
Debug  32 Read Baseaddr+0xc

Instruction set

The test generator reads instructions from the test program RAM and executes them sequentially. The following instructions have been implemented.

Op code
Description
4'b0000 No operation
4'b0001 Generate test reset 1 (TSTSZ low for x TCK cycles)
4'b0010 Generate test reset 2 (TMS high for x TCK cycles)
4'b0011 Load JTAG instruction register
4'b0100 Load JTAG data register
4'b0101 Load instruction register and data register
4'b0110 Load data register and instruction register
4'b0111 Load data register and pause in pause-dr 
4'b1000 Load data register (continue from pause-dr)
4'b1001 Load data register (continue from pause-dr and stop in pause-dr)
4'b1010 Wait in Run-Test-Idle state a number of TCK cycles
4'b1011 Pause in Run-Test-Idle state
4'b1100 End of test


Program example

Here is an example on how to program the ETC. This program reads the identification code from the IDCODE register by loading the IDCODE instruction and shift out the 32 bit identification code.

parameter INSTRUCTION_LENGTH                  = 4;
parameter DATA_LENGTH                         = 32;
parameter IDCODE                              = 4'b0010;
parameter ALL_TDO_DATA                        = 2'b0;
parameter DEVICE_IDCODE                       = 32'h14012049;

SetTdoRecordingMode      (ALL_TDO_DATA);
TestResetKeepingTrstzLow (10);
LoadInstruction          (INSTRUCTION_LENGTH,IDCODE);
SetExpectedData          (INSTRUCTION_LENGTH,4'b0001);
ReadWriteDataRegister    (DATA_LENGTH,32'h0);
SetExpectedData          (DATA_LENGTH,DEVICE_IDCODE);
EndOfTestProgram;


Design language


Most of the design has already been coded in
Verilog HDL. What is left to implement are the two memory blocks.

Top
  Next  Previous


Posted at 14:58 by svenand

Name
May 8, 2009   12:16 PM PDT
 
Can I same tutor in pdf format ....

Regards

Veerendra Jonnalagadda
jveerendra@gmail.com
eshetu admasu
October 14, 2008   08:47 AM PDT
 
hello mr.anderson, i am appriciatong ur kindness to share ur knowladge. i am using ur tutorials.
keep it up !!!!!!!!!!
eshetu ,ethiopia
soon
July 9, 2008   12:18 PM PDT
 
it would have been more useful if this comes out s a book..
Vitesh
May 21, 2008   12:50 PM PDT
 
hello Mr. Anderson
I am Vitesh

I was successfully able to work with virtex 4 (ML402 and VIODC boards ) / MATLAB simulik in implementing the video processing algorithms . however I was wondering if there is a way to do it using VHDL or C language. If so can you plz mail me the necessary documentation or the demo code in C or in VHDL mail me on vitesh.jaiswal@gmail.com
svenand
April 28, 2008   08:47 PM PDT
 
Hi,

I haven't made a pdf document. This site is a living document.

Sven
Sharan
April 28, 2008   02:48 PM PDT
 
Hi,

I was wondering if you have a single document (in pdf etc.) that I can read, instead of going through the html pages?

Regards
gheorghe DRAGAN
January 28, 2008   07:57 AM PST
 
How about TI MSP 430 series and software they are using?
Christian
November 2, 2007   01:12 AM PDT
 
Tjena Mr. Andersson,

are you being sarcastic? :) If you dont provide the source code how can we go on with the tutorial?

Thanks,

Chris
svenand
September 1, 2007   07:30 AM PDT
 
I keep one secret in this story. I will not reveal the source code of my design object.
Tom Pham
August 31, 2007   07:13 PM PDT
 
Hello Mr. Andersson

In your tutorial I saw you mention about

"Design language

Most of the design has already been coded in Verilog HDL. What is left to implement are the two memory blocks. " However I could not find any source code to add it in to project as your tutorial mention in Part 4. Please advise where I can find those files.

Thanks,
Tom
 

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