New Horizons

Welcome to my blog

My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company


You are welcome to contact me
and ask questions or make comments
about my blog.


New Horizons
What's new
Starting a blog
Writing a blog
Using an RSS reader

Zynq Design From Scratch
Started February 2014
1 Introduction
Changes and updates
2 Zynq-7000 All Programmable SoC
3 ZedBoard and other boards
4 Computer platform and VirtualBox
5 Installing Ubuntu
6 Fixing Ubuntu
7 Installing Vivado
8 Starting Vivado
9 Using Vivado
10 Lab 1. Create a Zynq project
11 Lab 1. Build a hardware platform
12 Lab 1. Create a software application
13 Lab 1. Connect to ZedBoard
14 Lab 1. Run a software application
15 Lab 1. Benchmarking ARM Cortex-A9
16 Lab 2. Adding a GPIO peripheral
17 Lab 2. Create a custom HDL module
18 Lab 2. Connect package pins and implement
19 Lab 2. Create a software application and configure the PL
20 Lab 2. Debugging a software application
21 Running Linux from SD card
22 Installing PetaLinux
23 Booting PetaLinux
24 Connect to ZedBoad via ethernet
25 Rebuilding the PetaLinux kernel image
26 Running a DHCP server on the host
27 Running a TFTP server on the host
28 PetaLinux boot via U-boot
29 PetaLinux application development
30 Fixing the host computer
31 Running NFS servers
32 VirtualBox seamless mode
33 Mounting guest file system using sshfs
34 PetaLinux. Setting up a web server
35 PetaLinux. Using cgi scripts
36 PetaLinux. Web enabled application
37 Convert from VirtualBox to VMware
38 Running Linaro Ubuntu on ZedBoard
39 Running Android on ZedBoard
40 Lab2. Booting from SD card and SPI flash
41 Lab2. PetaLinux board bringup
42 Lab2. Writing userspace IO device driver
43 Lab2. Hardware debugging
44 MicroZed quick start
45 Installing Vivado 2014.1
46 Lab3. Adding push buttons to our Zynq system
47 Lab3. Adding an interrupt service routine
48 Installing Ubuntu 14.04
49 Installing Vivado and Petalinux 2014.2
50 Using Vivado 2014.2
51 Upgrading to Ubuntu 14.04
52 Using Petalinux 2014.2
53 Booting from SD card and SPI flash
54 Booting Petalinux 2014.2 from SD card
55 Booting Petalinux 2014.2 from SPI flash
56 Installing Vivado 2014.3

Chipotle Verification System

EE Times Retrospective Series
It all started more than 40 years ago
My first job as an electrical engineer
The Memory (R)evolution
The Microprocessor (R)evolution

Four soft-core processors
Started January 2012
Table of contents
OpenRISC 1200
Nios II

Using the Spartan-6 LX9 MicroBoard
Started August 2011
Table of contents
Problems, fixes and solutions

FPGA Design From Scratch
Started December 2006
Table of contents
Acronyms and abbreviations

Actel FPGA design
Designing with an Actel FPGA. Part 1
Designing with an Actel FPGA. Part 2
Designing with an Actel FPGA. Part 3
Designing with an Actel FPGA. Part 4
Designing with an Actel FPGA. Part 5

A hardware designer's best friend
Zoo Design Platform

Installing Cobra Command Tool
A processor benchmark

Porting a Unix program to Mac OS X
Fixing a HyperTerminal in Mac OS X
A dream come true

Stockholm by bike

The New York City Marathon

Kittelfjall Lappland

Tour skating in Sweden and around the world
Wild skating
Tour day
Safety equipment
A look at the equipment you need
Skate maintenance
Books, photos, films and videos
Weather forecasts

38000 feet above see level
A trip to Spain
Florida the sunshine state

Photo Albums
Seaside Florida
Ronda Spain
Sevilla Spain
Cordoba Spain
Alhambra Spain
KittelfjÀll Lapland
Landsort Art Walk
Skating on thin ice

100 Power Tips for FPGA Designers

Adventures in ASIC
Computer History Museum
Design & Reuse
d9 Tech Blog
EDA Cafe
EDA DesignLine
Eli's tech Blog
FPGA Arcade
FPGA Central
FPGA developer
FPGA Journal
FPGA World
Lesley Shannon Courses
Mac 2 Ubuntu
Programmable Logic DesignLine
World of ASIC

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Monday, December 25, 2006
FPGA design from scratch. Part 2
The design object

Now when we have the
infrastructure in place it is time to define a design object. The picture shows a simple block diagram of the hardware design I plan to implement in a FPGA.

The design is an embedded test controller (ETC) that will run a JTAG test program stored in the test program memory. The test result will be stored in the test result memory and when the test has finished the result can be read and compared to the expected data. If the test passes a green led will be turned on and if the test fails a red led will light up.  Here is a short discription of all the steps to run a test:
  1. The MicroBlaze reads the test program from the program memory and writes it to the test program memory.
  2. The MicroBlaze writes to the control register to setup the ETC
  3. The MicroBlaze  writes to the control register to start the  test.
  4. The test generator executes the test program and generates test data that will be sent through the test configurator to the test object.
  5. The test object sends data back that will be recorded by the test recorder and stored in the test result memory.
  6. When the test is finished an interrrupt is sent to the MicroBlaze.
  7. The MicroBlaze will write to the control register to stop the test.
  8. The MicroBlaze will read the test result memory and compare the data to the expected data stored in the program memory.
  9. If the recorded data matches the expected data the test has passed.

Memory map

Register/Memory Name
Size Access Address
Test Program RAM
1024x32 Write  
Test Result RAM
1024x32 Read  
Control 32 Read/Write Baseaddr+0x0
Status 32 Read Baseaddr+0x4
Execute 32 Read/Write Baseaddr+0x8
Debug  32 Read Baseaddr+0xc

Instruction set

The test generator reads instructions from the test program RAM and executes them sequentially. The following instructions have been implemented.

Op code
4'b0000 No operation
4'b0001 Generate test reset 1 (TSTSZ low for x TCK cycles)
4'b0010 Generate test reset 2 (TMS high for x TCK cycles)
4'b0011 Load JTAG instruction register
4'b0100 Load JTAG data register
4'b0101 Load instruction register and data register
4'b0110 Load data register and instruction register
4'b0111 Load data register and pause in pause-dr 
4'b1000 Load data register (continue from pause-dr)
4'b1001 Load data register (continue from pause-dr and stop in pause-dr)
4'b1010 Wait in Run-Test-Idle state a number of TCK cycles
4'b1011 Pause in Run-Test-Idle state
4'b1100 End of test

Program example

Here is an example on how to program the ETC. This program reads the identification code from the IDCODE register by loading the IDCODE instruction and shift out the 32 bit identification code.

parameter INSTRUCTION_LENGTH                  = 4;
parameter DATA_LENGTH                         = 32;
parameter IDCODE                              = 4'b0010;
parameter ALL_TDO_DATA                        = 2'b0;
parameter DEVICE_IDCODE                       = 32'h14012049;

SetTdoRecordingMode      (ALL_TDO_DATA);
TestResetKeepingTrstzLow (10);
LoadInstruction          (INSTRUCTION_LENGTH,IDCODE);
SetExpectedData          (INSTRUCTION_LENGTH,4'b0001);
ReadWriteDataRegister    (DATA_LENGTH,32'h0);
SetExpectedData          (DATA_LENGTH,DEVICE_IDCODE);

Design language

Most of the design has already been coded in
Verilog HDL. What is left to implement are the two memory blocks.

  Next  Previous

Posted at 14:58 by svenand

May 8, 2009   12:16 PM PDT
Can I same tutor in pdf format ....


Veerendra Jonnalagadda
eshetu admasu
October 14, 2008   08:47 AM PDT
hello mr.anderson, i am appriciatong ur kindness to share ur knowladge. i am using ur tutorials.
keep it up !!!!!!!!!!
eshetu ,ethiopia
July 9, 2008   12:18 PM PDT
it would have been more useful if this comes out s a book..
May 21, 2008   12:50 PM PDT
hello Mr. Anderson
I am Vitesh

I was successfully able to work with virtex 4 (ML402 and VIODC boards ) / MATLAB simulik in implementing the video processing algorithms . however I was wondering if there is a way to do it using VHDL or C language. If so can you plz mail me the necessary documentation or the demo code in C or in VHDL mail me on
April 28, 2008   08:47 PM PDT

I haven't made a pdf document. This site is a living document.

April 28, 2008   02:48 PM PDT

I was wondering if you have a single document (in pdf etc.) that I can read, instead of going through the html pages?

November 2, 2007   01:12 AM PDT
Tjena Mr. Andersson,

are you being sarcastic? :) If you dont provide the source code how can we go on with the tutorial?


September 1, 2007   07:30 AM PDT
I keep one secret in this story. I will not reveal the source code of my design object.
Tom Pham
August 31, 2007   07:13 PM PDT
Hello Mr. Andersson

In your tutorial I saw you mention about

"Design language

Most of the design has already been coded in Verilog HDL. What is left to implement are the two memory blocks. " However I could not find any source code to add it in to project as your tutorial mention in Part 4. Please advise where I can find those files.


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