My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
In my spare time I write this blog
and I hope it will inspire others to
learn more about this fantastic field.
I live in Stockholm Sweden and have
my own company
You are welcome to contact me
and ask questions or make comments
about my blog.
Now when we have the infrastructure in place it is time to define a design object. The picture shows a simple block diagram of the hardware design I plan to implement in a FPGA.
The design is an embedded test controller (ETC) that will run a JTAG test program stored in the test program memory. The test result will be stored in the test result memory and when the test has finished the result can be read and compared to the expected data. If the test passes a green led will be turned on and if the test fails a red led will light up. Here is a short discription of all the steps to run a test:
The MicroBlaze reads the test program from the program memory and writes it to the test program memory.
The MicroBlaze writes to the control register to setup the ETC
The MicroBlaze writes to the control register to start the test.
The test generator executes the test program and generates test data that will be sent through the test configurator to the test object.
The test object sends data back that will be recorded by the test recorder and stored in the test result memory.
When the test is finished an interrrupt is sent to the MicroBlaze.
The MicroBlaze will write to the control register to stop the test.
The MicroBlaze will read the test result memory and compare the data to the expected data stored in the program memory.
If the recorded data matches the expected data the test has passed.
Test Program RAM
Test Result RAM
The test generator reads instructions from the test program RAM and executes them sequentially. The following instructions have been implemented.
Generate test reset 1 (TSTSZ low for x TCK cycles)
Generate test reset 2 (TMS high for x TCK cycles)
Load JTAG instruction register
Load JTAG data register
Load instruction register and data register
Load data register and instruction register
Load data register and pause in pause-dr
Load data register (continue from pause-dr)
Load data register (continue from pause-dr and stop in pause-dr)
Wait in Run-Test-Idle state a number of TCK cycles
Pause in Run-Test-Idle state
End of test
Here is an example on how to program the ETC. This program reads the identification code from the IDCODE register by loading the IDCODE instruction and shift out the 32 bit identification code.
hello mr.anderson, i am appriciatong ur kindness to share ur knowladge. i am using ur tutorials.
keep it up !!!!!!!!!!
soon July 9, 2008 12:18 PM PDT
it would have been more useful if this comes out s a book..
Vitesh May 21, 2008 12:50 PM PDT
hello Mr. Anderson
I am Vitesh
I was successfully able to work with virtex 4 (ML402 and VIODC boards ) / MATLAB simulik in implementing the video processing algorithms . however I was wondering if there is a way to do it using VHDL or C language. If so can you plz mail me the necessary documentation or the demo code in C or in VHDL mail me on email@example.com
svenand April 28, 2008 08:47 PM PDT
I haven't made a pdf document. This site is a living document.
Sharan April 28, 2008 02:48 PM PDT
I was wondering if you have a single document (in pdf etc.) that I can read, instead of going through the html pages?
How about TI MSP 430 series and software they are using?
Christian November 2, 2007 01:12 AM PDT
Tjena Mr. Andersson,
are you being sarcastic? :) If you dont provide the source code how can we go on with the tutorial?
svenand September 1, 2007 07:30 AM PDT I keep one secret in this story. I will not reveal the source code of my design object.
Tom Pham August 31, 2007 07:13 PM PDT
Hello Mr. Andersson
In your tutorial I saw you mention about
Most of the design has already been coded in Verilog HDL. What is left to implement are the two memory blocks. " However I could not find any source code to add it in to project as your tutorial mention in Part 4. Please advise where I can find those files.